TTEP Tutorial by Prof. Li-C. Wang (UC Santa Barbara) 

The emerge of Large Language Model (LLM) have significantly impacted our view for applying Machine Learning (ML) in semiconductor test. Recent LLMs include Codex focusing on code generation and InstructGPT for capturing user intent. Their successor, ChatGPT, had demonstrated remarkable performance for engaging in dialog on a wide variety of topics, answering questions, and generating code. With these recent LLM technological developments, this tutorial provides an integrated view of how to apply LLM in semiconductor test data analytics. In particular, we will cover introductory materials for LLMs and share our experience of leveraging the power of LLMs to build an AI Agent in semiconductor test domain. We will discuss a new paradigm called Decision-Support ML (DSML). In our domain, DSML is applied in an iterative exploration process for an engineer to learning knowledge from data. We will discuss common test data analytics practices as well as the latest LLM technologies and how they fit into our DSML view to build an end-to-end LLM-Assisted AI solution. Industrial case studies will be provided to illustrate the concepts taught in this tutorial.

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial1

TTEP Tutorial by Mark Tehranipoor (University of Florida) & Farimah Farahmandi (University of Florida)

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial2

TTEP Tutorial by Lee Harrison (Siemens EDA) & Peter Orlando (Siemens EDA)

In this tutorial, we will proceed to give an overview of the exciting field of AI and HPC. It will cover the critical and special characteristics and the architecture of the popular AI chips. Next we will summarize the features of the AI chips from design-for-test (DFT) perspective and introduce the DFT technologies that can help testing AI chips. We will also look at how the shift to 2.5D and 3D including Chiplet development is changing the industry and the adding new challenges for the DFT community Finally, we will present a few case studies on how DFT is implemented in the real AI chips. We will also present some of the functional monitoring techniques that are available today. An overall architecture showing how functional monitoring can be implemented and how the monitor data can be used to manage in-life capabilities. Finally, we will present a few case studies on how DFT is implemented in the real AI chips.

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial3

TTEP Tutorial by Paolo Bernardi (Politecnico di Torino)

Since the inception of IC design in the mid-1960s, IC test has been an integral part of the manufacturing process. Initially, tests were of the Functional nature of either randomly generated or created from verification suites. But as chips got larger, testing required a more targeted approach, one that needed to be easily replicated from one design to another. This led to the invention of Structural methods like scan, which made designs combinational and simplified the test generation process. After almost 50 years, the testing scenario evolved just slightly, following technology trends currently led by the complexity of the circuits under test and the field of use (i.e., Automotive). Structural methods are still dominant, at least during the manufacturing test process, but Functional techniques are now recognized to be: (i) Useful to complement structural techniques during the manufacturing test process, such as System Level Test. (ii) Able to mitigate thermal issues that may originate during stress phases like along Burn-In, thus enabling test data collection during this phase. (iii) Very helpful along with the useful life of the components in the mission field, to run a not destructive self-test and also able to capture and store information, opening possibilities for Silicon Lifetime Management (SLM). The talk will provide basic and practical information about some today-relevant functional techniques in the field of Software-Based Self-Test (SBST), Burn-In Functional Stress/Test (TDBI), and System-Level Test (SLT). Automotive chip case studies from STMicroelectronics will be illustrated.

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial4

TTEP Tutorial by Drew Walton (Microsoft) & Yogesh Varma (Intel)

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial5

TTEP Tutorial by Stephen Sunter (Siemens EDA)

This tutorial explores systematic analog and mixed-signal design-for-test, including analog fault/defect simulation. We will review widely-used basic DfT techniques, fault simulation, IEEE 1149.1/4/6/7, 1687, and ISO 26262 metrics, then BIST for ADC/DAC, PLL, SerDes/DDR, and random analog. Essential principles of practical analog BIST are presented, then practical DfT techniques, from quicker analog defect simulation, to DfT that emphasizes simplicity, diagnosis, reuse, and automation. Detailed summaries of the Analog Defect Coverage and Analog Test Access standards (IEEE P2427, P1687.2) are included, as they approach completion thanks to the effort of many people since 2014. The tutorial concludes with an introduction to digital scan-based DfT that enables ATPG for near-instantaneous high-coverage structural testing of analog circuits.

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial6

TTEP Tutorial by Sandeep Goel (TSMC) & Yervant Zorian (Synopsys)

Advancements in process technology have enabled the creation of chips with billions of transistors, significantly enhancing power and performance for high-performance computing (HPC) and AI applications. This complexity has spurred the development of various 3D integration and packaging techniques utilizing multi-die/chiplet-based designs. Advanced 3D integration technologies allow for the construction of multi-die systems, each offering specific advantages and trade-offs in terms of performance, application, and cost. Similar to traditional chips, all 3DICs must be rigorously tested for manufacturing defects. This includes Known-Good Die (KGD) testing before stacking, Known-Good-Stack (KGS) testing after stacking, final tests, and system-level tests. Furthermore, given the complexity of the stacking process, in-silicon monitoring solutions are necessary to continuously check silicon health during in-field operation. This tutorial offers an overview of the advanced packaging technologies and explores the associated test flow challenges. An example of how the 3Dblox open standard simplifies the description of a 3D stack, enabling interoperability between EDA tools and allowing various test optimizations, is presented. Additionally, it covers various Design-for-Test (DFT) schemes, sensors/monitors and embedded test & repair solutions to facilitate efficient testing across different packaging configurations.

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial7

TTEP Tutorial by Adit Singh (Auburn University)

New types of failures that evade traditional scan DFT tests are increasingly observed in advanced SoC designs. Recent reports from Google and Meta have highlighted significant levels of silent data corruption in large-scale data centers. These failures have been associated with specific processor cores in the processor networks, suggesting faulty or unstable hardware, rather than malfunction caused by random environmental noise. Although the limitations of structural scan tests have led to the growing adoption of System-Level Tests (SLT) as a final manufacturing screen in recent years, even these expensive functional tests allow significant test escapes that can cause failures during operation. We argue that timing marginalities, caused by manufacturing process variations, are a primary contributor to both SLT fallout and in-field failures. To support this claim, we first review existing scan-based timing tests, including recent developments in cell-aware and timing-aware methodologies, highlighting their capabilities and limitations. We then explain why these tests often fail to detect timing-related defects from process variation. Finally, we present research validated using production test data from Intel's 14nm FinFET technology that demonstrates how modifying voltage and timing conditions during scan and system-level testing can improve detection of circuits with marginal timing and thereby minimize failures in operation.

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial8

TTEP Tutorial by Arani Sinha (Intel), Alberto Bosio (Ecole Centrale de Lyon) & Ernesto Sanchez (Politecnico di Torino)

AI applications have become extremely popular in everyday life as well as in the industry, but at the same time their complexity requires dedicated hardware accelerators deployed in cloud-based Data Centers. Recent studies by hyperscalers have revealed that Data Center hardware can experience failures leading to Silent Data Corruption (SDC). SDCs can impact AI workloads both during training and inference and, eventually, cause huge revenue loss. The tutorial will start with an introduction to Silent Data Corruption. The tutorial will then offer an overview of the landscape of artificial intelligence, focusing on basic frameworks such as Multi Layer Perceptron, Deep Neural Networks, and Transformers. The following phase of the tutorial will focus on AI architectures such as Tensor Processing Unit from Google, Gaudi architecture from Intel, and GPU architecture from Nvidia. After that, the impact of manufacturing defects on training and inference will be discussed and fault injection techniques developed for studying the impact of defects will be described. Next, developments in functional and structural testing of AI architectures will be discussed. Finally, such resilience techniques as gradient clipping, algorithmic fault tolerance, and tensor processing monitor will be described. The tutorial will end with a brief discussion on open research problems in this space.

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial9

TTEP Tutorial by Debendra Das Sharma (Intel) & Yervant Zorian (Synopsys)

High-performance and power efficiency needs of emerging workloads demand on-package integration of heterogeneous processing units, memory, and electrical and optical interconnects. Applications such as artificial intelligence/machine learning, data analytics, 5G, automotive, and high-performance computing are driving these demands to meet the needs of cloud computing, intelligent edge, enterprise, client, and hand-held computing infrastructure. On-package interconnects are a critical component to deliver the power-efficient performance with the right feature set in this evolving landscape.

UCIe is an open industry standard with a fully specified stack that comprehends plug-and-play interoperability of chiplets on a package; like the seamless interoperability on board with well-established and successful off-package interconnect standards such PCI Express®, Universal Serial Bus (USB)®, and Compute Express Link (CXL)®. Recently, UCIe added significant enhancements for the test and debug infrastructure to work seamlessly across the silicon life cycle. In this tutorial, we will discuss the usages and key metrics of UCIe, both planar as well as 3D. We will delve into electrical, packaging, protocol, RAS, debug, testability, manageability, and software aspects along with the compliance and interoperability mechanisms. This will address inter die and intra die requirements. The intended audience of this tutorial are architects, SoC developers, chip designers, DFT & test engineers, researchers, and system integrators.

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial10

TTEP Tutorial by Mehdi Tahoori (IMEC)

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial11

TTEP Tutorial by Amit Pandey (Amazon), Karthik Natarjan (Synopsys) & Sankaran Menon (Ericsson)

Infield Test and Debug provides deeper insights into the system behavior and structural quality while the system is running in mission-mode. It provides a non-intrusive method for testing and debug of complex computer systems. This is specifically useful in mission-critical applications such as; space applications, ADAS (Advanced Driver Assistance Systems), for various industrial/robotic applications as well as virtually all real-time and data-center/AI applications. In this tutorial we will establish the motivation for Infield system Test & Debug, cover the various testing and debug techniques that are available today. We will then introduce the Infield system testing and debug mechanisms available for the closed-chassis systems using USB Type-C, PCIe and any other high-speed interfaces. We will conclude with results from an Infield system test and Debug used in real-world applications across the various industries.

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial12

While the ITC community has had a long history with the topics of Machine Learning and Artificial Intelligence, the amazing recent developments in AI have surprised even us.  These have led to dire projections from some corners that AI will take our jobs, but it seems much more likely that AI will become an important tool for DFT and test engineers, perhaps even marking an inflection point in the history of the profession.  This panel has two main objectives: the first is to discuss the general topic of how AI can practically be incorporated into our day jobs, and the second is to give the audience some real-time experience with a lightly-trained test chatbot who will be one of the panelists (and yes, we do appreciate the irony of this chatbot taking the job of some other panelist, but that’s unavoidable for our purpose here).

Richard Rodell Jr. is a distinguished engineer at Infineon Technologies, holding the position since August 2021, while also serving as the Vice President of Test Engineering since April 2020. Previously at Cypress Semiconductor, Richard has extensive experience in test engineering, spanning from roles as Test Engineering Senior Director and Vice President of Test Engineering to Test Engineering Manager and Senior Technical Lead. Richard's expertise includes worldwide management of test engineering for various memory types and system-on-chip (SoC) technologies. Richard earned a Bachelor of Science in Electrical Engineering from Marquette University in 1992.

Organizer: Carl Moore, yieldHUB (IRL) 

The rapid adoption of Artificial Intelligence (AI) across semiconductor manufacturing is redefining how data is interpreted, decisions are made, and quality is assured. This panel will explore real-world use cases of AI applied across critical manufacturing stages, with emphasis on Wafer Acceptance Testing (WAT), Wafer Probe, and Final Test processes.

WAT data provides early indicators of process variability and potential yield excursions. AI models leveraging this data can detect subtle correlations and anomalies across fab lots, offering predictive insights long before wafer test. At wafer probe, machine learning models optimize binning and identify systematic test escapes, improving inline yield monitoring. In final test, AI-driven adaptive test strategies help dynamically adjust test limits, enhancing outgoing quality while reducing test time and cost.

As quality expectations intensify—especially for automotive, medical, and aerospace applications—AI offers a path to proactive quality assurance by learning from vast and multidimensional datasets. Instead of retrospective analyses, AI enables real-time interventions, anomaly detection, and root cause attribution with unprecedented accuracy.

However, deploying AI in test and manufacturing is not a plug-and-play exercise. It demands data governance, model interpretability, and strong domain-context fusion. The industry faces a growing need for professionals who can straddle the worlds of data science and semiconductor engineering. Tomorrow’s test teams will require data scientists who also understand transistor physics and reliability metrics as fluently as they write software code.

Panelists from industry and academia will share insights, lessons learned, and forward-looking perspectives on how AI is redefining manufacturing strategies, infrastructure requirements, and talent needs. This discussion aims to provide attendees with a pragmatic understanding of AI integration challenges and the value proposition it offers across the semiconductor value chain.

Matheus Trevisan Moreira began his career as a professor in Brazil before transitioning to the technology industry, where he has held key technical leadership roles across startups, Apple, and Meta. He currently serves as a tech lead at Meta, driving the development of advanced silicon architectures and accelerators for AI workloads. Matheus is the author of over 100 peer-reviewed scientific publications, holds 12 patents, and has received multiple awards from IEEE and ACM for his contributions to computing and electronic design. His current interests focus on applying AI to accelerate and optimize silicon design, and on architecting systems for next-generation AI applications.

Organizer: Davide Appello, Technoprobe (IT)

As advanced packaging technologies redefine the boundaries of semiconductor performance, the complexity of testing these devices grows exponentially. This panel invites industry leaders to identify and defend what they see as the most critical challenge in testing next-generation packaged systems. Panelists will choose from seven pivotal topics: DFT infrastructure for multi-die systems, kiloampere current delivery during test and SLT, thermal management strategies, the sustainability of shift-left screening, integration of optical engines, advanced packaging for automotive and integration of high-bandwidth memories (HBM).Through a dynamic exchange of perspectives, the panel will explore how these challenges impact product quality, time-to-market, and cost efficiency. Attendees will gain insight into emerging test methodologies, infrastructure requirements, and strategic trade-offs shaping the future of semiconductor test. This session is designed to provoke thoughtful debate and offer actionable takeaways for engineers, technologists, and decision-makers navigating the evolving landscape of advanced packaging.

Dr. Jeorge S. Hurtarte is currently Senior Director and Principal Marketing Strategist in the Semiconductor Compute Test Division at Teradyne. Jeorge has held various technical, management and executive positions at Teradyne, Lam Research, LitePoint, TranSwitch, and Rockwell Semiconductors. Jeorge is in the Advisory Board of SEMI of North America and serves as co-chair of the IEEE Heterogeneous Integration Roadmap (HIR) Test Chapter. Jeorge holds a PhD in Electrical Engineering, and three master’s degrees (MBA, Computer Science, and Telecommunications). He is also visiting professor at the University of California, Santa Cruz and at the University of Phoenix. He is co-author of the book Understanding Fabless IC Technology.

Organizer: Ira Leventhal, Advantest (US) - Paolo Bernardi, PoliTO (IT)

Organizer: Marcello Traiola, Rennes University (FR)

As electronic systems become increasingly complex, connected, and intelligent, the disciplines of testing and reliability engineering are undergoing a profound transformation.

This roundtable panel brings together leading experts from industry and academia to explore how the field is evolving—and how both educational institutions and companies must adapt to stay ahead. At the core of the discussion will be the question of what technical skills will define the future of careers in test and reliability.

Panelists will examine the growing importance of AI-driven diagnostics, system-level testing, and data-centric engineering approaches. They will also explore how academic curricula, at both the master's and doctoral levels, should evolve to keep pace with these technological advancements. Key questions include whether the research-driven depth of a PhD offers a significant advantage over more application-focused master’s training, and how the two educational tracks can be made more complementary.

Finally, the panel will address how stronger industry-academia collaboration can ensure students graduate not only with strong theoretical foundations, but also with the practical, forward-looking skills that will shape the next era of electronic system reliability.

Organizer: Hans Martin von Staudt, Renesas (DE)

Leading edge chips require test procedures that adapt to silicon performance. The most prominent examples are repair and trim. Nearly all chips require trim and quite a few cannot be handled with BIST, very much so for Big-A/little-d devices.

As traditional ATE is geared towards a highly efficient execution of a linear flow of pre-computed stimulus and response, on-chip BIST was the only option to handle the interaction with the DUT, but it is not applicable to many use cases.

Responding to the needs of the test community the IJTAG standard family develops PDL2 with interactive (aka run-time) variables and flow control to express any arbitrary test and trim algorithm already on IP-level.

But what happens if the same IP, instantiated on a given chip 10 times, tested on the ATE with a 16x multi-site setup? 160 instances of a test algorithm, taking different decision on individual data for each instance!

Traditionally, the ATE test program had to serialise, which is rather inefficient.

• Can the test controller and the high-speed links to the instruments be beefed up?
• Can the pattern sequencers be upgraded to PDL2 interpreters?
• Do we actually need any interactivity from the ATE?

Anand Joshi is currently the Senior Fellow for AI at TechInsights. He is a semiconductor industry veteran with over 25 years of experience and a recognized expert in the AI chip community. He’s been a marketing executive and advisor with prominent AI companies that include Esperanto Technologies, NanoSemi (acquired by Maxlinear), Wave Computing, and Redpine Signals (acquired by Silicon Image). His market research reports via Tractica/Omdia/TechInsights on computer vision, AI, and data center infrastructure have been used by Fortune 500 companies for strategic planning purposes since 2015. He is a frequent conference speaker and advises the venture community about AI chip products, strategy, and market feasibility. Anand holds an MSEE from Virginia Tech and an MBA from UC Irvine.

Organizer: Yervant Zorian, Synopsys (US)