Days: Tuesday, September 23rd Wednesday, September 24th Thursday, September 25th
View this program: with abstractssession overviewtalk overview
Richard Rodell Jr. is a distinguished engineer at Infineon Technologies, holding the position since August 2021, while also serving as the Vice President of Test Engineering since April 2020. Previously at Cypress Semiconductor, Richard has extensive experience in test engineering, spanning from roles as Test Engineering Senior Director and Vice President of Test Engineering to Test Engineering Manager and Senior Technical Lead. Richard's expertise includes worldwide management of test engineering for various memory types and system-on-chip (SoC) technologies. Richard earned a Bachelor of Science in Electrical Engineering from Marquette University in 1992.
Organizer: Carl Moore, yieldHUB (IRL)
The rapid adoption of Artificial Intelligence (AI) across semiconductor manufacturing is redefining how data is interpreted, decisions are made, and quality is assured. This panel will explore real-world use cases of AI applied across critical manufacturing stages, with emphasis on Wafer Acceptance Testing (WAT), Wafer Probe, and Final Test processes.
WAT data provides early indicators of process variability and potential yield excursions. AI models leveraging this data can detect subtle correlations and anomalies across fab lots, offering predictive insights long before wafer test. At wafer probe, machine learning models optimize binning and identify systematic test escapes, improving inline yield monitoring. In final test, AI-driven adaptive test strategies help dynamically adjust test limits, enhancing outgoing quality while reducing test time and cost.
As quality expectations intensify—especially for automotive, medical, and aerospace applications—AI offers a path to proactive quality assurance by learning from vast and multidimensional datasets. Instead of retrospective analyses, AI enables real-time interventions, anomaly detection, and root cause attribution with unprecedented accuracy.
However, deploying AI in test and manufacturing is not a plug-and-play exercise. It demands data governance, model interpretability, and strong domain-context fusion. The industry faces a growing need for professionals who can straddle the worlds of data science and semiconductor engineering. Tomorrow’s test teams will require data scientists who also understand transistor physics and reliability metrics as fluently as they write software code.
Panelists from industry and academia will share insights, lessons learned, and forward-looking perspectives on how AI is redefining manufacturing strategies, infrastructure requirements, and talent needs. This discussion aims to provide attendees with a pragmatic understanding of AI integration challenges and the value proposition it offers across the semiconductor value chain.
| 13:30 | Chain Cell-Aware Diagnosis (abstract) PRESENTER: Manish Sharma |
| 14:00 | LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs (abstract) PRESENTER: Mohammed Zine E. Brahmi |
| 14:30 | Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing (abstract) PRESENTER: Saghir Shaikh |
| 14:45 | Device-Aware Test for Threshold Voltage Shifting in FeFET (abstract) PRESENTER: Changhao Wang |
| 14:50 | Early Testing of Memory Redundant Row Elements (abstract) PRESENTER: Luc Romain |
| 14:55 | Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG (abstract) PRESENTER: Reza Khoshzaban |
Organizer: Davide Appello, Technoprobe (IT)
The rapid advancement of silicon photonics technology has opened new frontiers in high-speed data communication, sensing, and computing. This special session at the International Test Conference will delve into the latest developments and challenges in testing silicon photonics products. As the industry moves towards mass production, ensuring the reliability and performance of these devices becomes paramount.
Key discussion topics will include fundamentals of SiPh device testability and test, the characteristics of test interfaces at probe and package and specifically mission mode test. Experts will share insights on overcoming common obstacles such as signal integrity issues, test stability and scalability. Additionally, the session will highlight case studies and real-world applications, providing attendees with practical knowledge and strategies to enhance their testing processes.
Join us for an engaging and informative session that promises to equip participants with the tools and understanding necessary to navigate the complexities of silicon photonics testing. Whether you are a researcher, engineer, or industry professional, this session offers valuable perspectives to drive forward the development and deployment of cutting-edge silicon photonics technologies.
| 16:30 | Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning (abstract) PRESENTER: Lawrence Schlitt |
| 17:00 | Advanced fault model, diagnosis and applications for deep nanometer process (abstract) PRESENTER: Jayant D'Souza |
| 17:30 | SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages (abstract) PRESENTER: Partho Bhoumik |
| 16:30 | Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation (abstract) PRESENTER: Soyed Tuhin Ahmed |
| 17:00 | A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis (abstract) PRESENTER: Jing-Jia Liou |
| 17:30 | Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis (abstract) PRESENTER: Masanori Hashimoto |
View this program: with abstractssession overviewtalk overview
| 10:30 | LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale (abstract) PRESENTER: Eduardo Ortega |
| 11:00 | NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications (abstract) PRESENTER: Xuanyi Tan |
| 11:30 | Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints (abstract) PRESENTER: Dina Moussa |
| 10:30 | Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application (abstract) PRESENTER: Minoru Iida |
| 11:00 | Scan Test for 99% Defect Coverage of R-2R DACs (abstract) PRESENTER: Stephen Sunter |
| 11:30 | Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering (abstract) PRESENTER: Emmanuel Nti Darko |
| 11:45 | Influence of Automated Test Equipment Drift on Process Capability Studies (abstract) PRESENTER: Anand Venkatachalam |
| 11:50 | 5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) (abstract) PRESENTER: Ching-Nen Peng |
| 11:55 | Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment (abstract) PRESENTER: Alessia Galli |
Organizer: Anthony Coyette, ONSEMI (BE)
The Test Technology Standards Committee (TTSC) is an IEEE Computer Society-sponsored group of volunteers that oversees the development and maintenance of standards that advance testability and interoperability within the electronics and semiconductor sectors. Its initiatives serve a broad spectrum of stakeholders, including intellectual property (IP) designers, integrated circuit (IC) engineers, board and system architects, automated test equipment (ATE) suppliers, and automation tool developers. As of the current date, TTSC oversees 19 published standards, 12 active projects with standards nearing publication, and 7 upcoming standards.
This session starts by providing an overview of the portfolio of standards under TTSC’s purview, highlighting the most recent/upcoming additions. The session then continues with short presentations from standards of interest to the Test community specifying language, multi-die contexts, and test access & control. First, the recent progress is reviewed on the front of the Standard Test Interface Language, IEEE Std 1450’s. Next, IEEE Std P1838a is formulating a standards-based language strategy and methodology for addressing board-level test applications with multi-die packages. Chiplet interconnect test and repair is being addressed by IEEE Std P3405. This session continues by discussing the focus of P3405 and how it helps standardize the test and repair hardware and its description.
Finally, a state-of-the-union is provided for IEEE Std 1149.1 and 1687/.1/.2 which are set to ballot within the next 24 months, bringing exciting updates and new features! The 1687 family is embracing PDL2, including run-time variables, flow control, iReturn containers, and more. IEEE Std P1687.1 adds support for non-TAP interfaces to be connected to an IJTAG network, and P1687.2 tackles analog DFT and complex test algorithms. IEEE Std 1149.1 standard adds new boundary scan cells and expands BSDL to better support 1149.6 type interfaces. These enhancements will take us beyond traditional methods and address today’s challenging issues with innovative solutions.
| 10:30 | FSWGEN: a Device-tree Specification driven System-Level Test workload generator (abstract) |
| 10:45 | A Benchmark Suite to Evaluate DNN’s Resilience (abstract) |
| 11:00 | LAMBDA: LLM-Assisted Malicious Bug Detection and Analysis in Hardware Designs (abstract) |
| 11:15 | A Novel Tester-Based Approach for Functional Testing of Hardware Timers (abstract) |
Poster stand # | Title | Authors
1 | 5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) | Hsuan-Yin Huang, Ching-Nen Peng and Kuo-An Wang
4 | Device-Aware Test for Threshold Voltage Shifting in FeFET | Changhao Wang, Sicong Yuan, Hanzhi Xun, Nicolo Bellarmino, Danyang Chen, Chujun Yin, Mottaqiallah Taouil, Moritz Fieback, Xiuyan Li, Lin Wang, Chaobo Li, Riccardo Cantoro, Said Hamdioui and Nima Kolahimahmoudi
5 | Early Testing of Memory Redundant Row Elements | Luc Romain, Albert Au, Roger Mah, Katarzyna Wojnowska and Lori Schramm
8 | Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment | Alessia Galli and Riccardo Vettori
9 | Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG | Reza Khoshzaban, Riccardo Cantoro, Matteo Sonza Reorda, Michelangelo Grosso and Iacopo Guglielminetti
12 | Influence of Automated Test Equipment Drift on Process Capability Studies | Anand Venkatachalam, Ernst Aderholz, Matthias Sauer, Simon Schweizer, Matthias Werner and Ilia Polian
13 | An On-Chip Sensor For Online Monitoring of HCI-Induced Aging In Integrated Circuits | Saeid Karimpour, Emmanuel Nti Darko and Degang Chen
16 | Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution | Vatsal Patel, Ritesh Desai, Ujash Poshiya and Dharini Subashchandran
17 | Advancing ATE for EV Battery Management: Overcoming Test Challenges with Smart Solutions | Sandeep D'Souza, Matthew Getz and Tim Bakken
20 | Early Reliability Estimation in Hardware Accelerators through an Improved Colored Petri Net Approach | Ernesto Cristopher Villegas Castillo, Josie Esteban Rodriguez Condia, Juan-David Guerrero-Balaguera, Felipe Augusto da Silva and Michael Glass
21 | Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness | Divyank Mittal, Sagar Kumar, Sameer Chillarige and Jyotirmoy Saikia
24 | FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks | Javad Bahrami, Parsa Nooralinejad, Hamed Pirsiavash and Naghmeh Karimi
25 | Dynamic SCAN Shift in High Volume Manufacturing Testing for Test Time Optimization | Lim Mao Ding, Yu Tin Cheong, Khai Wern Heng and Li Sok Khor
28 | FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals | Shengbo Liu, Xiao Yindong, Cao Wang, Xiaochun Li and David Keezer
29 | Hierarchical Test Using Running MISR Signatures | Brion Keller, Dale Meehl, Krishna Chakravadhanula and Pradeep Nagaraj
32 | High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops | Kentaroh Katoh, Toru Nakura and Haruo Kobayashi
33 | Low Noise 20-bit DAC for ATE | Brian Friend, Neha Udaiwal and Marzio Pedrali-Noy
36 | Method for Diagnosing Clock Jitter Using FPGA | Seongkwan Lee, Hyuntae Jeong, Cheolmin Park, Jun Yeon Won, Minho Kang and Jaemoo Choi
37 | Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction | Nicolò Bellarmino, Riccardo Cantoro, Martin Huch and Tobias Kilian
40 | MUX-based Polymorphic Registers and FSMs to Protect Against Non-invasive Voltage Fault Injection Attacks | Sourav Roy and Domenic Forte
41 | Improving Deterministic Test Pattern Generation through Massive Static Learning | Peter Wohl, Jonathon Colburn, John Waicukauski and Yasunari Kanzawa
44 | Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals | Cao Wang, Shengbo Liu, Ming Cheng, Yindong Xiao, Xiaochun Li and David Keezer
45 | DMA Burst Mode Fault Detection: Custom MBIST Strategies for Comprehensive Testing | Prakash Kumar, Ratheesh Thekke Veetil and Ajay Purushotham
48 | FeTest: Testing of FeFET-Based Memory Arrays | Dhruv Thapar, Arjun Chaudhuri, Kai Ni and Krishnendu Chakrabarty
49 | Enhancing scan coverage in mixed signal designs by clock and reset manipulation during testing | Khushboo Agarwal, Ari Shtulman, Ahmet Tokuz, Hoang Nguyen and Manjushree Shivarudraiah
52 | Graph Attention Network Based Fault Prediction Framework for Functional Safety Verification | Yutao Sun, Jiehua Huang, Xiangping Liao, Zhijun Wang and Liping Liang
53 | High performance advanced fault model diagnosis | Bharath Nandakumar, Sameer Chillarige and Vaibhav Mishra
56 | Combined Array and ADC Structural Test for RRAM-based Multiply-and-accumulate Circuits | Emmanouil Anastasios Serlis, Hanzhi Xun, Emmanouil Arapidis, Anteneh Gebregiorgis, Mottaqiallah Taouil, Said Hamdioui and Moritz Fieback
57 | AMBA Qchannel based power management VIP for Efficient low power validation | Gokul T and Raveendranath Reddy P
60 | Deep Learning-based IC Monitoring | Iresh Jayawardana Manannaidelage, Krishna Dahal, Spyros Tragoudas, Khader Abdel Hafez and Danushka Senarathna
61 | Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink | Kshitij Kulshreshtha, Vistrita Tyagi, Shrutika Patil, Manish Arora, Deepika Reddy Yenna and Shamitha Rao
64 | Assessment of System-Level Test programs in Automotive SoCs | Giusy Iaria, Claudia Bertani and Vincenzo Tancorre
5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE) (abstract) PRESENTER: Neil Huang |
Device-Aware Test for Threshold Voltage Shifting in FeFET (abstract) PRESENTER: Changhao Wang |
Early Testing of Memory Redundant Row Elements (abstract) PRESENTER: Katarzyna Wojnowska |
Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation (abstract) PRESENTER: Reza Khoshzaban |
Influence of Automated Test Equipment Drift on Process Capability Studies (abstract) PRESENTER: Anand Venkatachalam |
An On-Chip Sensor For Online Monitoring of HCI-Induced Aging In Integrated Circuits (abstract) PRESENTER: Saeid Karimpour |
Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution (abstract) PRESENTER: Vatsal Patel |
Advancing ATE for EV Battery Management: Overcoming Test Challenges with Smart Solutions (abstract) PRESENTER: Matthew Getz |
Early Reliability Estimation in Hardware Accelerators through an Improved Colored Petri Net Approach (abstract) PRESENTER: Ernesto Cristopher Villegas Castillo |
Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness (abstract) PRESENTER: Divyank Mittal |
FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks (abstract) PRESENTER: Javad Bahrami |
Dynamic SCAN Shift in High Volume Manufacturing Testing for Test Time Optimization (abstract) |
FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals (abstract) PRESENTER: Shengbo Liu |
Hierarchical Test Using Running MISR Signatures (abstract) PRESENTER: Brion Keller |
High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops (abstract) PRESENTER: Kentaroh Katoh |
Low Noise 20-bit DAC for ATE (abstract) |
Method for Diagnosing Clock Jitter Using FPGA (abstract) PRESENTER: Jun Yeon Won |
Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction (abstract) PRESENTER: Nicolò Bellarmino |
MUX-based Polymorphic Registers and FSMs to Protect Against Non-invasive Voltage Fault Injection Attacks (abstract) PRESENTER: Domenic Forte |
Improving Deterministic Test Pattern Generation through Massive Static Learning (abstract) PRESENTER: Peter Wohl |
Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals (abstract) PRESENTER: David Keezer |
DMA Burst Mode Fault Detection: Custom MBIST Strategies for Comprehensive Testing (abstract) |
FeTest: Testing of FeFET-Based Memory Arrays (abstract) PRESENTER: Dhruv Thapar |
Enhancing scan coverage in mixed signal designs by clock and reset manipulation during testing (abstract) |
Graph Attention Network Based Fault Prediction Framework for Functional Safety Verification (abstract) PRESENTER: Yutao Sun |
High performance advanced fault model diagnosis (abstract) PRESENTER: Bharath Nandakumar |
Combined Array and ADC Structural Test for RRAM-based Multiply-and-accumulate Circuits (abstract) PRESENTER: Emmanouil Anastasios Serlis |
AMBA Qchannel based power management VIP for Efficient low power validation (abstract) PRESENTER: Gokul T |
Deep Learning-based IC Monitoring (abstract) PRESENTER: Iresh Jayawardana Manannaidelage |
Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink (abstract) |
Assessment of System-Level Test programs in Automotive SoCs (abstract) PRESENTER: Giusy Iaria |
| 13:30 | TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration (abstract) PRESENTER: Zhiteng Chao |
| 14:00 | LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency (abstract) PRESENTER: Sudipta Paria |
| 14:30 | Automated Selection of Optimal EDT Input Configuration (abstract) PRESENTER: Janusz Rajski |
| 13:30 | Persistent High-Bandwidth IJTAG Data Delivery (abstract) PRESENTER: Jan Burchard |
| 14:00 | Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges (abstract) PRESENTER: Hans Martin von Staudt |
| 14:30 | Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks (abstract) PRESENTER: Sebastian Huhn |
Organizer: Marcello Traiola, Rennes University (FR)
As electronic systems become increasingly complex, connected, and intelligent, the disciplines of testing and reliability engineering are undergoing a profound transformation.
This roundtable panel brings together leading experts from industry and academia to explore how the field is evolving—and how both educational institutions and companies must adapt to stay ahead. At the core of the discussion will be the question of what technical skills will define the future of careers in test and reliability.
Panelists will examine the growing importance of AI-driven diagnostics, system-level testing, and data-centric engineering approaches. They will also explore how academic curricula, at both the master's and doctoral levels, should evolve to keep pace with these technological advancements. Key questions include whether the research-driven depth of a PhD offers a significant advantage over more application-focused master’s training, and how the two educational tracks can be made more complementary.
Finally, the panel will address how stronger industry-academia collaboration can ensure students graduate not only with strong theoretical foundations, but also with the practical, forward-looking skills that will shape the next era of electronic system reliability.
Organizer: Hans Martin von Staudt, Renesas (DE)
Leading edge chips require test procedures that adapt to silicon performance. The most prominent examples are repair and trim. Nearly all chips require trim and quite a few cannot be handled with BIST, very much so for Big-A/little-d devices.
As traditional ATE is geared towards a highly efficient execution of a linear flow of pre-computed stimulus and response, on-chip BIST was the only option to handle the interaction with the DUT, but it is not applicable to many use cases.
Responding to the needs of the test community the IJTAG standard family develops PDL2 with interactive (aka run-time) variables and flow control to express any arbitrary test and trim algorithm already on IP-level.
But what happens if the same IP, instantiated on a given chip 10 times, tested on the ATE with a 16x multi-site setup? 160 instances of a test algorithm, taking different decision on individual data for each instance!
Traditionally, the ATE test program had to serialise, which is rather inefficient.
- Can the test controller and the high-speed links to the instruments be beefed up?
- Can the pattern sequencers be upgraded to PDL2 interpreters?
- Do we actually need any interactivity from the ATE?
| 15:30 | Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing (abstract) PRESENTER: Yuxuan Yin |
| 16:00 | OCTANE: On-Chip Telemetry-based Anomaly Notification Engine (abstract) PRESENTER: Eduardo Ortega |
| 16:30 | IEA-Plugin: An AI Agent Reasoner for Test Data Analytics (abstract) PRESENTER: Seoyeon Kim |
| 15:30 | Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up (abstract) PRESENTER: Ding-Wei Cheng |
| 16:00 | Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost (abstract) PRESENTER: Ankita Patidar |
| 16:30 | Shifting-left Zero Defect Scan Test Development to Launch Automotive PPM-ready products (abstract) PRESENTER: Stephen Traynor |
| 16:45 | Test Pattern Aware Streaming Fabric-based Scan Test Methodology (abstract) PRESENTER: Krishna Gnawali |
| 16:50 | Scan Strategies for High Quality Latch Array Testing (abstract) PRESENTER: Bin Du |
| 16:55 | Functional Logic Diagnosis with Observation Points on Next-State Variables (abstract) |
| 15:30 | System-Level Test techniques for Automotive SoCs (abstract) |
| 16:00 | Chiplet Interconnect Test and Repair (abstract) |
| 16:30 | Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time (abstract) |
View this program: with abstractssession overviewtalk overview
Organizer: Yervant Zorian, Synopsys (US)
| 10:30 | Ultra dense SRAM Cell Test Challenges (abstract) PRESENTER: Uma Srinivasan |
| 11:00 | A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM (abstract) PRESENTER: Min-Kyu Kim |
| 11:30 | Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures (abstract) PRESENTER: Mehdi Tahoori |
| 10:30 | Stress Aware Quiescent Current Test Optimization (abstract) PRESENTER: Shubhendu Shrivastava |
| 11:00 | Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions (abstract) PRESENTER: Jason W.-Y. Cheng |
| 11:30 | Full enablement of Very Low Voltage testing to deliver Zero Defect Quality automotive products (abstract) PRESENTER: Stephen Traynor |
| 11:45 | Embedded Trace: A Key Enabler for Silicon Lifecycle Management (abstract) PRESENTER: Vivek Chickermane |
| 11:50 | CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption (abstract) PRESENTER: Xun Jiao |
| 11:55 | In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs (abstract) PRESENTER: Varun Sehgal |
| 10:30 | Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF) (abstract) PRESENTER: Behnam Farnaghinejad |
| 11:00 | QuEST: Quantitative Entropy-based Security and Trojan Detection Framework for Confidentiality Verification (abstract) PRESENTER: Domenic Forte |
| 11:30 | Pseudo Random Low Power Built in Self Test (abstract) PRESENTER: Dale Meehl |
| 11:45 | Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis (abstract) PRESENTER: Shakil Ahmed |
| 11:50 | Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection (abstract) PRESENTER: Noeël Moeskops |
| 11:55 | An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists (abstract) PRESENTER: Aric Fowler |
Poster stand # | Title | Authors
2 | An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists | Aric Fowler, Carl Sechen and Yiorgos Makris
3 | CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption | Xun Jiao, Fred Lin, Sunny Yang, Suman Gumudavelli, Shreya Varshini, Harish Dixit, Abhinav Pandey, Ahbinav Jauhri, Tyler Graf, Francesco Caggioni, Venkat Ramesh, Philip Henzler, Sameeksha Gupta, Jason Liang and Gautham Vunnam
6 | Embedded Trace: A Key Enabler for Silicon Lifecycle Management | Vivek Chickermane, Marcel Zak and Mat O'Donnell
7 | Functional Logic Diagnosis with Observation Points on Next-State Variables | Irith Pomeranz
10 | Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection | Noeël Moeskops, Abdullah Aljuffri, Said Hamdioui and Mottaqiallah Taouil
11 | Scan Strategies for High Quality Latch Array Testing | Bin Du, Nehal Patel, Yerong Chen, Jeremy Chin and Kethreine Tian
14 | Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis | Shakil Ahmed, Dipali Jain and Kaveh Shamsi
15 | In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs | Ashrith S Harith, Subramanian Mahadevan, Nilanjan Mukherjee, Varun Sehgal, Saket Goyal and Mohit Sharma
18 | Wafer Map Pattern Recognition using Ternary Spiking Neural Network | Abhishek Kumar Mishra, Anup Das and Nagarajan Kandasamy
19 | Test Pattern Aware Streaming Fabric-based Scan Test Methodology | Krishna Gnawali, Andrea Costa, Nathalie Etono, Denis Martin, Bala Tarun Nelapatla and Amit Purohit
22 | Optimizing Sensing Point Placement for High-Multi-Site Testing on Device Interface Boards | Ashley Chien-Hui Huang, Derek Hong-Yi Yang and Siya Ssu-Ya Liao
23 | Wafer Map Pattern Recognition for Multisite Probe with Synthetic Data Augmented Training | Chen He, Rebecca Chen and Patrick Goertz
26 | Teaching Llamas to Test: A Large Language Model-Based Approach | Christos Vasileiou and Yiorgos Makris
27 | Resurgence in Advanced ATPG Techniques for High-Performance Designs | Dale Meehl, Krishna Chakravadhanula, Brion Keller and Pradeep Nagaraj
30 | TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption | Deepesh Sahoo, Eduardo Ortega, Peter Domanski, Farshad Firouzi and Krishnendu Chakrabarty
31 | Statistical Analysis of the Nonlinearity Errors of Unary and Binary-Weighted DACs | Godfred Bonsu, Isaac Bruce, Emmanuel Darko, Kelvin Tamakloe and Degang Chen
34 | Machine Learning Assisted Vmin Prediction | Huitong Chen, Xinyu Sun, Rongrong Liu, Robert Wu and Kashish Shah
35 | Secure and Efficient Sharing of On-Chip Resources | Joel Åhlund, Markus Törmänen and Erik Larsson
38 | Structural Testing on SLT Platform with HSAT IP & High-Speed I/O Access | Jyotika Suri, Rakesh Kinger, Sridhar Nimmagadda and Henry Fei
39 | Precise Approach to ATPG: Handling Timing Exceptions for Better Small Delay Defect Coverage | Lana Pantskalashvili, Ron Press and Hans Tsai
42 | STARTS: Simulation Traits Assisted Random Test Selection for Multiprocessor Verification | Li Zhou, Menglong Lu, Li Luo, Jianfeng Zhang and Junbo Tie
43 | Sharing Scan Bandwidth Across Die to Die in MCM Package | Manish Bhattarai, Ramu Setty and Manish Bhattarai
46 | Origen Based Test and Validation | Paul DeRouen and Joe Chayachinda
47 | Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks | Po-Sheng Chiu, Chih-Yu Hsu, Chih-Tsun Huang and Jing-Jia Liou
50 | Test Bin Entitlement: Yield Outlier Detection using Die Area and LLM based Bin-Grouping | Ragad Al-Huq and Yuegui Zheng
51 | Why is Rigorous PCIe Interoperability Testing is Key to Robust and Reliable Systems? | Sean Chen, Frank Chang, Victor Castillo, Amarildo Garcia and Joe Obedowski
54 | Testing of Passive Memristor Crossbars in AI Hardware Accelerators | Shanmukha Mangadahalli Siddaramu, Mahta Mayahinia, Surendra Hemaram and Mehdi Tahoori
55 | Platform Thermal Management in System Level Test: Analysis of existing solutions and introduction to advanced liquid cooled memory solutions | Sridutt Tummalapalli and Srinath Reddy Yerakondappagari
58 | Most Effective At-Speed Test: Hybrid Launch-Off-Shift and Capture Technique | Takeo Kobayashi, Ron Press and Lana Pantskalashvili
59 | Methodology for Accurate and Automated IDD Characterization on ATE | Todd Jacobs and Peter Smykla
62 | The Role SLT Plays at Intel | Vishwanath Natarajan, Carlos O Bernabe and Ethan Hansen
63 | IEEE P1450.6.2: Core Test Language (CTL) for Memories An update to the existing standard | Saman Adham, Puneet Arora, Albert Au and Artur Pogiel
An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists (abstract) PRESENTER: Aric Fowler |
CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption (abstract) |
Embedded Trace: A Key Enabler for Silicon Lifecycle Management (abstract) |
Functional Logic Diagnosis with Observation Points on Next-State Variables (abstract) |
Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection (abstract) PRESENTER: Mottaqiallah Taouil |
Scan Strategies for High Quality Latch Array Testing (abstract) PRESENTER: Bin Du |
Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis (abstract) PRESENTER: Shakil Ahmed |
Wafer Map Pattern Recognition using Ternary Spiking Neural Network (abstract) PRESENTER: Abhishek Kumar Mishra |
Test Pattern Aware Streaming Fabric-based Scan Test Methodology (abstract) PRESENTER: Krishna Gnawali |
Optimizing Sensing Point Placement for High-Multi-Site Testing on Device Interface Boards (abstract) |
Wafer Map Pattern Recognition for Multisite Probe with Synthetic Data Augmented Training (abstract) PRESENTER: Chen He |
Teaching Llamas to Test: A Language-Based Approach (abstract) PRESENTER: Christos Vasileiou |
Resurgence in Advanced ATPG Techniques for High-Performance Designs (abstract) |
TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption (abstract) PRESENTER: Eduardo Ortega |
Statistical Analysis of the Nonlinearity Errors of Unary and Binary-Weighted DACs (abstract) PRESENTER: Godfred Bonsu |
Machine Learning Assisted Vmin Prediction (abstract) |
Secure and Efficient Sharing of On-Chip Resources (abstract) PRESENTER: Joel Åhlund |
Structural Testing on SLT Platform with HSAT IP & High-Speed I/O Access (abstract) PRESENTER: Jyotika Suri |
Precise Approach to ATPG: Handling Timing Exceptions for Better Small Delay Defect Coverage (abstract) |
STARTS: Simulation Traits Assisted Random Test Selection for Multiprocessor Verification (abstract) PRESENTER: Li Zhou |
Sharing Scan Bandwidth Across Die to Die in MCM Package (abstract) |
Origen Based Test and Validation (abstract) |
Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks (abstract) PRESENTER: Jing-Jia Liou |
Test Bin Entitlement: Yield Outlier Detection using Die Area and LLM based Bin-Grouping (abstract) PRESENTER: Ragad Al-Huq |
Why is Rigorous PCIe LTSSM Testing a Key to Robust and Reliable Systems? (abstract) PRESENTER: Sean Chen |
Testing of Passive Memristive Crossbars in AI Hardware Accelerators (abstract) PRESENTER: Shanmukha Mangadahalli Siddaramu |
Thermal Management in System Level Test: Analysis of existing solutions and an introduction to advanced liquid cooled memory solutions (abstract) PRESENTER: Sridutt Tummalapalli |
Most Effective At-Speed Test: Hybrid Launch-Off-Shift and Capture Technique (abstract) |
Deep Learning-based IC Monitoring (abstract) PRESENTER: Iresh Jayawardana Manannaidelage |
The Role SLT Plays at Intel (abstract) |
IEEE P1450.6.2: Core Test Language (CTL) for Memories An update to the existing standard (abstract) PRESENTER: Saman Adham |
Organizer: Ira Leventhal, Advantest (US) - Paolo Bernardi, PoliTO (IT)
| 13:30 | A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications (abstract) PRESENTER: Hiroyuki Iwata |
| 14:00 | Chiplets' Die-to-Die Interconnect Repair Language (IRL) (abstract) PRESENTER: Po-Yao Chuang |
| 14:30 | Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging (abstract) PRESENTER: Partho Bhoumik |
| 13:30 | DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors (abstract) PRESENTER: Vijay Kakollu |
| 14:00 | Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance (abstract) PRESENTER: Gowsika Dharmaraj |
| 14:30 | Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion (abstract) PRESENTER: Hao-Yu Yang |
| 13:30 | IC-PEPR: PEPR Testing Goes Intra-Cell (abstract) PRESENTER: Chris Nigh |
| 14:00 | Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2 (abstract) PRESENTER: Hao-Yu Yang |
| 14:30 | Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects (abstract) PRESENTER: Wu-Tung Cheng |