Jaidev Shenoy is currently working as a Senior Staff manager at Marvell Semiconductors and has more than 17 years of experience in DFT. His expertise are in DFT methodology development and validation across different technologies ranging from 65nm to the latest nodes, as well as multiple tools and flows. His areas of interest include DFT compression techniques, Low power DFT, Logic BIST, 3D IC Test, Post silicon diagnosis for both manufacturing and In-system test. He is a regular contributor in multiple conferences dedicated to the electronic test of devices, boards, systems and also holds one US patent. He has completed his PhD from IIT Bombay, India and has a Bachelor of Engineering degree from MSRIT, Bangalore, India.