ITC 2025: IEEE INTERNATIONAL TEST CONFERENCE

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Abu-Gosh, Fayez	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Aderholz, Ernst	Influence of Automated Test Equipment Drift on Process Capability Studies Influence of Automated Test Equipment Drift on Process Capability Studies
Adham, Saman	IEEE P1450.6.2: Core Test Language (CTL) for Memories An update to the existing standard
Agarwal, Khushboo	Enhancing scan coverage in mixed signal designs by clock and reset manipulation during testing
Agnihotri, Pratishtha	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
Ahmed, Shakil	Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis
Ahmed, Soyed Tuhin	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Al-Huq, Ragad	Test Bin Entitlement: Yield Outlier Detection using Die Area and LLM based Bin-Grouping
Aljuffri, Abdullah	Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection
Angione, Francesco	System-Level Test techniques for Automotive SoCs
Anjaneyareddy, Arun Kumar	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Appel, Megan	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Arapidis, Emmanouil	Combined Array and ADC Structural Test for RRAM-based Multiply-and-accumulate Circuits
Arora, Manish	Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink
Arora, Puneet	IEEE P1450.6.2: Core Test Language (CTL) for Memories An update to the existing standard
Au, Albert	Early Testing of Memory Redundant Row Elements IEEE P1450.6.2: Core Test Language (CTL) for Memories An update to the existing standard Early Testing of Memory Redundant Row Elements
Augusto da Silva, Felipe	Early Reliability Estimation in Hardware Accelerators through an Improved Colored Petri Net Approach
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Bahrami, Javad	FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks
Bakken, Tim	Advancing ATE for EV Battery Management: Overcoming Test Challenges with Smart Solutions
Banerjee, Sanmitra	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications
Bellarmino, Nicolò	Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET
Bellizia, Davide	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Bennett, Christopher H.	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Bernabe, Carlos O	The Role SLT Plays at Intel
Bernardi, Paolo	System-Level Test techniques for Automotive SoCs
Bertani, Claudia	Assessment of System-Level Test programs in Automotive SoCs
Bhattarai, Manish	Sharing Scan Bandwidth Across Die to Die in MCM Package
Bhattarai, Manish	Sharing Scan Bandwidth Across Die to Die in MCM Package
Bhoumik, Partho	Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages
Bhunia, Swarup	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Blair, Steve	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
Blanton, Shawn	IC-PEPR: PEPR Testing Goes Intra-Cell
Bonsu, Godfred	Statistical Analysis of the Nonlinearity Errors of Unary and Binary-Weighted DACs Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
Brahmi, Mohammed Zine E.	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Brea, Brandon	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Bruce, Isaac	Statistical Analysis of the Nonlinearity Errors of Unary and Binary-Weighted DACs Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
Burchard, Jan	Persistent High-Bandwidth IJTAG Data Delivery Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
C
Caggioni, Francesco	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Caggioni, Francesco	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Cantoro, Riccardo	Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG System-Level Test techniques for Automotive SoCs
Castillo, Victor	Why is Rigorous PCIe LTSSM Testing a Key to Robust and Reliable Systems?
Chakrabarty, Krishnendu	FeTest: Testing of FeFET-Based Memory Arrays TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging OCTANE: On-Chip Telemetry-based Anomaly Notification Engine Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages
Chakravadhanula, Krishna	Hierarchical Test Using Running MISR Signatures Resurgence in Advanced ATPG Techniques for High-Performance Designs Pseudo Random Low Power Built in Self Test
Chang, Frank	Why is Rigorous PCIe LTSSM Testing a Key to Robust and Reliable Systems?
Chao, Yu-Hong	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Chao, Zhiteng	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Chaplot, Nipun	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Chatterjee, Abhijit	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Chatterjee, Atri	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Chattopadhyay, Rita	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
Chatzopoulos, Odysseas	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
Chaudhuri, Arjun	FeTest: Testing of FeFET-Based Memory Arrays NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages
Chayachinda, Joe	Origen Based Test and Validation
Chen, Danyang	Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET
Chen, Degang	An On-Chip Sensor For Online Monitoring of HCI-Induced Aging In Integrated Circuits Statistical Analysis of the Nonlinearity Errors of Unary and Binary-Weighted DACs Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
Chen, Dong-Yi	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Chen, Harry	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
Chen, Huitong	Machine Learning Assisted Vmin Prediction
Chen, Jeffery Y.-C.	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
Chen, Rebecca	Wafer Map Pattern Recognition for Multisite Probe with Synthetic Data Augmented Training Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Chen, Sean	Why is Rigorous PCIe LTSSM Testing a Key to Robust and Reliable Systems?
Chen, Yerong	Scan Strategies for High Quality Latch Array Testing Scan Strategies for High Quality Latch Array Testing
Cheng, Ding-Wei	Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up
Cheng, Jason W.-Y.	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
Cheng, Ming	Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
Cheng, Quan	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Cheng, Wu-Tung	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects
Cheong, Yu Tin	Dynamic SCAN Shift in High Volume Manufacturing Testing for Test Time Optimization
Chern, Mason	Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up
Chi, Hao-Yang	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Chickermane, Vivek	Embedded Trace: A Key Enabler for Silicon Lifecycle Management Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Chillarige, Sameer	Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness High performance advanced fault model diagnosis Pseudo Random Low Power Built in Self Test
Chin, Jeremy	Scan Strategies for High Quality Latch Array Testing Scan Strategies for High Quality Latch Array Testing
Chiu, Po-Sheng	Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks
Cho, Kyung-Rak	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Cho, Muyun	Advanced fault model, diagnosis and applications for deep nanometer process
Choi, Jaemoo	Method for Diagnosing Clock Jitter Using FPGA
Chuang, Po-Yao	Chiplets' Die-to-Die Interconnect Repair Language (IRL) Chiplet Interconnect Test and Repair
Chung, Cheng-En	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Colburn, Jonathon	Improving Deterministic Test Pattern Generation through Massive Static Learning
Costa, Andrea	Test Pattern Aware Streaming Fabric-based Scan Test Methodology Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Cote, J-F	Persistent High-Bandwidth IJTAG Data Delivery
Czerniawski, Kacper	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
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D'Souza, Jayant	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects Advanced fault model, diagnosis and applications for deep nanometer process
D'Souza, Sandeep	Advancing ATE for EV Battery Management: Overcoming Test Challenges with Smart Solutions
Dahal, Krishna	Deep Learning-based IC Monitoring Deep Learning-based IC Monitoring
Das, Anup	Wafer Map Pattern Recognition using Ternary Spiking Neural Network
Dasgupta, Aritra	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Dempsey, Ryan	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
DeRouen, Paul	Origen Based Test and Validation
Desai, Ritesh	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
Devrani, Gaurav	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Dharmaraj, Gowsika	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Dharmavaram, Ramanath	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Di Carlo, Stefano	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
di Gruttola Giardino, Nicola	A Novel Tester-Based Approach for Functional Testing of Hardware Timers
Ding, Lim Mao	Dynamic SCAN Shift in High Volume Manufacturing Testing for Test Time Optimization
Dixit, Harish	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Dixit, Harish	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Dolmeta, Alessandra	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Domanski, Peter	TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale
Du, Bin	Scan Strategies for High Quality Latch Array Testing Scan Strategies for High Quality Latch Array Testing
Dworak, Jennifer	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
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Etono, Nathalie	Test Pattern Aware Streaming Fabric-based Scan Test Methodology Test Pattern Aware Streaming Fabric-based Scan Test Methodology
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Farnaghinejad, Behnam	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Fei, Henry	Structural Testing on SLT Platform with HSAT IP & High-Speed I/O Access
Feinberg, Ben	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Ferdous, Md Rezoan	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Fieback, Moritz	Device-Aware Test for Threshold Voltage Shifting in FeFET Combined Array and ADC Structural Test for RRAM-based Multiply-and-accumulate Circuits Device-Aware Test for Threshold Voltage Shifting in FeFET
Filipponi, Gabriele	FSWGEN: a Device-tree Specification driven System-Level Test workload generator
Firouzi, Farshad	TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale
Forte, Domenic	MUX-based Polymorphic Registers and FSMs to Protect Against Non-invasive Voltage Fault Injection Attacks QuEST: Quantitative Entropy-based Security and Trojan Detection Framework for Confidentiality Verification
Fowler, Aric	An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
Friend, Brian	Low Noise 20-bit DAC for ATE
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Galli, Alessia	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Garcia, Amarildo	Why is Rigorous PCIe LTSSM Testing a Key to Robust and Reliable Systems?
Gaudet, Jonathan	Persistent High-Bandwidth IJTAG Data Delivery Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Gebregiorgis, Anteneh	Combined Array and ADC Structural Test for RRAM-based Multiply-and-accumulate Circuits Stress Aware Quiescent Current Test Optimization
Getz, Matthew	Advancing ATE for EV Battery Management: Overcoming Test Challenges with Smart Solutions
Gizopoulos, Dimitris	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
Glass, Michael	Early Reliability Estimation in Hardware Accelerators through an Improved Colored Petri Net Approach
Gnawali, Krishna	Test Pattern Aware Streaming Fabric-based Scan Test Methodology Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Goel, Sandeep Kumar	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost
Goertz, Patrick	Wafer Map Pattern Recognition for Multisite Probe with Synthetic Data Augmented Training
Goh, Szu Huat	Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up
Goyal, Saket	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
Graf, Tyler	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Graf, Tyler	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Grosso, Michelangelo	Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Gu, Feng	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Guerrero-Balaguera, Juan-David	Early Reliability Estimation in Hardware Accelerators through an Improved Colored Petri Net Approach
Guglielminetti, Iacopo	Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Gumudavelli, Suman	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Gumudavelli, Suman	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Gunnes, Jo	Stress Aware Quiescent Current Test Optimization
Gupta, Sameeksha	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Gupta, Sameeksha	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Gurram, Venkata.Anilkumar Reddy	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
H
Hafez, Khader Abdel	Deep Learning-based IC Monitoring Deep Learning-based IC Monitoring
Hall, Austen	Ultra dense SRAM Cell Test Challenges
Hamdioui, Said	Device-Aware Test for Threshold Voltage Shifting in FeFET Combined Array and ADC Structural Test for RRAM-based Multiply-and-accumulate Circuits Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection Stress Aware Quiescent Current Test Optimization Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection Device-Aware Test for Threshold Voltage Shifting in FeFET
Hansen, Ethan	The Role SLT Plays at Intel
Harith, Ashrith S	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
Hashimoto, Masanori	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Hati, Arjun	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
He, Chen	Wafer Map Pattern Recognition for Multisite Probe with Synthetic Data Augmented Training LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Hefenbrock, Michael	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
Hemaram, Surendra	Testing of Passive Memristive Crossbars in AI Hardware Accelerators
Heng, Khai Wern	Dynamic SCAN Shift in High Volume Manufacturing Testing for Test Time Optimization
Henzler, Philip	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Henzler, Philip	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Hong, Heeil	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Hornicek, Gregory	Ultra dense SRAM Cell Test Challenges
Hsieh, Bing-Han	Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up
Hsu, Chih-Yu	Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks
Huang, Ashley Chien-Hui	Optimizing Sensing Point Placement for High-Multi-Site Testing on Device Interface Boards
Huang, Chih-Tsun	Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks
Huang, Jiehua	Graph Attention Network Based Fault Prediction Framework for Functional Safety Verification
Huang, Neil	5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
Huch, Martin	Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction
Huhn, Sebastian	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Hung, Hsin-Wei	Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2 Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Huott, William	Ultra dense SRAM Cell Test Challenges
Hwang, Sangjoon	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
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Iaria, Giusy	Assessment of System-Level Test programs in Automotive SoCs
Iida, Minoru	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
Iwata, Hiroyuki	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications
J
J N, Ravi	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs Shifting-left Zero Defect Scan Test Development to Launch Automotive PPM-ready products
Jain, Dipali	Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis
Jaishi Mishra, Manish	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Janicki, Jakub	Chain Cell-Aware Diagnosis Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects
Janiszewski, Wojciech	Persistent High-Bandwidth IJTAG Data Delivery
Jauhri, Ahbinav	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Jauhri, Ahbinav	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Jeong, Hyuntae	Method for Diagnosing Clock Jitter Using FPGA
Jian, Jun-Han	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Jiao, Xun	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Jurga, Krzysztof	Scan Test for 99% Defect Coverage of R-2R DACs
K
Kakollu, Vijay	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Kalla, Priyank	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
Kampmann, Matthias	Persistent High-Bandwidth IJTAG Data Delivery Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Kandasamy, Nagarajan	Wafer Map Pattern Recognition using Ternary Spiking Neural Network
Kang, Minho	Method for Diagnosing Clock Jitter Using FPGA
Kanzawa, Yasunari	Improving Deterministic Test Pattern Generation through Massive Static Learning
Karimi, Naghmeh	FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks
Karimpour, Saeid	An On-Chip Sensor For Online Monitoring of HCI-Induced Aging In Integrated Circuits Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
Katoh, Kentaroh	High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops
Keezer, David	FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
Keim, Martin	Persistent High-Bandwidth IJTAG Data Delivery Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Keller, Brion	Hierarchical Test Using Running MISR Signatures Resurgence in Advanced ATPG Techniques for High-Performance Designs
Khor, Li Sok	Dynamic SCAN Shift in High Volume Manufacturing Testing for Test Time Optimization
Khoshzaban, Reza	Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Kilian, Tobias	Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction
Kim, Deasun	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Kim, Min-Kyu	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Kim, Seoyeon	IEA-Plugin: An AI Agent Reasoner for Test Data Analytics
Kinger, Rakesh	Structural Testing on SLT Platform with HSAT IP & High-Speed I/O Access
Kobayashi, Haruo	High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops
Kobayashi, Norio	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
Kobayashi, Takeo	Most Effective At-Speed Test: Hybrid Launch-Off-Shift and Capture Technique
Kolahimahmoudi, Nima	Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET
Kulshreshtha, Kshitij	Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink
Kumar, Prakash	DMA Burst Mode Fault Detection: Custom MBIST Strategies for Comprehensive Testing
Kumar, Sagar	Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness
Kundu, Subhadip	Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up
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Laisne, Michael	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Larsson, Erik	Secure and Efficient Sharing of On-Chip Resources
Lee, Frank	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost
Lee, Jim	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Lee, Kuen-Jong	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Lee, Seongkwan	Method for Diagnosing Clock Jitter Using FPGA
Li, Chaobo	Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET
Li, Huawei	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Li, James Chien-Mo	Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up
Li, Peng	Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Li, Wei	IC-PEPR: PEPR Testing Goes Intra-Cell
Li, Wenxing	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Li, Xiaochun	FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
Li, Xiaowei	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Li, Xiuyan	Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET
Liang, Aaron C.-W.	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
Liang, Chien-Hsing	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
Liang, Chien-Hsing	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Liang, Jason	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Liang, Jason	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Liang, Liping	Graph Attention Network Based Fault Prediction Framework for Functional Safety Verification
Liang, Yuan	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Liao, Siya Ssu-Ya	Optimizing Sensing Point Placement for High-Multi-Site Testing on Device Interface Boards
Liao, Wang	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Liao, Xiangping	Graph Attention Network Based Fault Prediction Framework for Functional Safety Verification
Lim, Hyunyul	Advanced fault model, diagnosis and applications for deep nanometer process
Lin, Fred	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Lin, Fred	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Lin, Hen-Ming	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
Lin, Longyang	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Liou, Jing-Jia	Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Liu, Min-Hsin	Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up
Liu, Rongrong	Machine Learning Assisted Vmin Prediction
Liu, Shengbo	FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
Liu, Zizhen	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Loh, Lay Hoon	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Lu, Menglong	STARTS: Simulation Traits Assisted Random Test Selection for Multiprocessor Verification
Luo, Li	STARTS: Simulation Traits Assisted Random Test Selection for Multiprocessor Verification
Lyu, Hongqin	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
M
Mah, Roger	Early Testing of Memory Redundant Row Elements Early Testing of Memory Redundant Row Elements
Mahadevan, Subramanian	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
Makris, Yiorgos	Teaching Llamas to Test: A Language-Based Approach An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
Manannaidelage, Iresh Jayawardana	Deep Learning-based IC Monitoring Deep Learning-based IC Monitoring
Mangadahalli Siddaramu, Shanmukha	Testing of Passive Memristive Crossbars in AI Hardware Accelerators
Marinella, Matthew J.	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Marinissen, Erik Jan	Chiplets' Die-to-Die Interconnect Repair Language (IRL) Chiplet Interconnect Test and Repair
Martin, Denis	Test Pattern Aware Streaming Fabric-based Scan Test Methodology Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Masera, Guido	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Mayahinia, Mahta	Testing of Passive Memristive Crossbars in AI Hardware Accelerators Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
Meehl, Dale	Hierarchical Test Using Running MISR Signatures Resurgence in Advanced ATPG Techniques for High-Performance Designs Pseudo Random Low Power Built in Self Test
Meier, Reinhard	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Mishra, Abhishek Kumar	Wafer Map Pattern Recognition using Ternary Spiking Neural Network
Mishra, Vaibhav	High performance advanced fault model diagnosis
Mitra, Subhasish	IC-PEPR: PEPR Testing Goes Intra-Cell
Mittal, Divyank	Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness
Moeskops, Noeël	Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection
Moussa, Dina	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
Mrugalski, Grzegorz	Automated Selection of Optimal EDT Input Configuration
Mu, Jianan	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Mukherjee, Gitanjali	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications
Mukherjee, Nilanjan	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
N
Nagaraj, Pradeep	Hierarchical Test Using Running MISR Signatures Resurgence in Advanced ATPG Techniques for High-Performance Designs
Nakamura, Masayuki	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
Nakura, Toru	High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops
Nam, Incheol	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Nandakumar, Bharath	High performance advanced fault model diagnosis Pseudo Random Low Power Built in Self Test
Naresh, Nikita	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Natarajan, Suriyaprakash	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Natarajan, Vishwanath	The Role SLT Plays at Intel
Nelapatla, Bala Tarun	Test Pattern Aware Streaming Fabric-based Scan Test Methodology Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Nezhadi, Ali	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
Nguyen, Hoang	Enhancing scan coverage in mixed signal designs by clock and reset manipulation during testing
Ni, Kai	FeTest: Testing of FeFET-Based Memory Arrays
Nigh, Chris	IC-PEPR: PEPR Testing Goes Intra-Cell Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up
Nimmagadda, Sridhar	Structural Testing on SLT Platform with HSAT IP & High-Speed I/O Access
Noble, Brian	Ultra dense SRAM Cell Test Challenges
Nooralinejad Eslamloo, Parsa	FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks
Nti Darko, Emmanuel	An On-Chip Sensor For Online Monitoring of HCI-Induced Aging In Integrated Circuits Statistical Analysis of the Nonlinearity Errors of Unary and Binary-Weighted DACs Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
O
O'Donnell, Mat	Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Oak, Chaitali	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Obedowski, Joe	Why is Rigorous PCIe LTSSM Testing a Key to Robust and Reliable Systems?
Ockunzzi, Kelly	Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time
Olejarz, Michal	Persistent High-Bandwidth IJTAG Data Delivery
Ortega, Eduardo	TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale OCTANE: On-Chip Telemetry-based Anomaly Notification Engine Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
P
P, Raveendranath Reddy	AMBA Qchannel based power management VIP for Efficient low power validation
Paik, Woohyun	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
Pan, Gung-Yu	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
Pandey, Abhinav	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Pandey, Abhinav	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Pantskalashvili, Lana	Precise Approach to ATPG: Handling Timing Exceptions for Better Small Delay Defect Coverage Most Effective At-Speed Test: Hybrid Launch-Off-Shift and Capture Technique
Papadimitriou, George	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
Pappalardo, Salvatore	A Benchmark Suite to Evaluate DNN’s Resilience
Parasrampuria, Mayank	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Parekhji, Rubin	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications
Paria, Sudipta	LAMBDA: LLM-Assisted Malicious Bug Detection and Analysis in Hardware Designs LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Park, Cheolmin	Method for Diagnosing Clock Jitter Using FPGA
Park, Jaeseok	Advanced fault model, diagnosis and applications for deep nanometer process
Patel, Ayush	Persistent High-Bandwidth IJTAG Data Delivery
Patel, Nehal	Scan Strategies for High Quality Latch Array Testing Scan Strategies for High Quality Latch Array Testing
Patel, Vatsal	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
Patidar, Ankita	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost
Patil, Shrutika	Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink
Pedrali-Noy, Marzio	Low Noise 20-bit DAC for ATE
Peng, Ching-Nen	5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
Pentyala, Srimaiyee	Full enablement of Very Low Voltage testing to deliver Zero Defect Quality automotive products
Perkovic, Martina	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Pirsiavash, Hamed	FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks
Pogiel, Artur	IEEE P1450.6.2: Core Test Language (CTL) for Memories An update to the existing standard
Polian, Ilia	Influence of Automated Test Equipment Drift on Process Capability Studies Influence of Automated Test Equipment Drift on Process Capability Studies
Pomeranz, Irith	Functional Logic Diagnosis with Observation Points on Next-State Variables Functional Logic Diagnosis with Observation Points on Next-State Variables
Porsia, Antonio	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Poshiya, Ujash	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
Pradeep, Wilson	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Prakash, Palanisamy	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Press, Ron	Precise Approach to ATPG: Handling Timing Exceptions for Better Small Delay Defect Coverage Most Effective At-Speed Test: Hybrid Launch-Off-Shift and Capture Technique
Przybysz, Olga	Persistent High-Bandwidth IJTAG Data Delivery
Purdy, Ruben	IC-PEPR: PEPR Testing Goes Intra-Cell
Purohit, Amit	Test Pattern Aware Streaming Fabric-based Scan Test Methodology Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Purushotham, Ajay	DMA Burst Mode Fault Detection: Custom MBIST Strategies for Comprehensive Testing
R
Rajski, Janusz	Automated Selection of Optimal EDT Input Configuration
Ramesh, Saidapet	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Ramesh, Venkat	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Ramesh, Venkat	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Rao, Shamitha	Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink
Rearick, Jeff	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Rodko, Daniel	Ultra dense SRAM Cell Test Challenges
Rodriguez Condia, Josie Esteban	Early Reliability Estimation in Hardware Accelerators through an Improved Colored Petri Net Approach
Romain, Luc	Early Testing of Memory Redundant Row Elements Early Testing of Memory Redundant Row Elements
Roy, Sourav	MUX-based Polymorphic Registers and FSMs to Protect Against Non-invasive Voltage Fault Injection Attacks
Ruospo, Annachiara	Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
S
Sahoo, Deepesh	TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale
Saikia, Jyotirmoy	Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness
Sanchez, Ernesto	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Sauer, Matthias	Influence of Automated Test Equipment Drift on Process Capability Studies Influence of Automated Test Equipment Drift on Process Capability Studies
Savino, Alessandro	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Schlitt, Lawrence	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
Schramm, Lori	Early Testing of Memory Redundant Row Elements Persistent High-Bandwidth IJTAG Data Delivery Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks Early Testing of Memory Redundant Row Elements
Schweizer, Simon	Influence of Automated Test Equipment Drift on Process Capability Studies Influence of Automated Test Equipment Drift on Process Capability Studies
Sechen, Carl	An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
Sehgal, Varun	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
Senarathna, Danushka	Deep Learning-based IC Monitoring Deep Learning-based IC Monitoring
Serlis, Emmanouil Anastasios	Combined Array and ADC Structural Test for RRAM-based Multiply-and-accumulate Circuits
Setty, Ramu	Sharing Scan Bandwidth Across Die to Die in MCM Package
Shah, Kashish	Machine Learning Assisted Vmin Prediction
Shaikh, Saghir	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Shamsi, Kaveh	Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis
Sharma, Manish	Chain Cell-Aware Diagnosis Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects Advanced fault model, diagnosis and applications for deep nanometer process
Sharma, Mohit	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
Sharma, Sandipan	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Shenoy, Jaidev	Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time
Shin, Minju	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Shirasu, Hideki	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
Shivarudraiah, Manjushree	Enhancing scan coverage in mixed signal designs by clock and reset manipulation during testing
Shrivastava, Shubhendu	Stress Aware Quiescent Current Test Optimization
Shtulman, Ari	Enhancing scan coverage in mixed signal designs by clock and reset manipulation during testing
Singh, Adit	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Singh, Prof. Virendra	Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time
Sinha, Arani	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Sinha, Prachi	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Son, Youngseok	Advanced fault model, diagnosis and applications for deep nanometer process
Sonza Reorda, Matteo	Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Srinivasan, Uma	Ultra dense SRAM Cell Test Challenges
Stelmach, Artur	Chain Cell-Aware Diagnosis Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects
Stepniewska, Marta	Persistent High-Bandwidth IJTAG Data Delivery
Su, Fei	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
Su, Yu	IEA-Plugin: An AI Agent Reasoner for Test Data Analytics
Subashchandran, Dharini	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
Sun, Bin	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Sun, Xinyu	Machine Learning Assisted Vmin Prediction
Sun, Yutao	Graph Attention Network Based Fault Prediction Framework for Functional Safety Verification
Sung, Gijong	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Sunter, Stephen	Scan Test for 99% Defect Coverage of R-2R DACs
Suri, Jyotika	Structural Testing on SLT Platform with HSAT IP & High-Speed I/O Access
Szymanski, Przemyslaw	Persistent High-Bandwidth IJTAG Data Delivery
T
T, Gokul	AMBA Qchannel based power management VIP for Efficient low power validation
Tahoori, Mehdi	Testing of Passive Memristive Crossbars in AI Hardware Accelerators Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
Takashima, Fumiaki	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications
Talukdar, Jonti	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
Tamakloe, Kelvin	Statistical Analysis of the Nonlinearity Errors of Unary and Binary-Weighted DACs
Tan, Xuanyi	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications
Tancorre, Vincenzo	Assessment of System-Level Test programs in Automotive SoCs
Taouil, Mottaqiallah	Device-Aware Test for Threshold Voltage Shifting in FeFET Combined Array and ADC Structural Test for RRAM-based Multiply-and-accumulate Circuits Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection Device-Aware Test for Threshold Voltage Shifting in FeFET
Thapar, Dhruv	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages
Thapar, Dhruv	FeTest: Testing of FeFET-Based Memory Arrays
Thekke Veetil, Ratheesh	DMA Burst Mode Fault Detection: Custom MBIST Strategies for Comprehensive Testing
Thorpe, Ryan	Ultra dense SRAM Cell Test Challenges
Tian, Katherine	Scan Strategies for High Quality Latch Array Testing Scan Strategies for High Quality Latch Array Testing
Tian, Yue	Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost
Tie, Junbo	STARTS: Simulation Traits Assisted Random Test Selection for Multiprocessor Verification
Tokuz, Ahmet	Enhancing scan coverage in mixed signal designs by clock and reset manipulation during testing
Tragoudas, Spyros	Deep Learning-based IC Monitoring Deep Learning-based IC Monitoring
Trawka, Maciej	Automated Selection of Optimal EDT Input Configuration
Traynor, Stephen	Full enablement of Very Low Voltage testing to deliver Zero Defect Quality automotive products Shifting-left Zero Defect Scan Test Development to Launch Automotive PPM-ready products
Tsai, Hans	Precise Approach to ATPG: Handling Timing Exceptions for Better Small Delay Defect Coverage
Tseng, Nan-Hsin	Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2 Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Tummalapalli, Sridutt	Thermal Management in System Level Test: Analysis of existing solutions and an introduction to advanced liquid cooled memory solutions
Tyagi, Vistrita	Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink
Tyszer, Jerzy	Automated Selection of Optimal EDT Input Configuration
Törmänen, Markus	Secure and Efficient Sharing of On-Chip Resources
U
Udaiwal, Neha	Low Noise 20-bit DAC for ATE
Urban, Szczepan	Chain Cell-Aware Diagnosis Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects Advanced fault model, diagnosis and applications for deep nanometer process
V
Varshini, Shreya	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Varshini, Shreya	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Vasileiou, Christos	Teaching Llamas to Test: A Language-Based Approach
Veda, Gaurav	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects
Venkatachalam, Anand	Influence of Automated Test Equipment Drift on Process Capability Studies Influence of Automated Test Equipment Drift on Process Capability Studies
Vettori, Riccardo	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Villegas Castillo, Ernesto Cristopher	Early Reliability Estimation in Hardware Accelerators through an Improved Colored Petri Net Approach
von Staudt, Hans Martin	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Vunnam, Gautham	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Vunnam, Gautham	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
W
Waheed, Muhammad	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Waicukauski, John	Improving Deterministic Test Pattern Generation through Massive Static Learning
Wang, Cao	FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
Wang, Changhao	Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET
Wang, Kuo-An	5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
Wang, Li-C	IEA-Plugin: An AI Agent Reasoner for Test Data Analytics
Wang, Lin	Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET
Wang, Zhijun	Graph Attention Network Based Fault Prediction Framework for Functional Safety Verification
Wen, Charles H.-P.	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
Werner, Matthias	Influence of Automated Test Equipment Drift on Process Capability Studies Influence of Automated Test Equipment Drift on Process Capability Studies
Wisnesky II, Carl	Pseudo Random Low Power Built in Self Test
Withey, Preston	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects
Wohl, Peter	Improving Deterministic Test Pattern Generation through Massive Static Learning
Wojnowska, Katarzyna	Early Testing of Memory Redundant Row Elements Early Testing of Memory Redundant Row Elements
Won, Jun Yeon	Method for Diagnosing Clock Jitter Using FPGA
Wu, Cheng-Wen	Chiplet Interconnect Test and Repair
Wu, Jiaming	QuEST: Quantitative Entropy-based Security and Trojan Detection Framework for Confidentiality Verification
Wu, Robert	Machine Learning Assisted Vmin Prediction
X
Xiao, T. Patrick	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Xiong, Jinjun	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Xu, Boxun	Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Xun, Hanzhi	Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET
Xun, Hanzhi	Combined Array and ADC Structural Test for RRAM-based Multiply-and-accumulate Circuits
Y
Yang, Derek Hong-Yi	Optimizing Sensing Point Placement for High-Multi-Site Testing on Device Interface Boards
Yang, Giyoung	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Yang, Hao-Yu	Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2 Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Yang, Sunny	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Yang, Sunny	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Ye, Jing	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Yenna, Deepika Reddy	Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink
Yerakondappagari, Srinath Reddy	Thermal Management in System Level Test: Analysis of existing solutions and an introduction to advanced liquid cooled memory solutions
Yin, Chujun	Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET
Yin, Yuxuan	Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Yindong, Xiao	FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
Yuan, Sicong	Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET
Z
Zak, Marcel	Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Zhang, Huizi	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Zhang, Jianfeng	STARTS: Simulation Traits Assisted Random Test Selection for Multiprocessor Verification
Zhang, Mingtao	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Zhang, Rengang	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Zheng, Yuegui	Test Bin Entitlement: Yield Outlier Detection using Die Area and LLM based Bin-Grouping
Zhou, Li	STARTS: Simulation Traits Assisted Random Test Selection for Multiprocessor Verification
Zimnowlodzki, Piotr	Chain Cell-Aware Diagnosis Advanced fault model, diagnosis and applications for deep nanometer process
Å
Åhlund, Joel	Secure and Efficient Sharing of On-Chip Resources

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