ITC 2025: IEEE INTERNATIONAL TEST CONFERENCE

A
Abu-Gosh, Fayez	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Aderholz, Ernst	Influence of Automated Test Equipment Drift on Process Capability Studies
Agnihotri, Pratishtha	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
Ahmed, Shakil	Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis
Ahmed, Soyed Tuhin	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Aljuffri, Abdullah	Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection
Anjaneyareddy, Arun Kumar	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Appel, Megan	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Au, Albert	Early Testing of Memory Redundant Row Elements
B
Banerjee, Sanmitra	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications
Bellarmino, Nicolo	Device-Aware Test for Threshold Voltage Shifting in FeFET
Bellizia, Davide	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Bennett, Christopher H.	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Bhoumik, Partho	Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages
Bhunia, Swarup	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Blair, Steve	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
Blanton, Shawn	IC-PEPR: PEPR Testing Goes Intra-Cell
Bonsu, Godfred Osei	Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
Brahmi, Mohammed Zine E.	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Brea, Brandon	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Bruce, Isaac	Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
Burchard, Jan	Persistent High-Bandwidth IJTAG Data Delivery Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
C
Caggioni, Francesco	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Cantoro, Riccardo	Device-Aware Test for Threshold Voltage Shifting in FeFET Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Chakrabarty, Krishnendu	LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging OCTANE: On-Chip Telemetry-based Anomaly Notification Engine Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages
Chakravadhanula, Krishna	Pseudo Random Low Power Built in Self Test
Chao, Yu-Hong	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
Chao, Zhiteng	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Chaplot, Nipun	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Chatterjee, Abhijit	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Chatterjee, Atri	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Chattopadhyay, Rita	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
Chatzopoulos, Odysseas	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
Chaudhuri, Arjun	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages
Chen, Danyang	Device-Aware Test for Threshold Voltage Shifting in FeFET
Chen, Degang	Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
Chen, Dong-Yi	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Chen, Harry	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
Chen, Jeffery Y.-C.	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
Chen, Rebecca	Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Chen, Yerong	Scan Strategies for High Quality Latch Array Testing
Cheng, Ding-Wei	Debugging and Preventing Abnormally High Vmin During Logic Scan Test Bring-up
Cheng, Jason W.-Y.	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
Cheng, Quan	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Cheng, Wu-Tung	Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects
Chern, Mason	Debugging and Preventing Abnormally High Vmin During Logic Scan Test Bring-up
Chi, Hao-Yang	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Chickermane, Vivek	Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Chillarige, Sameer	Pseudo Random Low Power Built in Self Test
Chin, Jeremy	Scan Strategies for High Quality Latch Array Testing
Cho, Kyung-Rak	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Cho, Muyun	Advanced fault model, diagnosis and applications for deep nanometer process
Chuang, Po-Yao	Chiplets' Die-to-Die Interconnect Repair Language (IRL)
Chung, Cheng-En	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Costa, Andrea	Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Cote, J-F	Persistent High-Bandwidth IJTAG Data Delivery
Czerniawski, Kacper	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
D
D'Souza, Jayant	Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects Advanced fault model, diagnosis and applications for deep nanometer process
Dasgupta, Aritra	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Dempsey, Ryan	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Devrani, Gaurav	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Dharmaraj, Gowsika	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Dharmavaram, Ramanath	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Di Carlo, Stefano	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Dixit, Harish	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Dolmeta, Alessandra	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Domanski, Peter	LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale
Du, Bin	Scan Strategies for High Quality Latch Array Testing
Dworak, Jennifer	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
E
Etono, Nathalie	Test Pattern Aware Streaming Fabric-based Scan Test Methodology
F
Farnaghinejad, Behnam	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Feinberg, Ben	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Ferdous, Md Rezoan	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Fieback, Moritz	Device-Aware Test for Threshold Voltage Shifting in FeFET
Firouzi, Farshad	LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale
Forte, Domenic	QuEST: Quantitative Entropy-based Security and Trojan Detection Framework for Confidentiality Verification
Fowler, Aric	An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
G
Galli, Alessia	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Gaudet, Jonathan	Persistent High-Bandwidth IJTAG Data Delivery Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Gebregiorgis, Anteneh	Stress Aware Quiescent Current Test Optimization
Gizopoulos, Dimitris	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
Gnawali, Krishna	Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Goel, Sandeep Kumar	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost
Goh, Szu Huat	Debugging and Preventing Abnormally High Vmin During Logic Scan Test Bring-up
Goyal, Saket	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
Graf, Tyler	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Grosso, Michelangelo	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Gu, Feng	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Guglielminetti, Iacopo	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Gumudavelli, Suman	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Gunnes, Jo	Stress Aware Quiescent Current Test Optimization
Gupta, Sameeksha	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Gurram, Venkata.Anilkumar Reddy	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
H
Hall, Austen	Ultra dense SRAM Cell Test Challenges
Hamdioui, Said	Stress Aware Quiescent Current Test Optimization Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection Device-Aware Test for Threshold Voltage Shifting in FeFET
Harith, Ashrith S	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
Hashimoto, Masanori	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Hati, Arjun	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
He, Chen	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Hefenbrock, Michael	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
Henzler, Philip	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Hong, Heeil	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Hornicek, Gregory	Ultra dense SRAM Cell Test Challenges
Hsieh, Bing-Han	Debugging and Preventing Abnormally High Vmin During Logic Scan Test Bring-up
Huang, Hsuan-Yin	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
Huhn, Sebastian	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Hung, Hsin-Wei	Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2 Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Huott, William	Ultra dense SRAM Cell Test Challenges
Hwang, Sangjoon	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
I
Iida, Minoru	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
Iwata, Hiroyuki	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications
J
J N, Ravi	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs Shifting-left Zero Defect Scan Test Development to Launch Automotive PPM-ready products
Jain, Dipali	Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis
Jaishi Mishra, Manish	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Janicki, Jakub	Chain Cell-Aware Diagnosis Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects
Janiszewski, Wojciech	Persistent High-Bandwidth IJTAG Data Delivery
Jauhri, Ahbinav	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Jian, Jun-Han	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Jiao, Xun	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Jurga, Krzysztof	Scan Test for 99% Defect Coverage of R-2R DACs
K
Kakollu, Vijay	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Kalla, Priyank	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
Kampmann, Matthias	Persistent High-Bandwidth IJTAG Data Delivery Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Karimpour, Saeid	Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
Keim, Martin	Persistent High-Bandwidth IJTAG Data Delivery Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Khoshzaban, Reza	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Kim, Deasun	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Kim, Min-Kyu	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Kim, Seoyeon	IEA-Plugin: An AI Agent Reasoner for Test Data Analytics
Kobayashi, Norio	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
Kolahimahmoudi, Nima	Device-Aware Test for Threshold Voltage Shifting in FeFET
Kundu, Subhadip	Debugging and Preventing Abnormally High Vmin During Logic Scan Test Bring-up
L
Laisne, Michael	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Lee, Frank	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost
Lee, Jim	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Lee, Kuen-Jong	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Li, Chaobo	Device-Aware Test for Threshold Voltage Shifting in FeFET
Li, Chien-Mo	Debugging and Preventing Abnormally High Vmin During Logic Scan Test Bring-up
Li, Huawei	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Li, Peng	Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Li, Wei	IC-PEPR: PEPR Testing Goes Intra-Cell
Li, Wenxing	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Li, Xiaowei	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Li, Xiuyan	Device-Aware Test for Threshold Voltage Shifting in FeFET
Liang, Aaron C.-W.	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
Liang, Chien-Hsing	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
Liang, Chien-Hsing	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Liang, Jason	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Liang, Yuan	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Liao, Wang	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Lim, Hyunyul	Advanced fault model, diagnosis and applications for deep nanometer process
Lin, Fred	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Lin, Hen-Ming	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
Lin, Longyang	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Liou, Jing-Jia	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
Liu, Min-Hsin	Debugging and Preventing Abnormally High Vmin During Logic Scan Test Bring-up
Liu, Zizhen	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Loh, Lay Hoon	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Lyu, Hongqin	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
M
Mah, Roger	Early Testing of Memory Redundant Row Elements
Mahadevan, Subramanian	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
Makris, Yiorgos	An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
Marinella, Matthew J.	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Marinissen, Erik Jan	Chiplets' Die-to-Die Interconnect Repair Language (IRL)
Martin, Denis	Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Masera, Guido	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Mayahinia, Mahta	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
Meehl, Dale	Pseudo Random Low Power Built in Self Test
Meier, Reinhard	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Mitra, Subhasish	IC-PEPR: PEPR Testing Goes Intra-Cell
Moeskops, Noeël	Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection
Moussa, Dina	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
Mrugalski, Grzegorz	Automated Selection of Optimal EDT Input Configuration
Mu, Jianan	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Mukherjee, Gitanjali	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications
Mukherjee, Nilanjan	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
N
Nakamura, Masayuki	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
Nam, Incheol	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Nandakumar, Bharath	Pseudo Random Low Power Built in Self Test
Naresh, Nikita	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Natarajan, Suriyaprakash	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Nelapatla, Bala Tarun	Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Nezhadi, Ali	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
Nigh, Chris	IC-PEPR: PEPR Testing Goes Intra-Cell Debugging and Preventing Abnormally High Vmin During Logic Scan Test Bring-up
Noble, Brian	Ultra dense SRAM Cell Test Challenges
Nti Darko, Emmanuel	Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
O
O'Donnell, Mat	Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Oak, Chaitali	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Olejarz, Michal	Persistent High-Bandwidth IJTAG Data Delivery
Ortega, Eduardo	LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale OCTANE: On-Chip Telemetry-based Anomaly Notification Engine Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
P
Paik, Woohyun	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
Pan, Gung-Yu	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
Pandey, Abhinav	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Papadimitriou, George	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
Parasrampuria, Mayank	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Parekhji, Rubin	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications
Paria, Sudipta	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Park, Jaeseok	Advanced fault model, diagnosis and applications for deep nanometer process
Patel, Ayush	Persistent High-Bandwidth IJTAG Data Delivery
Patel, Nehal	Scan Strategies for High Quality Latch Array Testing
Patidar, Ankita	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost
Peng, Ching-Nen	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
Pentyala, Srimaiyee	Full enablement of Very Low Voltage testing to deliver Zero Defect Quality automotive products
Perkovic, Martina	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Polian, Ilia	Influence of Automated Test Equipment Drift on Process Capability Studies
Pomeranz, Irith	Functional Logic Diagnosis with Observation Points on Next-State Variables
Porsia, Antonio	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Pradeep, Wilson	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Prakash, Palanisamy	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Przybysz, Olga	Persistent High-Bandwidth IJTAG Data Delivery
Purdy, Ruben	IC-PEPR: PEPR Testing Goes Intra-Cell
Purohit, Amit	Test Pattern Aware Streaming Fabric-based Scan Test Methodology
R
Rajski, Janusz	Automated Selection of Optimal EDT Input Configuration
Ramesh, Saidapet	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Ramesh, Venkat	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Rearick, Jeff	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Rodko, Daniel	Ultra dense SRAM Cell Test Challenges
Romain, Luc	Early Testing of Memory Redundant Row Elements
Ruospo, Annachiara	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
S
Sahoo, Deepesh	LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale
Sanchez, Ernesto	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Sauer, Matthias	Influence of Automated Test Equipment Drift on Process Capability Studies
Savino, Alessandro	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Schlitt, Lawrence	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
Schramm, Lori	Persistent High-Bandwidth IJTAG Data Delivery Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks Early Testing of Memory Redundant Row Elements
Schweizer, Simon	Influence of Automated Test Equipment Drift on Process Capability Studies
Sechen, Carl	An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
Sehgal, Varun	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
Shaikh, Saghir	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Shamsi, Kaveh	Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis
Sharma, Manish	Chain Cell-Aware Diagnosis Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects Advanced fault model, diagnosis and applications for deep nanometer process
Sharma, Mohit	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
Sharma, Sandipan	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Shin, Minju	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Shirasu, Hideki	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
Shrivastava, Shubhendu	Stress Aware Quiescent Current Test Optimization
Singh, Adit	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Sinha, Arani	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Sinha, Prachi	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
Son, Youngseok	Advanced fault model, diagnosis and applications for deep nanometer process
Sonza Reorda, Matteo	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Srinivasan, Uma	Ultra dense SRAM Cell Test Challenges
Stelmach, Artur	Chain Cell-Aware Diagnosis Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects
Stepniewska, Marta	Persistent High-Bandwidth IJTAG Data Delivery
Su, Fei	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
Su, Yu	IEA-Plugin: An AI Agent Reasoner for Test Data Analytics
Sun, Bin	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Sung, Gijong	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Sunter, Stephen	Scan Test for 99% Defect Coverage of R-2R DACs
Szymanski, Przemyslaw	Persistent High-Bandwidth IJTAG Data Delivery
T
Tahoori, Mehdi	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
Takashima, Fumiaki	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications
Talukdar, Jonti	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
Tan, Xuanyi	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications
Taouil, Mottaqiallah	Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection Device-Aware Test for Threshold Voltage Shifting in FeFET
Thapar, Dhruv	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages
Thorpe, Ryan	Ultra dense SRAM Cell Test Challenges
Tian, Kethreine	Scan Strategies for High Quality Latch Array Testing
Tian, Yue	Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost
Trawka, Maciej	Automated Selection of Optimal EDT Input Configuration
Traynor, Stephen	Full enablement of Very Low Voltage testing to deliver Zero Defect Quality automotive products Shifting-left Zero Defect Scan Test Development to Launch Automotive PPM-ready products
Tseng, Nan-Hsin	Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2 Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Tyszer, Jerzy	Automated Selection of Optimal EDT Input Configuration
U
Urban, Szczepan	Chain Cell-Aware Diagnosis Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects Advanced fault model, diagnosis and applications for deep nanometer process
V
Varshini, Shreya	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Veda, Gaurav	Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects
Venkatachalam, Anand	Influence of Automated Test Equipment Drift on Process Capability Studies
Vettori, Riccardo	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
von Staudt, Hans Martin	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Vunnam, Gautham	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
W
Waheed, Muhammad	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Wang, Changhao	Device-Aware Test for Threshold Voltage Shifting in FeFET
Wang, Kuo-An	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
Wang, Li-C	IEA-Plugin: An AI Agent Reasoner for Test Data Analytics
Wang, Lin	Device-Aware Test for Threshold Voltage Shifting in FeFET
Wen, Charles H.-P.	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
Werner, Matthias	Influence of Automated Test Equipment Drift on Process Capability Studies
Wisnesky II, Carl	Pseudo Random Low Power Built in Self Test
Withey, Preston	Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects
Wojnowska, Katarzyna	Early Testing of Memory Redundant Row Elements
Wu, Jiaming	QuEST: Quantitative Entropy-based Security and Trojan Detection Framework for Confidentiality Verification
X
Xiao, T. Patrick	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Xiong, Jinjun	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Xu, Boxun	Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Xun, Hanzhi	Device-Aware Test for Threshold Voltage Shifting in FeFET
Y
Yang, Giyoung	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Yang, Hao-Yu	Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2 Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Yang, Sunny	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Ye, Jing	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Yin, Chujun	Device-Aware Test for Threshold Voltage Shifting in FeFET
Yin, Yuxuan	Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Yuan, Sicong	Device-Aware Test for Threshold Voltage Shifting in FeFET
Z
Zak, Marcel	Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Zhang, Huizi	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Zhang, Mingtao	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Zhang, Rengang	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Zimnowlodzki, Piotr	Chain Cell-Aware Diagnosis Advanced fault model, diagnosis and applications for deep nanometer process

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