Carlos is currently a lead hardware designer and architect who has led multiple generations of System Level Test Solutions currently used in Intel's ATMs. Carlos first joined Intel in 2000 as a Systems Engineer in the Embedded Group in Arizona. Subsequently he moved to become a Platform Architect for silicon development, later as a Senior Technical Marketing Engineer and eventually moved to the Technology Manufacturing Group as Test and R&D Engineer. He has held several technical and leadership positions including roles in embedded systems, analog designs, digital FPGA (Field Programmable Gate Array) designs, post-silicon debug/validation, firmware development, and tester architecture including test methods.​