ABSTRACT. Computational integrity is crucial in modern hardware, particularly in data centers where Silent Data Corruptions (SDCs) threaten reliability. Traditional error detection mechanisms struggle to capture SDCs, and existing testing methods face significant scalability challenges. We propose an LLM-aided approach to generate targeted test cases for SDC detection in RISC-V CV32E40P cores. Our method maximizes voltage droops in specific hardware modules, increasing the likelihood of SDCs. Experiments show that our method improves SDC detection efficacy while reducing the number of required test cases. By leveraging LLM-aided test case generation, our method enhances testing efficiency, contributing to more effective in-field SDC detection.

ABSTRACT. Safety-critical applications like autonomous driving require rigorous functional safety assurance. We propose a safety-guided test pattern generation framework for transition faults using Launch-on-Capture (LOC) delay testing. The neural twin models standard cell transitions with Cell-Nets (MLPs) and replaces inter-cell wires with neural connections. Its end-to-end differentiability enables backpropagation-based test generation, enhancing fault propagation to primary outputs (POs). The framework supports non-binary criticality-factor (CF) assignment, leveraging CF to guide test pattern generation. NeuralGPT employs concurrent test generation with GPU acceleration, achieving superior safety-guided fault propagation and scalability in benchmark evaluations.

ABSTRACT. As artificial intelligence becomes integral in domains like healthcare and autonomous systems, dedicated hardware accelerators are becoming increasingly essential. These are structurally tested at manufacturing, independent of the AI model executed. However, in-field reliability demands model-based functional testing using the Deep Neural Networks (DNNs) deployed during inference. Faults in DNNs can degrade performance, making in-field testing critical under memory and time constraints. We propose a framework to generate a set of test patterns according to memory constraints while ensuring effective fault coverage of the fault distribution through joint optimization of patterns. Results show 100% coverage, outperforming random and adversarial inputs.

ABSTRACT. This paper proposes a push-on mating 57- to 81-GHz mm-wave interface for Automated Test Equipment (ATE). This interface does not require screw fastening, yet maintains high repeatability. Additionally, it is expected to be miniaturized and multi-port, allowing it to be placed in large quantities on an ATE. This contributes to the reduction of testing costs for mm-wave devices.

ABSTRACT. Digital scan-based ATPG was recently described for ‘random analog’ circuits with >95% coverage of the shorts and opens prescribed by IEEE P2427, with test times <1 ms and analog defect simulation times <1 hour, but coverage for a dual-string DAC was much lower. This paper shows >99% coverage in <20 µs is possible for DACs that have a binary R-2R and/or unary segment resistor structure, with simple design-for-scan-test circuit changes that do not significantly affect performance or area. These DAC types are used in many applications because of their simplicity, speed, and area.

ABSTRACT. High-resolution waveform generation is crucial for BIST and biomedical applications, where signal fidelity is critical. Traditional methods rely on expensive ATE, making cost-effective alternatives essential. This paper presents a 24-bit waveform generation approach using two low-cost 14-bit DACs with dithering-based enhancement for high purity. A 14-bit ADC is used as measurement device. Measured results from a TSMC 0.18 μm implementation show ENOB of 20 bits and distortion exceeding 130 dB, validating the design. The proposed method provides a low-cost, high-precision solution for embedded systems requiring accurate signal generation with minimal hardware overhead.

ABSTRACT. Process capability index is a useful metric for maintaining the quality of semiconductor manufacturing. We address, for the first time, the influence of Automated Test Equipment (ATE) drift on process capability. Influence of ATE calibration on the measurement results have been analyzed using polynomial regression. We outline an integrated approach for the interpretation of process capability indices which considers not only the part variation associated with device manufacturing process, but also the measurement variation due to wearing calibration of the ATE. Using polynomial regression model of ATE correction data and Device Under Test (DUT) measurement results we demonstrate that it is possible to broadly distinguish process and measurement variation.

ABSTRACT. 5G application achieves high speed and wide bandwidth performance (60 GHz) which needs precise impedance matching. From testing industry point of view, test interface diagnose will suffer Device under Test sensitive contact which impact impedance matching. This paper introduces an innovative methodology to measure S-parameter by Automatic Test Equipment built-in Vetor Network Analyzer without mounting external instrument. In that way ATE could automatically power up the components on test interface and leverage ATE to measure S-parameter. Engineers could finally avoid device contact. The methodology significantly enhances test setup quality and debug efficiency, improving maintenance cycle time with simple/easier process.

ABSTRACT. The increasing integration of optical and electronic components has led to the widespread adoption of Photonic Integrated Circuits (PICs). As PIC complexity grows, wafer-level testing becomes a critical challenge, requiring both electrical and optical characterization with nanometric alignment precision. This paper presents Eclipse Dynamic, an innovative probe card integrating both electrical probes and an embedded Fiber Array Unit (FAU) actuated by piezoelectric elements within the Probe Head, enabling automated, high-precision optical alignment without external positioning equipment. A preliminary feasibility study is conducted to characterize the FAU’s dynamic alignment capabilities and to demonstrate the system’s ability to achieve nanometric alignment accuracy.

ABSTRACT. The "Shift-Left" Design-for-Test (DFT) approach focuses on early testability evaluation at the Register Transfer Level (RTL) to optimize Power-Performance-Area-Testability (PPAT) and accelerate Time-to-Market (TTM). This paper explores how Large Language Models (LLMs) can enhance RTL-based DFT. A multi-LLM collaboration is proposed to autonomously perform Partial Scan Selection (PSS) and Test Point Insertion (TPI). Two data augmentation methods—back-annotating heuristic results and using advanced LLMs guided by DFT knowledge—are introduced. Direct Preference Optimization (DPO) with real feedback from commercial EDA tools further refines the approach. Experimental results show improved testing metrics compared to other methods, including ChatGPT-4.

ABSTRACT. Scan-based Design-for-Testability (DFT) is crucial for achieving high test quality in modern digital circuits, especially with 3D integration and chiplet-based systems. However, it faces challenges in ensuring testability at deep logic levels. Traditional solutions rely on Test Point (TP) insertion, which incurs high design costs. To address this, we propose LITE, an ATPG-aware scan instrumentation technique that leverages functional flip-flops for controllability and observability. Our approach significantly improves testability in terms of pattern count and coverage while incurring lower overhead than TP-based methods, offering a scalable and low-cost alternative for complex designs.

ABSTRACT. The primary purpose of this work is to automate selection of key attributes of a test data compression environment such as Embedded Deterministic Test. Given a test compression setup, the main objective of the proposed approach is to quickly estimate the expected test pattern count, test data volume, and the resultant test application time within the framework of the actual test compression flow when using ATPG-produced test cubes. This way one can mimic a process of test cube merging and anticipate compressibility of the resultant test patterns without resorting to CPU-intensive solvers of linear equations.

ABSTRACT. High-bandwidth IJTAG over SSN allows an efficient test of large-scale logic chips and SOCs. It leverages a high-speed parallel bus to concurrently access many local IEEE-1687 IJTAG networks. Whenever the high-bandwidth IJTAG access mode is activated, it must first be configured through the global IJTAG network. The initial configuration and subsequent reconfigurations constitute a substantial test time overhead. This paper presents wide-ranging enhancements to the high-bandwidth IJTAG access such that it can remain active throughout the entire test session. This results in a significant reduction of test setup time and more efficient test delivery.

ABSTRACT. The IJTAG standard IEEE1687 addressed digital test needs but skipped many practical and physical-world test challenges. P1687.2 worked on an analog extension. The paper shows how quite a few of P1687.2’s concepts can enhance the base standard. It describes new concepts joining digital and analog test properties and behaviour with a consistent description. This spans from seemingly trivial aspects like bidirectionals and relays to co-existence with the full range of analog test. A case study validates how mixed-signal test procedure intent is captured in a new standard language (PDL2) which is retargeted across hierarchy levels, resolving conflicts for test pins and buses.

ABSTRACT. The increasing complexity of integrated circuits demands scalable and efficient design for testability (DFT) solutions to ensure cost-effective test access and functional correctness. Streaming Scan Network (SSN) and High-Bandwidth IJTAG over SSN (HB-IJTAG) enhance test efficiency by accelerating data transfer and optimizing execution. However, these technologies introduce validation challenges due to intricate control mechanisms and their large-scale deployment. This paper presents a holistic approach for generating and sequencing functional validation patterns by systematically leveraging SSN and HB-IJTAG to optimize efficiency. This methodology enables concurrent, robust validation of hundreds of DFT components, significantly improving test execution time.

ABSTRACT. Accurate chip performance prediction is essential in semiconductor manufacturing for energy efficiency and reliability. However, the transition of prediction models from legacy technology nodes to advanced technology nodes often results in poor performance due to process variations, data scarcity, and inconsistencies in feature and target nomenclature. We design a novel transfer learning framework that overcomes these challenges to adapt prediction models trained for a 16nm technology node for minimum operating voltage prediction at a 5nm node while using a small amount of 5nm chip data. A key innovation is the integration of features from silicon odometer sensors exclusive to the 5nm technology, which provides better correlations to the chip performance.

ABSTRACT. Silicon lifecycle management (SLM) is essential for the reliability and quality of silicon products. This work introduces On-Chip Telemetry-based anomaly Notification Engine (OCTANE), a SLM codesign method to monitor chip status using performance counters/sensors. OCTANE features on-chip anomaly scoring through high-speed Fixed Point arithmetic. We utilize a workload-agnostic unsupervised feature ranking and selection technique to provide general compute SLM generalizability. OCTANE demonstrates highly effective on-chip anomaly detection and subsequent diagnosis. OCTANE shows effective anomaly detection with accuracies above 0.96, maintains low area/power (1.2%/2.6%) overhead, and achieves subsequent diagnosis with accuracies surpassing 0.98.

ABSTRACT. This paper introduces IEA-plugin, a novel AI agent-based reasoning module developed as a new front-end for the Intelligent Engineering Assistant (IEA). The primary objective of IEA-plugin is to utilize the advanced reasoning and coding capabilities of Large Language Models (LLMs) to effectively address two critical practical challenges: capturing diverse engineering requirements and improving system scalability. Built on the LangGraph agentic programming platform, IEA-plugin is specifically tailored for industrial deployment and integration with backend test data analytics tools. Compared to the previously developed IEA-Plot (introduced two years ago), IEA-plugin represents a significant advancement, capitalizing on recent breakthroughs in LLMs to deliver capabilities that were previously unattainable.

ABSTRACT. At-speed logic scan tests are an important tool to ensure desired quality in mobile chips. During initial test pattern bring-up, tests that exhibit an unexpectedly high Vmin pose a risk of over-testing and production yield loss. This is particularly problematic if the Vmin of the test is significantly higher than that of the functional system workloads. In such situations, the at-speed logic scan test is debugged to find and resolve the source of the high Vmin. This paper describes an example case study of Vmin debug, in which a series of experiments are performed to identify the root cause as individual test patterns that capture the responses of unconstrained paths. We propose pre-silicon and post-silicon methods to improve Vmin by preventing problematic patterns and reducing the debug effort during test bring-up. Our methods have been verified on ATE to effectively improve Vmin by 28.83 mV to 39.33 mV with 0% to 0.5% pattern count inflation.

ABSTRACT. In advanced semiconductor development at 5nm and below, rapid yield ramp-up and defect identification are vital. Scan-based testing, the primary Design for Testability (DFT) method, faces challenges as scan chains are prone to defects, hindering yield learning. Traditional fault isolation, such as Laser Voltage Probing, is ineffective due to backside power rail constraints. Hardware solutions affect power, performance, and area (PPA), while software lacks precision. This paper introduces two methods: a multi-mode scan design with soft repair capability and a hybrid hardware-software approach. These enhance scan chain diagnosis, supporting faster yield ramp-up and defect identification.

ABSTRACT. High-coverage ATPG scan structural testing is a standard in the automotive industry for effectively screening logic gates with hard defects. Cell-aware testing further optimizes this by injecting defects into standard cell gates. However, latent defects remain difficult to expose, even under extreme test conditions. These defects may go undetected and fail in the field, posing a challenge for chip suppliers to diagnose and improve tests for mature production products. This work introduces a simulation-based approach to enhance latent defect screening by modeling soft resistive defects across voltage, process, and temperature, optimizing cell-aware stimuli to improve defect detection and reduce failure.

ABSTRACT. Streaming Fabric (SF) lowers total test application time (TAT) by simultaneously distributing high-speed test data among multiple cores in a SOC. However, concurrency is limited by the available bandwidth. This paper proposes a protocol aware SF-based solution that identifies redundancies in ATPG test patterns and delivers only meaningful data to cores by interleaving test data. It also proposes a heuristic bandwidth allocation algorithm that distributes bandwidth while accounting for TAT. Experimental results show that the protocol aware solution and the bandwidth allocation algorithm reduces the total test cycles by an average of 43% and 40%, respectively compared to baseline SF.

ABSTRACT. Latch arrays become increasingly popular due to their lower area overhead and power consumption compared to the alternative SRAM. We explore new scan strategies used in latch array design, their implementation flow, and the benefits of these changes to latch array test coverage. Scan solution offers smaller area overhead compared to BIST solution and provides failure analysis capability not available in BIST solution. This innovative approach achieved 100% SAF and TDF coverage for latch array core. Due to the complexity of clock gating and decoding logic in the surrounding logic, different latch array reset schemes are tested and compared.

ABSTRACT. This article considers logic diagnosis using functional sequences for defects that occur during functional operation and may not be detected by scan-based tests. The article suggests the insertion of observation points on next-state variables to collect additional fail data and thus improve the accuracy of logic diagnosis. The target faults are functionally possible transition or stuck-at faults that can cause a chip to fail during functional operation.