ABSTRACT. Computational integrity is crucial in modern hardware, particularly in data centers where Silent Data Corruptions (SDCs) threaten reliability. Traditional error detection mechanisms struggle to capture SDCs, and existing testing methods face significant scalability challenges. We propose an LLM-aided approach to generate targeted test cases for SDC detection in RISC-V CV32E40P cores. Our method maximizes voltage droops in specific hardware modules, increasing the likelihood of SDCs. Experiments show that our method improves SDC detection efficacy while reducing the number of required test cases. By leveraging LLM-aided test case generation, our method enhances testing efficiency, contributing to more effective in-field SDC detection.

ABSTRACT. Safety-critical applications like autonomous driving require rigorous functional safety assurance. We propose a safety-guided test pattern generation framework for transition faults using Launch-on-Capture (LOC) delay testing. The neural twin models standard cell transitions with Cell-Nets (MLPs) and replaces inter-cell wires with neural connections. Its end-to-end differentiability enables backpropagation-based test generation, enhancing fault propagation to primary outputs (POs). The framework supports non-binary criticality-factor (CF) assignment, leveraging CF to guide test pattern generation. NeuralGPT employs concurrent test generation with GPU acceleration, achieving superior safety-guided fault propagation and scalability in benchmark evaluations.

ABSTRACT. As artificial intelligence becomes integral in domains like healthcare and autonomous systems, dedicated hardware accelerators are becoming increasingly essential. These are structurally tested at manufacturing, independent of the AI model executed. However, in-field reliability demands model-based functional testing using the Deep Neural Networks (DNNs) deployed during inference. Faults in DNNs can degrade performance, making in-field testing critical under memory and time constraints. We propose a framework to generate a set of test patterns according to memory constraints while ensuring effective fault coverage of the fault distribution through joint optimization of patterns. Results show 100% coverage, outperforming random and adversarial inputs.

ABSTRACT. This paper proposes a push-on mating 57- to 81-GHz mm-wave interface for Automated Test Equipment (ATE). This interface does not require screw fastening, yet maintains high repeatability. Additionally, it is expected to be miniaturized and multi-port, allowing it to be placed in large quantities on an ATE. This contributes to the reduction of testing costs for mm-wave devices.

ABSTRACT. Digital scan-based ATPG was recently described for ‘random analog’ circuits with >95% coverage of the shorts and opens prescribed by IEEE P2427, with test times <1 ms and analog defect simulation times <1 hour, but coverage for a dual-string DAC was much lower. This paper shows >99% coverage in <20 µs is possible for DACs that have a binary R-2R and/or unary segment resistor structure, with simple design-for-scan-test circuit changes that do not significantly affect performance or area. These DAC types are used in many applications because of their simplicity, speed, and area.

ABSTRACT. High-resolution waveform generation is crucial for BIST and biomedical applications, where signal fidelity is critical. Traditional methods rely on expensive ATE, making cost-effective alternatives essential. This paper presents a 24-bit waveform generation approach using two low-cost 14-bit DACs with dithering-based enhancement for high purity. A 14-bit ADC is used as measurement device. Measured results from a TSMC 0.18 μm implementation show ENOB of 20 bits and distortion exceeding 130 dB, validating the design. The proposed method provides a low-cost, high-precision solution for embedded systems requiring accurate signal generation with minimal hardware overhead.

ABSTRACT. Process capability index is a useful metric for maintaining the quality of semiconductor manufacturing. We address, for the first time, the influence of Automated Test Equipment (ATE) drift on process capability. Influence of ATE calibration on the measurement results have been analyzed using polynomial regression. We outline an integrated approach for the interpretation of process capability indices which considers not only the part variation associated with device manufacturing process, but also the measurement variation due to wearing calibration of the ATE. Using polynomial regression model of ATE correction data and Device Under Test (DUT) measurement results we demonstrate that it is possible to broadly distinguish process and measurement variation.

ABSTRACT. 5G application achieves high speed and wide bandwidth performance (60 GHz) which needs precise impedance matching. From testing industry point of view, test interface diagnose will suffer Device under Test sensitive contact which impact impedance matching. This paper introduces an innovative methodology to measure S-parameter by Automatic Test Equipment built-in Vetor Network Analyzer without mounting external instrument. In that way ATE could automatically power up the components on test interface and leverage ATE to measure S-parameter. Engineers could finally avoid device contact. The methodology significantly enhances test setup quality and debug efficiency, improving maintenance cycle time with simple/easier process.

ABSTRACT. The increasing integration of optical and electronic components has led to the widespread adoption of Photonic Integrated Circuits (PICs). As PIC complexity grows, wafer-level testing becomes a critical challenge, requiring both electrical and optical characterization with nanometric alignment precision. This paper presents Eclipse Dynamic, an innovative probe card integrating both electrical probes and an embedded Fiber Array Unit (FAU) actuated by piezoelectric elements within the Probe Head, enabling automated, high-precision optical alignment without external positioning equipment. A preliminary feasibility study is conducted to characterize the FAU’s dynamic alignment capabilities and to demonstrate the system’s ability to achieve nanometric alignment accuracy.

ABSTRACT. This paper explores the portability and reusability of functional System-Level Test (SLT) methodologies across different System-on-Chip (SoC) design architectures. The proposed approach leverages the Device-tree Specification (DTS) of the Device-Under-Test (DUT) to enable automated test generation. By constructing a graph representation from the DTS, the methodology facilitates the creation of functional test programs across different SoC architectures through a simple graph traversal process, making it highly adaptable and efficient in simplifying SLT development.

ABSTRACT. Assessing AI systems reliability is essential before deploying them in safety-critical applications. While recent efforts have focused on improving model resilience to random hardware faults, meaningful comparison remains difficult due to the lack of standardized reference models. Different authors use different implementations, which makes comparisons unfair and biased: resilience is influenced by the training processes, the software framework, and data representations. To address these issues, this work introduces a benchmark suite of CNN models to test the resilience of DNNs. The benchmark is structured on different axes: software framework, hardware platform, data representation, task and dataset. It is aimed at providing a shared foundation for fair and reproducible resilience evaluation.

ABSTRACT. Identifying potential bugs early in the design flow is essential to mitigate vulnerability propagation and prevent costly fixes in later stages. The recent emergence of Large Language Models (LLMs) has demonstrated proficiency across various domains, including vulnerability assessment in hardware designs. Existing techniques primarily focus on generating security property or assertion for comprehensive verification, with less emphasis on bug detection. We propose a novel framework, LAMBDA, that leverages pre-trained LLM and retrieval-augmented generation (RAG) to identify relevant CWEs, generate SystemVerilog Assertions (SVAs) to detect deviations from intended behaviors, highlighting potential bugs. Experimental results demonstrate successful identification of eight unique bugs using LAMBDA in buggy OpenTitan SoC design from Hack@DAC'24 competition.

ABSTRACT. This paper proposes a novel multi-site functional testing methodology for hardware timers, essential components in safety-critical systems. The methodology employs a custom flexible tester modified for JTAG-based multi-site testing, enabling simultaneous evaluation of multiple devices under test (DUTs) alongside a golden chip for reference. By varying voltage and frequency conditions, the DUT’s timer behaviour is compared to the golden chip’s to identify faults such as transition delay and small delay faults. Experimental results demonstrate the effectiveness of the methodology in enhancing reliability and ensuring compliance with stringent safety standards like ISO26262 and DO-178C. This approach provides a scalable and adaptable solution for testing complex SoC designs in diverse safety-critical applications.

ABSTRACT. 5G FR2 applications achieve high-speed performance and wide bandwidth capabilities, requiring precise impedance matching. From the perspective of the testing industry, test interface diagnostics can be affected by sensitive contact with the Device Under Test, which impacts impedance matching. This paper presents an innovative methodology for measuring S-parameter using Automatic Test Equipment built-in Vector Network Analyzer. This allows engineers to avoid direct contact with the device, significantly improving test setup quality, debugging efficiency, and maintenance cycle times while offering a simpler and more streamlined process.

ABSTRACT. Ferroelectric Field-Effect Transistors (FeFETs) are promising candidates for non-volatile memory (NVM) technologies, particularly in embedded systems and edge computing, where performance and reliability are critical. Due to their unique physical properties, FeFETs exhibit defects, such as Threshold Voltage Shifting (TVS) caused by trap charges in the oxide layer, which are not captured by conventional defect models. This study applies the Device-aware Test (DAT) methodology to model these defects by integrating their impact into the device’s electrical parameters, calibrated with measurement data. Defect injection, circuit-level simulations and fault analysis are conducted to introduce realistic fault models. Finally, the March algorithm and Design-for-Test (DfT) solutions are proposed to effectively detect these defects.

ABSTRACT. Redundant elements in memories are used to enhance the manufacturing yield of silicon devices. Although redundant elements allocated during manufacturing tests are fully tested, unallocated elements remain untested. To increase device reliability, allocation of memory spares during in-field testing may become necessary throughout the lifecycle of a device. In other words, all redundant elements must be tested during manufacturing to avoid using defective spare in the field. This paper presents a novel hardware architecture and manufacturing test flow to systematically test all redundant row elements and preemptively identify defective ones. This solution ensures that only reliable unallocated spare elements remain available for in-system repair.

ABSTRACT. A fault list analysis methodology is proposed to determine how many Cell-Aware Test (CAT) defects can be detected by test patterns generated targeting the other fault models, including stuck-at faults (SAFs), transition-delay faults(TDFs), and small-delay defects (SDDs). Our analysis reveals that a proper ordering in fault simulation can accelerate the CAT fault simulation process. We evaluated our approach on a RISC-V core, synthesized using an industrial technology library. We demonstrated an innovative method to optimize CAT fault simulation by means of preliminary static fault list analysis, resulting in fault simulation runtime reduction of up to 80% for static and 35% for dynamic CAT faults.

ABSTRACT. Process capability index is a useful metric for maintaining the quality of semiconductor manufacturing. We address, for the first time, the influence of Automated Test Equipment (ATE) drift on process capability. An integrated approach for interpretation of process capability indices considers not only the part variation associated with device manufacturing process, but also the measurement variation due to wearing calibration of the ATE. With a polynomial regression model of ATE correction data and Device Under Test (DUT) measurement results we account for measurement variation due to ATE drift and understand how it influences process capability studies.

ABSTRACT. In this brief, we present the development of an on-chip sensor designed to monitor hot-carrier-induced (HCI) aging in NMOS transistors, utilizing the hot-carrier-induced series-resistance enhancement (HISREM) model. With a 10 MHz clock and SAR logic, the sensor generates a digital output proportional to device age under HCI stress, achieving 8-bit accuracy. Our methodology was developed using GF22FDSOI technology and evaluated over a 20-year period with extensive Cadence RelXpert simulations. We validate the sensors' robustness to process variations and random mismatches through 200 Monte Carlo (MC) iterations. INL and DNL evaluation is used to ensure that the accuracy of the design is sufficient even in the worst-case corner conditions.

ABSTRACT. High Bandwidth Memory (HBM) has emerged as a critical enabler for artificial intelligence (AI) workloads, offering massive bandwidth and low power consumption necessary to meet the growing computational demands of deep learning and high-performance computing. HBM is a pivotal piece of technology for AI training as well as AI inference due to its high bandwidth and comparable low latency, which enables speedy data access and its processing, helping in handling the large datasets and performing complex calculations. With AI models continuously expanding in complexity, efficient verification methodologies for HBM devices are essential to ensure reliability and performance across various configurations. Our approach presents robust, flexible verification framework for HBM devices.

ABSTRACT. This work discusses challenges of automated test equipment (ATE) for electric vehicles (EV) battery management systems (BMS) and introduces novel system-architectural solutions based on highly integrated system-on-a-chip (SOC) parametric measurement units (PMUs). The presented system-architectural solution and the integrated PMU SOC achieve the stringent requirements of BMS ATE, while realizing a high-density ATE system. Moreover, the presented architecture is scalable to support future BMS ATE trends and maintain EV safety, reliability and efficiency.

ABSTRACT. This work investigates Colored-Petri-Nets (CPN) for early reliability estimation in hardware accelerators, significantly reducing complexity during the early design stages of safety-critical systems. Our method builds high-level models of complex hardware accelerators to estimate reliability, integrating circuit characterization and fine-grain fault simulations on fundamental structures. We evaluate our methodology using six architecture variants of an on-chip hardware accelerator for deep learning (GPU's Tensor Cores). The results demonstrate that our approach reduces evaluation to 118x, achieving accuracy levels of up to 93.5% compared to exhaustive RT-level fault injection campaigns while enhancing engineering productivity for early-stage designs.

ABSTRACT. ICL introduced in IEEE 1687 (iJTAG) standard is a way to describe the instrument connectivity network known as the iJTAG network. An early consistency verification check is required between the ICL and the iJTAG network in the design to avoid expensive design edits done at a later stage in the DFT flow. This poster discusses a methodology to verify the consistency between the iJTAG network present in the design and its ICL by generating smart verification vectors for optimized simulation time while ensuring test completeness and ease of debuggability thus affecting the test cost positively.

ABSTRACT. Implementing Deep Neural Networks (DNNs) in hardware is essential due to rising Power-Performance-Area demands and the limitations of GPUs in meeting them. However, such accelerators are vulnerable to Fault Injection Attacks (FIAs). FAMOUS protects against FIAs by exploiting invariances in DNNs—particularly permutation invariance—by dynamically swapping convolutional channels and linear layer connections during runtime. This misleads attackers aiming to corrupt critical weights. We evaluate FAMOUS on transformer models across multiple datasets. Even with targeting 100 essential weights, accuracy drops are minimal compared to severe drops without protection. CNNs also benefit from FAMOUS, though to a lesser extent.

ABSTRACT. A significant challenge in semiconductor high volume manufacturing testing is the reduction of test times, which directly impacts production throughput and cost. This research investigates the application of shift overclocking methodologies in HVM, with a focus on the relationship between Intra-Die Variation, voltage and temperature with the scan shift clock frequencies. We analyzed the effectiveness of different dynamic shift equations in optimizing test times across a range of IDV levels. By leveraging the developed equations for real-time test adjustments, semiconductor manufacturers can achieve a more streamlined testing process, resulting in reduced test times and enhanced production efficacy.

ABSTRACT. This paper introduces a novel jitter injection module that integrates a programmable SiGe delay line (PDL) with an FPGA-based arbitrary signal generator, enabling flexible generation of diverse jitter profiles. The proposed solution enables cost-effective generation of Gaussian-distributed random jitter (RJ), sinusoidal/periodic jitter, and deterministic jitter (DJ) in unlimited combinations. Experimental results demonstrate injection of both periodic and random jitter components onto 28 GHz clock signals, with the module achieving ±7.4 femtosecond (fs) accuracy for random jitter and high flexibility in generating arbitrary profiles (e.g., sinusoidal jitter).

ABSTRACT. Most large chip designs today utilize a Core-based testing methodology. Most Core-based test methodologies utilize DFT logic from chip testing within each Core and use boundary isolation logic to make testing of the Cores independent from each other. One of the older chip testing approaches was to use MISRs - sometimes for Logic BIST and sometimes for test compression of ATPG patterns. Except for LBIST, using MISRs for Core testing is not common. We show a DFT approach in which MISRs are used as the test compression mechanism within Cores utilizing an LBIST-like running signature so that the signatures do not have to be checked very frequently.

ABSTRACT. This paper introduces a highly reliable delay-based weak FPGA PUF, leveraging stochastic delay measurement with PLLs. The delay of delay-lines is precisely measured using the proposed fully synchronous stochastic delay measurement method. Thus, the reliability surpasses that of conventional PUFs that depend on asynchronous circuits or measurement. In the evaluation, the inter-chip HD of the proposed PUF without Spread Spectrum Clock Generator (SSCG) is 47.79%, and the intra-chip HD is 0.0052%, which is about 1/100 of the conventional method. With SSCG, the inter-chip HD of the proposed PUF is 47.98%, and the intra-chip HD is 0.00092%, which is about 1/5 of the value in the absence of SSCG.

ABSTRACT. This work introduces a low-noise digital-to-analog converter (DAC) in a custom automated test equipment (ATE) environment designed to meet the stringent demands of advanced semiconductor testing. Total integrated input referred RMS noise of 9.15uV was obtained for 0.1Hz to 50kHz range. Moreover, DNL error of 1.6LSB and INL error of 4LSB were obtained post calibration.

ABSTRACT. Evaluating the clock quality of a device's phaselocked loop (PLL) using automatic test equipment (ATE) at an affordable cost is challenging due to the large number of channels and long test times required. This study proposes a new low-cost method for testing the clock jitter of the device using PLL, delay, gate, etc. in the FPGA. Using this circuit, the total jitter analysis function of an expensive, heavy, and slow oscilloscope can be performed simultaneously with tens of CH of clocks within 1us time on a smart phone size board with only tens of dollars of FPGA.

ABSTRACT. Microcontroller (MCU) performance screening ensures devices meet the maximum operating frequency (Fmax) specification. Speed Monitors (SMONs), implemented as ring oscillators, are used to estimate Fmax. Traditional machine learning (ML) models have been explored for this task but require extensive feature engineering and tuning. This work investigates Tabular Foundation Models, specifically TabPFN, for MCU performance prediction. TabPFN leverages in-context learning, enabling accurate inference without dataset-specific training. We evaluate its performance on a composite dataset combining four distinct MCU product families. Results show that TabPFN matches or exceeds baseline ML models while eliminating the need for manual optimization, offering a promising direction for efficient screening in semiconductor manufacturing with minimal human supervision

ABSTRACT. Modern electronic systems such as FPGAs, processors and SoCs are equipped with trusted computing platforms to ensure confidentiality, availability and integrity. Also, to make them more energy efficient, they come with customizable dynamic voltage and frequency scaling (DVFS) mechanism. However, attackers can take advantage of this system and can carry out non-invasive voltage fault injection (VFI) attacks and break confidentiality, availability and integrity. Voltage glitch detectors require a separate response mechanism and latency makes them ineffective. In this article, multiplexer (MUX)-based polymorphic latches, registers and FSMs are designed and implemented in cryptographic benchmarks capable of destroying data under VFI attacks.

ABSTRACT. We present new techniques to efficiently perform static learning on industrial designs. The number of learned ties, equivalences and implications can reach billions, even after pruning “non-worthwhile” relationships. Furthermore, we show that this learning improves coverage and pattern count of automatic Test Pattern Generation (ATPG). To the best of our knowledge, this is the first work to show that static learning can improve ATPG results on industrial designs.

ABSTRACT. This paper presents an experimental comparison of multiplexing techniques for generating high-speed Non-Return-to-Zero (NRZ) test signals ranging from 28 to 64 Gbps using field-programmable gate arrays (FPGAs) and advanced SiGe components. Traditional high-speed signal synthesis methods, such as exclusive-OR (XOR) gates and multiplexers (MUX), are evaluated for their performance in overcoming signal integrity challenges like jitter, edge-rate, and data-eye degradation. The study demonstrates that re-clocking input signals with high-speed flip-flops prior to XOR-based frequency doubling significantly reduces jitter, while re-clocked 2:1 and 4:1 MUXs leverage dual-edge sampling to achieve double and quadruple data-rate extension. The methods are quantitatively compared experimentally.

ABSTRACT. Traditional MBIST algorithms often fail to detect certain functional scenarios, as seen in a unique case where chips had functional test failures during Direct Memory Access (DMA) in burst mode. In burst mode, memory is accessed continuously, causing the address line to change on every clock cycle. MBIST tests passed and Schmoo plots showed no abnormalities, but functional tests still failed. Further analysis revealed that the memory couldn’t handle continuous access, needing an address change every cycle to detect defects. By leveraging Tessent’s advanced capabilities, a custom operation set was developed, ensuring continuous address changes during memory access and enabling detection of these functional failures for future prevention.

ABSTRACT. Ferroelectric FETs (FeFETs) are emerging as promising candidates for non-volatile memory (NVM) and in-memory computing. However, device-level defects, process variations, and charge trapping-induced degradation pose significant challenges to their reliability, particularly in multi-level cell (MLC) FeFET arrays. In this work, we propose a testing framework for FeFET arrays that detects and diagnoses BEOL faults in the presence of parametric variations and SAP faults. Additionally, we introduce a reference threshold-based MBIST methodology to monitor charge trapping-induced degradation.

ABSTRACT. This poster introduces a novel technique to enhance structural test coverage for mixed-signal designs with considerable non-scan elements by manipulating clock and reset signals within scan testing framework.Utilizing a Custom Clock Controller, we strategically stagger scan clocks to improve observability of fault effects in both scan and non-scan logic.A custom reset override mechanism is employed to control reset signals, ensuring deterministic behavior of non-scan logic during scan capture.This dual approach enhances stuck-at coverage, by facilitating precise capture and simulation. Experimental results demonstrate substantial improvements in ATPG coverage.This method offers viable solution to challenges posed by non-scan logic (x-generators) in mixed-signal design scan testing, promising to improve reliability of semiconductor devices.

ABSTRACT. As automotive chips grow in complexity, the cost of functional safety verification rises sharply. This paper proposes a Graph Attention Network based framework that extracts fault propagation features and iteratively identifies critical nodes prone to single-point failures under ISO 26262 guidance. Tested on five open-source circuits, the framework achieves 97.89% accuracy and 98.42% F1-score. Leave-one-out cross-validation yields 97.12% accuracy and 96.86% F1-score, demonstrating strong generalization from small to large-scale circuits. Compared to traditional RTL fault injection and neural network methods, it reduces fault simulation time and training data usage by about half. The framework outperforms existing methods in accuracy and efficiency, enabling scalable automotive safety verification.

ABSTRACT. This paper proposes a new approach to perform diagnosis with all the advanced fault models in a tractable time. Proposed approach allows simpler addition of newer fault models with marginal run time overhead. Experimental results indicate up to 2.97X run time reduction with proposed approach.

ABSTRACT. Compute-in-memory (CIM) AI accelerators using non-volatile memories like RRAM enable energy-efficient edge inference by executing Multiply-Accumulate (MAC) operations directly in memory in a single cycle. These designs modify memory cells and analog-to-digital converters (ADCs), introducing faults not seen in standard memories. We present the first structural testing methodology and framework for RRAM-based CIM MAC circuits, including defect and fault models for memory cells and ADCs. Our robust inference-driven tests exercise full MAC functionality, significantly reducing test time compared to traditional methods, and integrating cell and peripheral testing to ensure high reliability, defect coverage, and operational efficiency.

ABSTRACT. Power Management has become critical to meet SoC Product Performance Goals. The latest High speed interface IO (HSIO) IP designs implement Power Management Units (PMUs) with complex low power saving control. Due to the adoption of multiple power reduction techniques, the power management verification must be more advanced and efficient. Novel Amba Q-Channel reset and power gating interface behavior. Q-Channel interface is part of ARM low power interface spec. PM BFM simulates the behavior of a Q-channel interface, enabling verification of power management features and functionality. It abstracts the low-level details of the Q-channel interface and provides a high-level interface for testbench components.

ABSTRACT. A novel IC monitoring approach is proposed that uses deep learning to identify delayed transients when non-robust tests are applied. A sensor to capture transients during the clock period is proposed, and the collected data are fed into the deep learning model. The deep learning model is trained with data collected with the proposed embedded sensor when manufacturing tests for delay defects are applied. Experimental results with ISCAS’85, ISCAS’89, and ITC’99 benchmark circuits, considering process variations, demonstrate the accuracy and scalability of the proposed method.

ABSTRACT. This work introduces a novel methodology for accessing IEEE 1687 (IJTAG) instruments in System-on-Chip (SoC) designs using an enhanced PDL Solver integrated with AccessLink. It enables independent access to 1687 instruments via ScanMuxes controlled by Scan Registers, eliminating the need for a top-level TAP controller instantiation. AccessLink bridges the external IEEE 1149.1 TAP and the internal 1687 network, supporting both single and multi-TAP configurations. The flow includes ICL extraction, PDL solving, and test setup generation, addressing challenges like pattern generation and instrument isolation. This approach improves modularity and scalability, offering a streamlined, flexible solution for complex SoC validation and test infrastructure design.

ABSTRACT. Scan-based testing is a well-established method in satisfying the high reliability standards of modern automotive devices; however, the increasing complexity of SoC architectures exposes inherent challenges. Traditional Automatic Test Pattern Generation (ATPG) techniques are not always capable of achieving complete fault coverage. In this context, System-Level Test (SLT) is employed to add further coverage in particular on functional states that may not be excited by the scan-based patterns. The proposed approach aims at categorizing not-detected faults from scan-based tests to enable an assessment of SLT routines and show to what extent such programs are actually covering the faults hard to detect by scan-based tests.

ABSTRACT. The "Shift-Left" Design-for-Test (DFT) approach focuses on early testability evaluation at the Register Transfer Level (RTL) to optimize Power-Performance-Area-Testability (PPAT) and accelerate Time-to-Market (TTM). This paper explores how Large Language Models (LLMs) can enhance RTL-based DFT. A multi-LLM collaboration is proposed to autonomously perform Partial Scan Selection (PSS) and Test Point Insertion (TPI). Two data augmentation methods—back-annotating heuristic results and using advanced LLMs guided by DFT knowledge—are introduced. Direct Preference Optimization (DPO) with real feedback from commercial EDA tools further refines the approach. Experimental results show improved testing metrics compared to other methods, including ChatGPT-4.

ABSTRACT. Scan-based Design-for-Testability (DFT) is crucial for achieving high test quality in modern digital circuits, especially with 3D integration and chiplet-based systems. However, it faces challenges in ensuring testability at deep logic levels. Traditional solutions rely on Test Point (TP) insertion, which incurs high design costs. To address this, we propose LITE, an ATPG-aware scan instrumentation technique that leverages functional flip-flops for controllability and observability. Our approach significantly improves testability in terms of pattern count and coverage while incurring lower overhead than TP-based methods, offering a scalable and low-cost alternative for complex designs.

ABSTRACT. The primary purpose of this work is to automate selection of key attributes of a test data compression environment such as Embedded Deterministic Test. Given a test compression setup, the main objective of the proposed approach is to quickly estimate the expected test pattern count, test data volume, and the resultant test application time within the framework of the actual test compression flow when using ATPG-produced test cubes. This way one can mimic a process of test cube merging and anticipate compressibility of the resultant test patterns without resorting to CPU-intensive solvers of linear equations.

ABSTRACT. High-bandwidth IJTAG over SSN allows an efficient test of large-scale logic chips and SOCs. It leverages a high-speed parallel bus to concurrently access many local IEEE-1687 IJTAG networks. Whenever the high-bandwidth IJTAG access mode is activated, it must first be configured through the global IJTAG network. The initial configuration and subsequent reconfigurations constitute a substantial test time overhead. This paper presents wide-ranging enhancements to the high-bandwidth IJTAG access such that it can remain active throughout the entire test session. This results in a significant reduction of test setup time and more efficient test delivery.

ABSTRACT. The IJTAG standard IEEE1687 addressed digital test needs but skipped many practical and physical-world test challenges. P1687.2 worked on an analog extension. The paper shows how quite a few of P1687.2’s concepts can enhance the base standard. It describes new concepts joining digital and analog test properties and behaviour with a consistent description. This spans from seemingly trivial aspects like bidirectionals and relays to co-existence with the full range of analog test. A case study validates how mixed-signal test procedure intent is captured in a new standard language (PDL2) which is retargeted across hierarchy levels, resolving conflicts for test pins and buses.

ABSTRACT. The increasing complexity of integrated circuits demands scalable and efficient design for testability (DFT) solutions to ensure cost-effective test access and functional correctness. Streaming Scan Network (SSN) and High-Bandwidth IJTAG over SSN (HB-IJTAG) enhance test efficiency by accelerating data transfer and optimizing execution. However, these technologies introduce validation challenges due to intricate control mechanisms and their large-scale deployment. This paper presents a holistic approach for generating and sequencing functional validation patterns by systematically leveraging SSN and HB-IJTAG to optimize efficiency. This methodology enables concurrent, robust validation of hundreds of DFT components, significantly improving test execution time.

ABSTRACT. Accurate chip performance prediction is essential in semiconductor manufacturing for energy efficiency and reliability. However, the transition of prediction models from legacy technology nodes to advanced technology nodes often results in poor performance due to process variations, data scarcity, and inconsistencies in feature and target nomenclature. We design a novel transfer learning framework that overcomes these challenges to adapt prediction models trained for a 16nm technology node for minimum operating voltage prediction at a 5nm node while using a small amount of 5nm chip data. A key innovation is the integration of features from silicon odometer sensors exclusive to the 5nm technology, which provides better correlations to the chip performance.

ABSTRACT. Silicon lifecycle management (SLM) is essential for the reliability and quality of silicon products. This work introduces On-Chip Telemetry-based anomaly Notification Engine (OCTANE), a SLM codesign method to monitor chip status using performance counters/sensors. OCTANE features on-chip anomaly scoring through high-speed Fixed Point arithmetic. We utilize a workload-agnostic unsupervised feature ranking and selection technique to provide general compute SLM generalizability. OCTANE demonstrates highly effective on-chip anomaly detection and subsequent diagnosis. OCTANE shows effective anomaly detection with accuracies above 0.96, maintains low area/power (1.2%/2.6%) overhead, and achieves subsequent diagnosis with accuracies surpassing 0.98.

ABSTRACT. This paper introduces IEA-plugin, a novel AI agent-based reasoning module developed as a new front-end for the Intelligent Engineering Assistant (IEA). The primary objective of IEA-plugin is to utilize the advanced reasoning and coding capabilities of Large Language Models (LLMs) to effectively address two critical practical challenges: capturing diverse engineering requirements and improving system scalability. Built on the LangGraph agentic programming platform, IEA-plugin is specifically tailored for industrial deployment and integration with backend test data analytics tools. Compared to the previously developed IEA-Plot (introduced two years ago), IEA-plugin represents a significant advancement, capitalizing on recent breakthroughs in LLMs to deliver capabilities that were previously unattainable.

ABSTRACT. At-speed logic scan tests are an important tool to ensure desired quality in mobile chips. During initial test pattern bring-up, tests that exhibit an unexpectedly high Vmin pose a risk of over-testing and production yield loss. This is particularly problematic if the Vmin of the test is significantly higher than that of the functional system workloads. In such situations, the at-speed logic scan test is debugged to find and resolve the source of the high Vmin. This paper describes an example case study of Vmin debug, in which a series of experiments are performed to identify the root cause as individual test patterns that capture the responses of unconstrained paths. We propose pre-silicon and post-silicon methods to improve Vmin by preventing problematic patterns and reducing the debug effort during test bring-up. Our methods have been verified on ATE to effectively improve Vmin by 28.83 mV to 39.33 mV with 0% to 0.5% pattern count inflation.

ABSTRACT. In advanced semiconductor development at 5nm and below, rapid yield ramp-up and defect identification are vital. Scan-based testing, the primary Design for Testability (DFT) method, faces challenges as scan chains are prone to defects, hindering yield learning. Traditional fault isolation, such as Laser Voltage Probing, is ineffective due to backside power rail constraints. Hardware solutions affect power, performance, and area (PPA), while software lacks precision. This paper introduces two methods: a multi-mode scan design with soft repair capability and a hybrid hardware-software approach. These enhance scan chain diagnosis, supporting faster yield ramp-up and defect identification.

ABSTRACT. High-coverage ATPG scan structural testing is a standard in the automotive industry for effectively screening logic gates with hard defects. Cell-aware testing further optimizes this by injecting defects into standard cell gates. However, latent defects remain difficult to expose, even under extreme test conditions. These defects may go undetected and fail in the field, posing a challenge for chip suppliers to diagnose and improve tests for mature production products. This work introduces a simulation-based approach to enhance latent defect screening by modeling soft resistive defects across voltage, process, and temperature, optimizing cell-aware stimuli to improve defect detection and reduce failure.

ABSTRACT. Streaming Fabric (SF) lowers total test application time (TAT) by simultaneously distributing high-speed test data among multiple cores in a SOC. However, concurrency is limited by the available bandwidth. This paper proposes a protocol aware SF-based solution that identifies redundancies in ATPG test patterns and delivers only meaningful data to cores by interleaving test data. It also proposes a heuristic bandwidth allocation algorithm that distributes bandwidth while accounting for TAT. Experimental results show that the protocol aware solution and the bandwidth allocation algorithm reduces the total test cycles by an average of 43% and 40%, respectively compared to baseline SF.

ABSTRACT. Latch arrays become increasingly popular due to their lower area overhead and power consumption compared to the alternative SRAM. We explore new scan strategies used in latch array design, their implementation flow, and the benefits of these changes to latch array test coverage. Scan solution offers smaller area overhead compared to BIST solution and provides failure analysis capability not available in BIST solution. This innovative approach achieved 100% SAF and TDF coverage for latch array core. Due to the complexity of clock gating and decoding logic in the surrounding logic, different latch array reset schemes are tested and compared.

ABSTRACT. This article considers logic diagnosis using functional sequences for defects that occur during functional operation and may not be detected by scan-based tests. The article suggests the insertion of observation points on next-state variables to collect additional fail data and thus improve the accuracy of logic diagnosis. The target faults are functionally possible transition or stuck-at faults that can cause a chip to fail during functional operation.

ABSTRACT. Traditional structural tests do not provide comprehensive coverage of all possible faults in automotive System-on-Chips (SoCs). To address these gaps, the manufacturing test flow now incorporates System-Level Test (SLT), an additional holistic phase that executes advanced functional programs. This research advances SLT methodologies by introducing a stress-optimization approach. It provides guidelines for developing SLT suites for communication peripherals. It introduces automated SLT workload generation techniques leveraging graph-based SoC to reduce manual effort. Furthermore, grading methodologies are proposed to evaluate SLT using high-level metrics. The methods are validated on a 40nm automotive SoC, manufactured by STMicroelectronics. Experimental results demonstrate that SLT suites can enhance the quality and reliability of SoCs.

ABSTRACT. This research tackles key challenges in testing and repairing chiplet-based (2.5D/3D) multi-die integrated circuits (ICs) as manufacturing advances toward ultra-dense systems with many die-to-die interconnects via micro-bumps, hybrid-bumps, or TSVs. Traditional testing detects only hard defects and includes unrealistic shorts, reducing effectiveness. We propose E2I-TEST, a method that detects all realistic hard and weak short, open, and coupling defects while avoiding aliasing to support diagnosis. It maintains constant test pattern counts regardless of interconnect number. We also introduce a standard repair description language for interoperable interconnect repair, a polynomial-time repair algorithm for UCIe, and micro-bump map optimization to lower defect risks. This work enhances yield, reliability, and defect resilience.

ABSTRACT. The current complex ICs is very challenging with respect to manufacturing and detection of defects. Decompressors and compactors have been adopted to reduce test time but makes diagnosis harder especially for high data compaction techniques like MISRs, used in Logic-BIST. In this thesis, a novel method of comparing the MISR signature intermittently inside the chip has been proposed and explained, along with improvements compared to conventional methods. In addition, a unique, first-of-a-kind compaction method using prime numbers to exactly identify the location of one or two fault capturing flops directly from the signature has been invented. The mechanism and the mathematical proofs along with simulation results have been explained.