ABSTRACT. This paper discusses test techniques used to create an exceptionally reliable processor using an ultra-dense SRAM cell. The test challenges are addressed from the context of stability, in a high-performance processor chip. We will discuss methods to alleviate the read stability fails by enabling the most optimal set of repairs to the highly repairable custom cache arrays without overrunning the total repair capacity of the chip. This paper demonstrates off chip repair calculation strategies to efficiently repair outlier SRAM cells by prioritizing BIST algorithms, test temperature, voltage, and other parameters.

ABSTRACT. The exact characterization of circuits in packaged chips have been essential to design the semiconductor product. However, it is hard to directly measure massive circuits at the desired location in packaged chips. In this paper, we study the method for characterizations of circuits in the chip by implementing a unique operation that is not used in DRAM normal operation. By using our technique, mismatch in millions of sensing amplifier can be extracted in the chip level, and the performance of circuit to cancel mismatch can be also measured, which can be used to develop next-generation sensing amplifier.

ABSTRACT. Compute-in-Memory (CiM) with Non-Volatile Memory (NVM) offers promising performance and power efficiency for data-intensive tasks. NVM properties impact CiM architecture efficiency, requiring rapid design space exploration. We introduce Sisyphus, the first cross-layer framework for architecture research, integrating STT-MRAM, ReRAM, and PCM-based CiM designs into gem5 for performance, power, and resilience evaluation. Sisyphus enables holistic analysis by running workloads on CPU-CiM systems, comparing them to CPU-only baselines. Our experiments show how Sisyphus identifies the best NVM type based on optimization goals.

ABSTRACT. Voltage stress-Iddq signature has supported zero defect efforts, but scaling and test time constraints have caused latent Gate Oxide (GOx) shorts. This paper proposes three methods to optimize signature detection in digital IC testing: 1) Critical Thickness Model (CTM), identifying the minimum stress time for MOSFETs with GOx < 3nm, reducing test costs and yield loss. 2) Stress Coverage Quantification Algorithm (SCQA), evaluating actual stress coverage. 3) Coverage Maximization Algorithm (CMA), reducing voltage stress test escapes. CTM reported minimum stress time 10e-3 lower than current practice, SCQA reported a 6.2% coverage difference at the transistor level compared to ATPG, and CMA reduced voltage stress test escapes by 10%, improving quality.

ABSTRACT. Traditional timing-prediction methods that assume constant temperature for automotive electronics can lead to errors of up to 17% compared to models that incorporate temperature distribution over 30 years of aging, resulting in inaccurate reliability assessments. To address this limitation, this paper introduces a highly-reliable timing-prediction framework that integrates functional behaviors, aging effects, and temperature distributions for accurate analysis. By leveraging two-phase machine-learning approach for cell-delay prediction and eliminating false paths at design level, our solution achieves maximum critical path timing error of only 2.22% compared to SPICE simulations. Additionally, it significantly improves computational efficiency, achieving speed-ups of up to 203.97×.

ABSTRACT. Scan VLV testing is an established industry practice to screen latent defects. To be effective these tests must be run near intrinsic voltages of silicon. We discuss the experiments that helped productize this in single digit FinFET technology.

ABSTRACT. A key requirement for SLM is to detect and isolate functional failures that escape structural tests. Embedded trace can collect time stamped data to analyze the trajectory of the software transactions involving the CPU, memory, I/Os, peripherals, and other sub-systems, is a key component of any silicon analytic system. This presentation will use an industrial case study of an embedded trace system developed based on the Efficient Trace for RISV-V (E-Trace) specification to highlight the central position it occupies in building a comprehensive silicon debug and continuous monitoring solution. Results on some industrial benchmarks demonstrate the efficiency of this approach.

ABSTRACT. The growing complexity in manufacturing and operating the hardware in AI clusters leads to significant challenges in reliability. To tackle this issue, we present CP-Bench, an open-source, Configurable and Parameterizable, PyTorch-level test suite designed to test AI hardware failure, performance degradation, and silent data corruption (SDC). Built upon open source projects, CP-Bench contains 30+ AI workloads (e.g., Llama). We have deployed CP-Bench for use cases throughout Meta’s hardware lifecycle, from manufacturing to in-production diagnostics, based on which we detect/reproduce various hardware issues such as SDC. Notably, some of these issues were not caught by vendor’s tooling.

ABSTRACT. In-Field Test has for long relied on using Built-in self-test (BIST). This involves power-on, power-off and testing during device operation. Hyperscalar datacenters that often-run large-scale AI/ML applications need to run periodic testing of device in-field. This is necessary to prevent interruptions caused by Silent Data Corruption (SDC). For this, targeted portions of the device must be accessible for testing, while rest of the device is running in functional mode. This poster explores method to test the device In-field using In-System Embedded Deterministic Test (IS-EDT) patterns delivered through Streaming Scan Network (SSN). The In-System Test Controller (ISTC) runs IS-EDT patterns and can also use an IJTAG network to run BIST capabilities.

ABSTRACT. Modern RISC-V designs integrate cryptographic accelerators to boost performance, yet their power side-channel vulnerabilities remain underexplored. This work presents a pre-silicon evaluation methodology using simulated power traces, employing KL divergence, Correlation Power Analysis (CPA), and Differential Power Analysis (DPA) at the RTL level. Demonstrated on a CVA6-based AES accelerator integrated via the Core-V-Extension Interface (CV-X-IF), the method reveals leakage trends consistent with FPGA-based power measurements. While hardware AES shows improved resilience over software, key extraction remains feasible, underscoring the need for early-stage analysis. The approach offers a generalizable framework for assessing side-channel leakage in RISC-V cryptographic accelerators.

ABSTRACT. Modern semiconductor design heavily relies on the integration of IPs from 3PIP vendors to improve design efficiency. However, such collaboration introduces security concerns as adversaries can insert hardware Trojans as outsourced IP vendors. Typically, confidentiality verification is applied for hardware Trojan detection, as Trojans function by leaking sensitive information. In this paper we present QuEST, a confidentiality verification framework that identifies data leakage by analyzing statistical dependencies between inputs and outputs. Moreover, QuEST applies Shannon entropy-based metrics to quantify the extent of data leakage. The proposed framework successfully detects date leakage caused by hardware Trojans in 11 Trust-hub benchmarks.

ABSTRACT. In this paper, we present new PRPG gating concepts that can help control the input scan switching activity but still allow scan chains to get pseudo-random 0/1’s during the scan load operations. This allows for a predictable Low Power pseudo random scan input data to help achieve fault mark off without the need to shut off scan chains or custom PRPG logic.

ABSTRACT. Pseudo-Boolean Satisfiability (PBSAT) can be used to perform automated power side-channel analysis, i.e. recover secret keys from the power consumption information of a generic Boolean circuit. These PBSAT procedures however have higher complexity due to the NP-hard nature of PBSAT solving, and can be more sensitive to noise. In this paper we propose a formal circuit slicing procedure to improve runtime, and procedures based on pseudo-Boolean optimization (PBOPT) to improve error tolerance. We show orders of magnitude improvement in runtime via the slicing routine, and improvements in key accuracy in the face of error that would cripple the original PBSAT routines on a set of generic benchmark circuits.

ABSTRACT. In this paper we introduce a passive physical anti-tampering Physical Unclonable Function (PUF) based on glitters that can protect the entire IC and/or PCB. As a case study, a prototype of the proposed glitter based PUF has been developed using a Raspberry Pi (RPi) camera, a resin coating layer containing glitters and a 3D printed case. Using actual drill measurements, our findings indicate that even drilling with a 0.1mm diameter drill can be detected and lead to a wrong key.

ABSTRACT. Hardware description language (HDL) netlists extracted from reverse-engineered integrated circuits (ICs) are described at the transistor level, thereby obscuring any internal sequential circuitry. Existing methods to extract sequential behavior from transistor-level netlists rely upon prior knowledge of the design, such as the location of memory state cells or the number of state-holding nets, which may not be available. Toward identifying state-holding elements in an extracted netlist without help from any such information, we propose a new methodology which combines graph searching with satisfiability modulo theories (SMT) solving to detect and locate state-holding nets.

ABSTRACT. Hardware description language (HDL) netlists extracted from reverse-engineered integrated circuits (ICs) are described at the transistor level, thereby obscuring any internal sequential circuitry. Existing methods to extract sequential behavior from transistor-level netlists rely upon prior knowledge of the design, which may not be available. Toward identifying state-holding elements in an extracted netlist without help from any such information, we propose a new methodology which combines graph searching with satisfiability modulo theories (SMT) solving to detect and locate state-holding nets.

ABSTRACT. The growing complexity in manufacturing and operating the hardware in AI clusters leads to significant challenges in reliability. To tackle this issue, we present CP-Bench, an open-source, Configurable and Parameterizable, PyTorch-level test suite designed to test AI hardware failure, performance degradation, and silent data corruption (SDC). Built upon open source projects, CP-Bench contains 30+ AI workloads (e.g., Llama). We have deployed CP-Bench for use cases throughout Meta’s hardware lifecycle, from manufacturing to in-production diagnostics, based on which we detect/reproduce various hardware issues such as SDC. Notably, some of these issues were not caught by vendor’s tooling.

ABSTRACT. A key requirement for silicon debug and continuous moni-toring is to detect and isolate functional failures that es-cape structural tests. This paper will use the case study of an embedded trace system developed based on the Efficient Trace for RISV-V (E-Trace) specification to highlight the cen-tral position it occupies in building a comprehensive SLM solution. Results on some industrial benchmarks demonstrate the efficiency of this approach.

ABSTRACT. When the occurrence of defects is detected during functional operation, the defects can be detected and diagnosed using functional sequences. This article suggests the insertion of observation points on next-state variables to improve the effectiveness of functional sequences for logic diagnosis. The article describes an efficient diagnostic fault simulation procedure for functional sequences, and a procedure for the insertion of observation points. Experimental results for benchmark circuits in an academic simulation environment demonstrate the potential of observation points on next-state variables to improve logic diagnosis.

ABSTRACT. In this paper we introduce a passive physical anti-tampering Physical Unclonable Function (PUF) based on glitters that can protect the entire IC and/or PCB. As a case study, a prototype of the proposed glitter based PUF has been developed using a Raspberry Pi (RPi) camera, a resin coating layer containing glitters and a 3D printed case. Using actual drill measurements, our findings indicate that even drilling with a 0.1mm diameter drill can be detected and lead to a wrong key.

ABSTRACT. Latch arrays become increasingly popular due to their lower area overhead and power consumption compared to the alternative SRAM. We explore new scan strategies used in latch array design, their implementation flow, and the benefits of these changes to latch array test coverage. Scan solution offers smaller area overhead compared to BIST solution and provides failure analysis capability not available in BIST solution. This innovative approach achieved 100% SAF and TDF coverage for latch array core. Due to the complexity of clock gating and decoding logic in the surrounding logic, different latch array reset schemes are tested and compared.

ABSTRACT. Pseudo-Boolean Satisfiability (PBSAT) can be used to perform automated power side-channel analysis, i.e., recover secret keys from the power consumption information of a generic Boolean circuit. These PBSAT procedures, however, have higher complexity due to the NP-hard nature of PBSAT solving, and can be more sensitive to noise. In this paper, we propose a formal circuit slicing procedure to improve runtime and procedures based on pseudo-Boolean optimization (PBOPT) to improve error tolerance. We show orders of magnitude improvement in runtime via the slicing routine, and improvements in key accuracy in the face of error that would cripple the original PBSAT routines on a set of generic benchmark circuits.

ABSTRACT. The analysis of wafer map patterns is crucial for detecting manufacturing defects in integrated circuits. Although deep neural networks have been used for this task, spiking neural networks (SNNs) offer a more energy-efficient alternative by using spike activations, replacing multiplications with simpler additions. We develop an SNN with ternary spike activations, enhancing information capacity and learning. Using direct spike training with pseudogradients, our model outperforms both binary SNNs and DNNs on the WM-811k wafer benchmark dataset, excelling in identifying critical defect patterns that are underrepresented in the dataset with high accuracy and computational efficiency.

ABSTRACT. Streaming Fabric (SF) lowers the total test application time by enabling the concurrent distribution of high-speed test data to multiple cores in a SOC. Typically, scan or scan-like data must be delivered unmodified. This paper proposes a protocol aware SF-based solution that takes advantage of identified redundancies in SEQ ATPG test patterns to deliver only meaningful data to cores. The bandwidth occupied by redundant data is freed up and used to deliver meaningful data to another core. Experimental results show that the protocol aware solution reduces total test cycles by an average of 43% compared to baseline SF.

ABSTRACT. Automated Test Equipment (ATE) systems widely employ four-wire (Kelvin) measurement techniques to ensure accurate power delivery to the Device Under Test (DUT). When a single power source supplies multiple DUTs, the sensing point is typically placed at the geometric center of the DUT array on the Device Interface Board (DIB). However, in cases of non-uniform current distribution among DUTs, this approach may not yield optimal results. This paper presents an optimized sensing point placement strategy, which is validated through simulations to significantly reduce voltage deviation relative to the target voltage in high-multi-site testing with non-uniform current distributions.

ABSTRACT. Machine Learning (ML) techniques have recently been applied to automate the wafer map pattern recognition problem. However, as manually annotating wafer map data is expensive and time-consuming, most of the research work leverage on public available dataset such as WM-811K with known probe technology agnostic labels. Probe technology specific wafer map patterns, especially multisite probe touchdown related patterns, have not been considered, as they are affected by specific wafer test methodology and require customized labeled data which are not readily available. In this paper, we propose a synthetic data augmented training method to enable automated wafer map recognition for multisite probe specific patterns.

ABSTRACT. We present a pilot study exploring whether Large Language Models (LLMs) can generate test vectors for stuck-at faults in gate-level combinational circuits. We hypothesize that a “language of test” exists, capturing how input stimuli expose differences between fault-free and faulty netlist functionality. To test this hypothesis, we generated 958K test vectors across 40K random combinational circuits, using fault-simulation results to fine-tune a 7-billion-parameter Llama-2 model via Low-Rank Adaptation (LoRA), supervised fine-tuning (SFT) and Group Relative Policy Optimization (GRPO) to mitigate hallucinations. On unseen netlists, the model generated test vectors for target faults with over 70% success—far exceeding random generation.

ABSTRACT. As designs grow in size and complexity, the DFT (Design For Test) and ATPG (Automatic Test Pattern Generation) capabilities have to adapt for functional data paths being tuned for high speeds, which is leading to growing trend in having non-scan flops and pipelining in the design. In this poster, we propose couple key technologies customers can enable to minimize scan logic but keep ATPG quality.

ABSTRACT. Silent Data Corruption (SDC) is caused by undetected errors that yield incorrect results without triggering system alerts or error logs. Existing test methodologies are inadequate for capturing dynamic voltage fluctuations occurring under realistic workload conditions, limiting their effectiveness for detecting SDCs. To address these limitations, we introduce Telemetry-Informed Delay Testing (TIDE), a novel methodology that enhances SDC detection by leveraging telemetry sensors to monitor voltage fluctuations and their impact on timing integrity. By incorporating dynamic, workload-aware test generation, the proposed framework overcomes key limitations of traditional approaches and facilitates early detection of SDCs. The effectiveness of TIDE is demonstrated through case studies conducted on two RISC-V-based SoCs and multiple workloads.

ABSTRACT. Digital-to-analog converters (DACs) in modern SoCs require high accuracy. Although testing for nonlinearity error properties is well-studied, their statistical nature is less explored. This paper examines the differential and integral nonlinearity (DNL and INL) of unary and binary-weighted DACs, revealing that code-dependent DNL and INL are roughly Gaussian distributed. Furthermore, the extrema of DNL and INL follow the Generalized Extreme Value Distribution. MATLAB simulations results demonstrate strong agreement between analytical predictions and observed DNL/INL.

ABSTRACT. Selecting the appropriate correct minimum supply voltage (Vmin) at product test is crucial for chip reliability, yield, power, and performance, but process variations make it challenging to determine. The typical method relies on a manual, labor-intensive lookup table based on DRO values. To improve accuracy and efficiency, we propose machine learning models for two predictions: (1) optimal Vmin per die using Support Vector Regression (SVR) with correlated coefficients, and (2) in-field Vmin shift due to aging via linear regression. By leveraging key inputs, these models offer opportunity to optimize test guard bands, enhance accuracy, minimize manual correlation, accelerate silicon time-to-market, and extend chip lifetime.

ABSTRACT. This paper proposes a method for sharing on-chip instruments in an IEEE Std. 1687 (IJTAG) network, between different external users, in a secure and efficient manner. Instruments are made accessible for authorized users while remaining hidden to others. The users are also protected against attacks from hardware trojans, in hidden third party instruments. The solution is demonstrated with a use case on a benchmark IJTAG network.

ABSTRACT. The increasing complexity of SoCs and very high test coverage demands escalate structural test costs on expensive ATE resources. This paper introduces an approach enabling deterministic structural tests on cost-effective System Level Test (SLT) platforms via existing High-Speed I/O (HSIO) access mechanisms. We demonstrate integrating Synopsys's High Speed Access Test (HSAT) IP, which bridges SoC HSIO (e.g., USB) and Design-for-Test infrastructure for efficient pattern transfer. This HSAT IP-based scheme significantly cuts test costs by shifting tests to SLT, enabling high concurrency, optimizing ATE utilization, and providing robust diagnostics for rapid root cause analysis and improved DPPM. Future work extends this framework to in-system test for Silicon Lifecycle Management.

ABSTRACT. Silent data corruption is a big challenge for large-scale data centers that lead to chip malfunctions. This problem is often caused by small delay defects. Timing-aware ATPG (TA-ATPG) is a heuristic that detects small delay defects (SDD) by using the minimum slack path for fault propagation. This poster will show a precise approach to TA-ATPG. The proposed method generates high-quality test patterns for SDD detection and effectively handles timing exception paths.

ABSTRACT. Most existing methods overlook runtime-determined characteristics during the selection of stimuli. We propose a novel approach, Simulation Traits Assisted Random Test Selection (STARTS). Initially, the test case is executed on the model to predict the behavior of the multiprocessor. Subsequently, a GRU-based variational autoencoder augmented with a self-attention layer is utilized to embed the stimulus into a latent representation. The distance within this latent space is then adopted as a critical factor for selection. The proposed method integrates both hardware-related information and inherent multiprocessor stimuli characteristics. Experimental results indicate that the model significantly reduces the time required to achieve coverage goals by leveraging multiple traits in an efficient manner.

ABSTRACT. As chiplet-based multi-die systems become standard in advanced semiconductor packaging, efficient Design-for-Test (DFT) strategies are critical. This work presents a scalable scan test solution that leverages existing die-to-die (D2D) functional interfaces to share scan bandwidth across dies in a Multi-Chip Module (MCM), significantly reducing test cost and time.

ABSTRACT. This poster explores how Origen can be used to generate tests from a single source for both ATE and validation lab test fixtures, promoting collaboration across different teams.

ABSTRACT. Spiking Neural Networks (SNNs) implemented with Resistive RAM (ReRAM) offer promising advantages in area and power efficiency. However, process-induced resistance variability poses a significant challenge to inference accuracy. To address this issue, we propose a test and calibration framework to maintain target model accuracy. The test flow employs systematic pattern generation and formulates a set of linear equations to estimate ReRAM cell resistances. Given the estimated resistance, rows exhibiting large deviations are replaced using redundant rows to mitigate computational errors. Experimental results on Tiny ImageNet with a Transformer-based SNN demonstrate that the proposed calibration method improves inference accuracy by 2.3% and 4.2% with one and two redundant rows, respectively.

ABSTRACT. Yield entitlement for products with different die areas is well understood in relation to defect density. However, it is not as straightforward to determine the expected loss for each failure mechanism that limits yield. This can hinder the attainment of yield entitlement and increase the cost of a die overtime. This paper provides a method to quickly identify products with higher than anticipated failure rates for all failure modes using die area and large language models on wafer sort bin definitions. Both simulated cases and actual production data are used to show how outlier products can be easily identified.

ABSTRACT. PCI Express (PCIe) is a high-speed interconnect technology that plays crucial role in modern computing systems, connecting key components such as storage devices, network interfaces, accelerators, and GPUs. Ensuring robust interoperability is essential to maintaining device compatibility, link stability, and overall system reliability across different configurations and environments. Rigorous PCIe LTSSM testing helps identify and mitigate link training intermittent failures, signal integrity issues, and protocol mismatches early in development, reducing system downtime, preventing performance degradation, and enhancing user experience. This paper presents a case study on PCIe LTSSM testing in data center class platforms, highlighting real-world test methodologies and issues uncovered in systems.

ABSTRACT. Passive-memristor-crossbars offer promising solution for AI-hardware accelerators by enabling parallel matrix-vector-multiplication, where column current is primary-observable. So, column-level fault detection is sufficient to meet manufacturing test requirements for inference-workloads. However, the absence of selector devices makes existing testing methods inapplicable, as they need cell-level access. This work presents two-phase-testing methodology for passive crossbars. Phase 1 performs chip-level screening to identify faulty columns, Phase 2 estimates the number of faults per column, reducing test-time by 70% compared to March tests. For 64×64 passive crossbar, proposed method achieves ∼98% coverage in detecting faulty-columns and ∼97.5% accuracy in fault-estimation, providing sufficient resolution for manufacturing screening and system-level fault tolerance strategies for AI workloads.

ABSTRACT. System Level Test (SLT) of compute products, such as processors, graphic cards, or AI accelerators, can stress critical components on the platform to their rated maximum performance and thermal envelopes. This at-speed test requires thermal management solutions compatible with the dense SLT environment, deployable at scale. Here we introduce the challenges of thermal management in SLT, parameters that affect thermal envelopes, using a case study of DDR memory. We present typical thermal management solutions used in a high-volume system test, their advantages and shortcomings, introduce liquid cooled solutions that can overcome them, and the functional benefits of using advanced liquid cooled DIMM solutions at scale in test factories.

ABSTRACT. Timing-related fault detection is essential for VLSI circuit reliability. At-speed testing detects delay variation problems that result in partially conducting transistors, resistive bridges, and other defects. This poster shows a hybrid launch-off-shift and capture technique in one ATPG run by adding a small control logic. The experimental data show significantly improved result compared to other existing methods.

ABSTRACT. A novel IC Monitoring technique is proposed that uses deep learning to identify delayed hazards when non-robust tests are applied. Which uses an embedded sensor to capture transients during the clock period, and the collected data are fed into the deep learning model. Process variations are taken into consideration. The deep learning model is trained with data collected with the proposed embedded sensor when manufacturing tests for delay defects were applied. Experimental results with ISCAS85, ISCAS89, and ITC99 benchmark circuits demonstrate the accuracy and scalability of the proposed method.

ABSTRACT. Abstract—SLT has been a mainstay at Intel for several generations of products across all segments. In this poster, we discuss the need for SLT by detailing the challenges driven by marginal faults, provide an insight into the building blocks of our architecture, briefly discuss several tester configurations, highlight its significance with data from Intel products, and finally layout future opportunities and potential directions being explored.

ABSTRACT. This paper offers a comprehensive overview of the IEEE P1450.6.2-2014 standard update, highlighting key advancements and improvements introduced in the revision. The syntax and semantics of the 2014 version have been refined to address various limitations encountered by users in previous versions, as well as to accommodate new and emerging memory types. These updates aim to enhance the standard's flexibility and usability, ensuring better alignment with evolving industry needs. The paper delves into the modifications to different components within the structure of the memory test model. It explores how these changes improve the representation and handling of memory attributes, which are essential for effective testing and repair processes.

ABSTRACT. System-on-Wafer (SoW) technology integrates multiple chiplets on a single wafer substrate, delivering enhanced performance for high-computation applications. This paper introduces an innovative 3D test access architecture for complex SoW systems. Our proposed omnidirectional test access architecture, compliant with IEEE Std. 1838, provides a scalable, plug-n-play testing solution for comprehensive multi-directional testing. It enables efficient scan path configuration, optimizing test scheduling while minimizing power consumption and timing impacts. A case study of a SoW system with four chiplets connected in a 2x2 configuration validates the architecture feasibility and effectiveness, demonstrating its potential to improve SoW testability and reliability.

ABSTRACT. Chips with multiple interconnected dies offer significant advantages over those with a single monolithic die, driving the rapid adoption of multi-die packages in the market. Die-to-die interconnects are typically realized as large, dense arrays of fine-pitch micro-bumps or hybrid bonds, prone to manufacturing defects like shorts and opens. Typically spare interconnects are included to "repair" defective ones. This paper introduces an Interconnect Repair Language (IRL), based on Google's Protocol Buffers, to describe all repair provisions. We demonstrate IRL with an example for UCIe-Advanced 2.0 and present cost/benefit metrics for repair solutions alongside potential EDA tools based on the proposed IRL.

ABSTRACT. Fan-out wafer-level packaging enables high-performance chiplet integration but faces manufacturing challenges such as warpage, die shift, and delamination, leading to various defects in Cu pillar, redistribution layers and solder balls. To address this, we propose a defect analysis and testing framework that maps defects to equivalent faulty circuits for precise fault characterization. A built-in self-test architecture with an embedded ring oscillator detects weak opens, bridging, and coupling faults while quantifying the size of these defects. Our framework mitigates fault aliasing across voltage corners and transistor sizes, enhancing diagnostics, yield learning, and silicon lifecycle management. HSPICE simulations are performed to validate the effectiveness of this framework in 7 nm CMOS technology.

ABSTRACT. Small defects and excessive process variability can cause circuit delay changes and result in subtle failures. Such failures, if undetected, can escape to the field resulting in Silent Data Errors (SDE). To expose such failures, we discuss five fault models and the associated scan tests. Of these five, we introduce two new fault models. Silicon results on the E-core of a recent cloud server microprocessor product are described and the relative merits of such tests are determined. 

ABSTRACT. Delay characterization of standard cells under resistive open defects is of increasing concern due to aggressive timing margins in digital circuits.  The problem is made worse by the large number of open defect sites in standard cells combined with a wide range of defect resistance values for each site.  To alleviate the resultant simulation complexity, we propose the concept of resistive fault dominance (RFD) for resistive open defects. RFD eliminates simulations of certain open defects with intermediate defect resistance values that are guaranteed to exceed specified timing margins for standard cells based on tests for specific “dominant” resistive open defects. An algorithmic delay characterization methodology is developed.

ABSTRACT. As semiconductor technology advances, small delay defects have become a major concern in System-on-Chip testing due to shrinking timing margins.This paper presents an SDD diagnosis method integrating timing-aware fault simulation with injected delay selection and a mismatch-weighted score method to enhance diagnostic accuracy. Rather than relying on fixed delay values, the proposed method determines injected delays based on the slack of transition paths, generating multiple delay sizes to improve fault simulation resolution. The mismatch-weighted score calculation adjusts contributions of failures, enhancing defect ranking and mitigating process variation effects. Experimental results demonstrate that the proposed method significantly improves SDD localization and reduces fault candidates, outperforming conventional approaches in accuracy and efficiency.

ABSTRACT. The rise of datacenters that employ large volumes of advanced chips has enabled the realization and quantification of negative impacts from manufacturing test escapes, including field failures and silent data corruptions. More comprehensive fault models have been proposed to close exposed gaps in test quality, but have shown significant increases in fault lists over traditional fault models. In this work, we propose an enhanced test metric that targets physical regions by flattening cell-internal physical structures within the full circuit layout, then developing an optimized fault set to exhaustively test each region's signals.

ABSTRACT. As semiconductor manufacturing processes continue to shrink, the impact of small-delay defects becomes increasingly significant. Traditional Automatic Test Pattern Generation (ATPG) methods often fail to detect these defects, as they are masked by critical paths. This work proposes a Timing-Partitioned Small-Delay-Defect (TPSDD) methodology to address this issue. By analyzing timing path delays and grouping transition paths based on their delay sizes, ATPG patterns can be generated to specifically test these groups, revealing hidden small-delay defects. Additionally, techniques for identifying outlier dies and defect candidates are presented, validated through testing on the N2 process node. Our silicon results confirm the effectiveness of TPSDD in detecting small-delay defects.

ABSTRACT. Diagnosis simulation based on stuck-at faults cannot expose all diagnosis problems because silicon defects don’t behave as stuck-at faults. The failure-activation conditions of silicon defects are generally more complicated and act as conditionally-activated stuck-at-faults. Distinguishing bits exist on one fault but not on another fault. These bits are used in this paper to distinguish a conditionally-activated fault from others. Diagnosis coverage can be calculated using the number of distinguishing bits to estimate silicon diagnosis resolution before volume production. Diagnosis test patterns and diagnosis points can be added to increase distinguishing bits to improve diagnosis coverage for silicon defects.