ITC 2025: IEEE INTERNATIONAL TEST CONFERENCE
TALK KEYWORD INDEX

This page contains an index consisting of author-provided keywords.

2
2.5D
5
5G Testing Enigneering
A
ABIST
ACCESSLINK
Accuracy
ADC
advance processes
advanced packaging
aging
AI Agent
AI Hardware
AI Hardware Accelerator
analog test generation
Anomaly Detection
Anomaly Diagnosis
Anti-Tamper
Anti-Tampering
arbitrary waveform generator
architecturally correct execution
Assertion-Based Verification
At-speed testing
ATE
ATPG
ATPG Techniques
auto generated PDL
auto-range
Automated Test Equipment
Automated Test Equipment (ATE)
Automated Test Pattern Generation (ATPG)
Automatic Test Equipment (ATE)
Automatic test pattern generation (ATPG)
automation
automotive
automotive electronics
B
Battery Management System
Battery Management Systems
Benchmark
BEOL Defects
BIST
Bit line sense amplifier
Bit-Flip Attack (BFA)
BTI
Bug Detection
Built-In Redundancy Analysis
Built-In Self-Repair
Built-In Self-Test
built-in self-test (BIST)
Bus Functional Model(BFM)
C
Calibration
cascaded PLLs
cell aware
cell-aware
cell-aware ATPG
cell-aware test
Central Processing Unit
chain diagnosis
characterization
chip aging
Chiplet interconnects
Chiplet-based system
Chiplets
CIM
circuit reliability
CLASS
Clock
clock tree defect
CMOS
CNN
Colored Petri Nets
common-input learning
Compression
Computation-in-memory
Compute-in-Memory
conditionally-activated fault
Confidentiality
Configuration
consistency verification
Contactless flange rectangular waveguide
Continuous Monitoring
Controllability
Core
Core characteristic
Core-V eXtension Interface (CV-X-IF)
Coverage closure
CP Testing
critical circuit nodes
Critical faults
Critical Thickness Model
Cryptographic Accelerator
current range
Custom clock controller
Custom MBIST Algorithm
Custom operation set
Custom reset controller
CVA6
CWE
D
D2D
DAC
Data Center Systems
data converters
Debugging
Deep Learning
Deep Neural Network
Defect activation
Defect characterization
Defect diagnosis
defect modeling
defect-finding
defect-oriented stress
Defect-oriented test
defects
Delay fault testing
Delay Test
Delay test coverage
Delay Testing
delay-line array
Deobfuscation
Dependability
design for diagnosis
Design for Test
Design for Test (DFT)
Design Space Exploration
Design-for-Test
Design-for-Testability (DFT)
Device Interface Board (DIB)
Device Testing
Device Under Test
device-aware test
DFM and Test Diagnosis
DFT
diagnosability
Diagnose Program
Diagnosis
diagnosis control points
diagnosis coverage
diagnosis observe points
diagnosis simulation
diagnostic fault simulation
Diagnostics
Differential non-linearity (DNL)
digital tester
DIMM
Direct Memory Access
distinguishing bit
dithering
DNL
DPM
DPPM
DRAM
Drift
Dynamic Voltage and Frequency Scaling (DVFS)
Dynamic voltage and frequency scaling (DVFS) Polymorphic latch
E
ease of debuggability
Electric Vehicles
Elmore Delay
Embedded deterministic test
Embedded test
Entitlement
equivalence learning
Error Injection
Extrinsic Variations
eye diagram
F
failure analysis
False path
Fan-out wafer-level packaging
fault collapsing
fault coverage
fault diagnosis
fault dominance
fault equivalence
Fault Injection
Fault Injection Attack
Fault Injection Attack (FIA)
fault list optimization
fault mode
Fault Modeling
fault models
Fault Propagation
fault simulation
Fault Tolerance
Fault-Aware Training
Fault-tolerance
FeFET
FeFETs
femtosecond
Ferroelectric FETs (FeFETs)
flip-flop
Fmax
Four-wire (Kelvin) Measurement
FPGA
FT Testing
functional fault simulations
functional launch-on-capture (FLOC) tests
Functional Safety
functional sequences
functional switching activity
functional testing
functionally possible faults
G
Gaussian noise generation
Generalized extreme value distribution
Generative AI
Generic Circuit Learning
Glitter PUF
global control signal diagnosis
Graph Attention Network
Ground bounce
Guard Bands
H
Hardware Accelerator
hardware cost
Hardware Security
Hardware Telemetry
hardware testing
hardware timers
Hardware Trojan
HB-IJTAG
HBM
HCI
Hierarchical
Hierarchical Design for test (DFT)
Hierarchical Test
High Speed Access Test (HSAT)
High-Speed IO
Hot Carier induced
HSIO
HVM
Hw/SW co-design
Hybrid launch-off-shift and capture
Hypergraph Theoretic Weighting
I
IC Monitoring
ICL
IDD
IEEE 1500
IEEE 1687
IEEE 1687 (IJTAG)
IEEE 1838
IEEE Std. 1687
IJTAG
Impedance Match
implication learning
In Memory Computation
In-Field Testing
In-System Test
INL
Integral
Integral non-linearity (INL)
inter-cell bridge
Interactive Test
interconnect
Interconnect ATPG
Interconnect Repair Language
Interconnect Test and Repair
J
Jitter
jitter injection
JTAG
K
k-Way Partitioning
L
LA-DOS
LangGraph
language
Large Language Model
Large Language Models
latch array
Latent defects
Latent gate oxide shorts
Launch-off-capture
Launch-off-shift
layout-aware
LBIST
LDO
Linear Regression
Liquid Cooling
LLM
LLMs
Load Board
Load Board (L/B)
logic diagnosis
Low Power
low-cost
LTSSM
M
Machine Learning
Manufacturing
manufacturing test
Manufacturing Test Setup
March Testing
Marginal Defects
MBIST
MCM
Measurement Variation
Memory
Memory Arrays
Memory Controller
Memory Repair
Memory test
Memory-BIST
Memristor
Memristors
Microwave
Millimeter-wave
Mismatch
MISR
Mixed-Signal
ML in Testing
Model
Model Robustness
Monte Carlo
Monte Carlo Sampling
multi-chiplet designs
Multi-cycle path
multi-GHz testing
multi-gigahertz
multiplexer
Multiply-and-accumulate
Multiprocessor verification
multisite probe
N
Neural Networks
Neuromorphic computing
non-linearity (INL)
Non-Robust Tests
Non-scan Testing
Non-Volatile Memory
NVM
O
Observability
observation points
Offset cancelation
On-chip
On-chip authentication
Open defects
Optics
optimization
Origen
Outlier Detection
overclock
P
P1687.2
Parametric Measurement Unit
Passive Memristor Crossbar
Passive PUF
path delay faults
pattern retargeting
PCIe Interoperability
PDL
PDL2
Performance
Phantom
phase locked loops
Physical Failure Analysis
Physical Unclonable Function
physically unclonable function
picosecond
PICS
Platform Level Test
PLL
Polarization Defects
polymorphic FSM
Polymorphic Latch
Polymorphic Register
Post-Silicon Validation
Power management(PM)
Power Side-channel Attack
Power-Aware
PPM
Pre-Silicon/Post-Silicon
Probabilistic Estimation
Probe Card
Probe Card (P/C)
Process Capability
Process Variation
Processor Trace
Pseudo-Boolean Satisfiability
PSS
push-on mating mm-wave interface
PyTorch Models
Q
Q-channel
Quantitative vulnerability
R
Random failures
Randomization
reconfigurable scan network
Redundancy
Refresh
Register Transfer Level
Regression
Reliability
reliability analysis
Reliability Estimation
ReLU
Relxpert
Repair
Repair prioritization
ReRAM Test
Resistance Variation
Resistive fault dominance
Resistive RAM
Resolution
Reverse Engineering
RF Network
Ring Oscillator
Ring Oscillators
RISC-V
RISC-V E-Trace
RMS
RRAM
RRAMs
RTL
RTL-Level PSC Analysis
S
S-parameter
SAT
Satisfiability Modulo Theories
scan
Scan Architecture
scan chain diagnosis
scan diagnosis
Scan Instrumentation
scan shift
Scan Switching
Scan Test
Scan-based test
selective hardening
Semiconductor
Semiconductor Performance Modeling
Sensing Point Placement
Sensor
sequential ATPG
serializer
Server
Shift-Left
SIB
SiGe
Signatures
Silent Data Corruption
Silent Data Corruption in AI devices
Silent data error
Silent Data Errors
Silicon Debug
Silicon Lifecycle Management
Silicon Odometer Sensing
Silicon Photonic
Silicon Photonics
silicon practice
Simulated Annealing
simulation time
Simulation Trait
SLT
small delay
small delay defect
small-delay defects
small-delay-defect
SoC Security
SOC Test
software-based self-tests
software-hardware co-design
SORT
Speed Binning
Speed Monitors
speed-up
Spiking Neural Network
Spiking neural networks
spread-spectrum clock generator PLL
SSN
Stability
staggered Clocking
State Element Identification
Static Random-Access Memory (SRAM)
stochastic delay measurement
Streaming Fabric
Streaming Scan Network
Stress coverage
Stress time
Structural test
Structural Testing
stuck-at fault (SAF)
stuck-at faults
Support Vector Regression (SVR)
synthetic data
System Level Test
System Level Test (SLT)
System Test
System Validation
System-Level test
system-level-test
System-on-Chip (SOC)
system-on-wafer
SystemVerilog Assertion (SVA)
T
Tabular Foundation Models
TAP
Technoprobe
temperature
Tensor Core
Test
Test Benchmark
Test Bin
Test Bus
test completeness
Test compression setup
Test Cost
test coverage
Test Data Analytics
Test data compression
Test Generation
Test Generation and Simulation
Test Inerface
Test metrics
Test pattern generation
Test Pin
Test Point Insertion
Test Points
Test Selection
test time optimization
Test Time Reduction
Testability
Testing
Testmethod
Thermal management
tie learning
Timing Analysis
Timing exception paths
Timing-aware
Timing-aware ATPG
timing-based
timing-critical
Timings
toggle coverage
TPI
Transfer Learning
Transfer Matrix Method
Transient Fault
transition delay fault (TDF)
transition delay faults
Transition Fault
transition faults
U
UDFM
Unconstrained Path
UVM
V
Validation
Vcell method
Vector Network Analyzer (VNA)
Verification
Verification IP (VIP)
Vision Transformer (ViT)
VLSI
VLV
Vmin
Voltage Deviation
Voltage Droop
Voltage fault injection (VFI)
Voltage Regulators
Voltage stress
W
wafer map pattern recognition
wafer-level integration
waveform generation
Waveguide to microstrip-line transition
weak and strong non-robust propagation conditions
Weight Permutation
Y
Yield
Yield Analysis and Optimization
Yield enhancement
Z
Zero Defect Quality
zero defects