ITC 2025: IEEE INTERNATIONAL TEST CONFERENCE

This page contains an index consisting of author-provided keywords.

5
5G Testing Enigneering	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
A
ABIST	Ultra dense SRAM Cell Test Challenges
ADC	Scan Test for 99% Defect Coverage of R-2R DACs
advance processes	Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost
advanced packaging	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications
aging	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
AI Agent	IEA-Plugin: An AI Agent Reasoner for Test Data Analytics
AI Hardware	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
analog test generation	Scan Test for 99% Defect Coverage of R-2R DACs
Anomaly Detection	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
Anomaly Diagnosis	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
Anti-Tamper	Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection
architecturally correct execution	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
ATE	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
ATPG	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs Test Pattern Aware Streaming Fabric-based Scan Test Methodology Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Automated Test Equipment	Influence of Automated Test Equipment Drift on Process Capability Studies
Automated Test Equipment (ATE)	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
Automated Test Pattern Generation (ATPG)	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Automatic Test Equipment (ATE)	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
Automatic test pattern generation (ATPG)	Scan Strategies for High Quality Latch Array Testing
automotive electronics	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
B
BIST	Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages
Bit line sense amplifier	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
built-in self-test (BIST)	Scan Strategies for High Quality Latch Array Testing
C
Calibration	Influence of Automated Test Equipment Drift on Process Capability Studies
cell aware	Chain Cell-Aware Diagnosis
cell-aware	Advanced fault model, diagnosis and applications for deep nanometer process LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
cell-aware ATPG	Advanced fault model, diagnosis and applications for deep nanometer process
Central Processing Unit	LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale
chain diagnosis	Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost Advanced fault model, diagnosis and applications for deep nanometer process
Chiplet interconnects	Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging
Chiplets	SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages
CIM	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
clock tree defect	Advanced fault model, diagnosis and applications for deep nanometer process
Compute-in-Memory	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
Confidentiality	QuEST: Quantitative Entropy-based Security and Trojan Detection Framework for Confidentiality Verification
Contactless flange rectangular waveguide	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
Continuous Monitoring	Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Controllability	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Core characteristic	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Core-V eXtension Interface (CV-X-IF)	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
CP Testing	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
Critical faults	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Critical Thickness Model	Stress Aware Quiescent Current Test Optimization
Cryptographic Accelerator	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
CVA6	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
D
DAC	Scan Test for 99% Defect Coverage of R-2R DACs Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
data converters	Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
Deep Neural Network	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
Defect activation	Stress Aware Quiescent Current Test Optimization
Defect characterization	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
defect modeling	Device-Aware Test for Threshold Voltage Shifting in FeFET
defect-finding	Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2
defect-oriented stress	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
defects	IC-PEPR: PEPR Testing Goes Intra-Cell
Delay fault testing	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Delay Test	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors Debugging and Preventing Abnormally High Vmin During Logic Scan Test Bring-up
Delay Testing	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications
Deobfuscation	Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis
design for diagnosis	Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects
Design for Test	Persistent High-Bandwidth IJTAG Data Delivery
Design-for-Test	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
Design-for-Testability (DFT)	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Device Under Test	Influence of Automated Test Equipment Drift on Process Capability Studies
device-aware test	Device-Aware Test for Threshold Voltage Shifting in FeFET
DFM and Test Diagnosis	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
DFT	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks Persistent High-Bandwidth IJTAG Data Delivery TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration Scan Test for 99% Defect Coverage of R-2R DACs Test Pattern Aware Streaming Fabric-based Scan Test Methodology Early Testing of Memory Redundant Row Elements
diagnosability	Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects
Diagnose Program	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
Diagnosis	Debugging and Preventing Abnormally High Vmin During Logic Scan Test Bring-up Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
diagnosis control points	Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects
diagnosis coverage	Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects
diagnosis observe points	Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects
diagnosis simulation	Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects
diagnostic fault simulation	Functional Logic Diagnosis with Observation Points on Next-State Variables
dithering	Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
DPPM	Full enablement of Very Low Voltage testing to deliver Zero Defect Quality automotive products
DRAM	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Drift	Influence of Automated Test Equipment Drift on Process Capability Studies
E
Elmore Delay	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Embedded deterministic test	Automated Selection of Optimal EDT Input Configuration
F
failure analysis	Chain Cell-Aware Diagnosis
Fan-out wafer-level packaging	Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages
fault collapsing	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Fault Coverage	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
fault diagnosis	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
fault dominance	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
fault equivalence	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Fault Injection	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
fault mode	Advanced fault model, diagnosis and applications for deep nanometer process
Fault Modeling	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
fault models	IC-PEPR: PEPR Testing Goes Intra-Cell Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Fault Propagation	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
Fault Simulation	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Fault-tolerance	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
FeFET	Device-Aware Test for Threshold Voltage Shifting in FeFET
FT Testing	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
functional sequences	Functional Logic Diagnosis with Observation Points on Next-State Variables
Functional Testing	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale
functionally possible faults	Functional Logic Diagnosis with Observation Points on Next-State Variables
G
Glitter PUF	Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection
global control signal diagnosis	Advanced fault model, diagnosis and applications for deep nanometer process
H
hardware cost	Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost
Hardware Security	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF) QuEST: Quantitative Entropy-based Security and Trojan Detection Framework for Confidentiality Verification
Hardware Telemetry	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
Hardware Trojan	QuEST: Quantitative Entropy-based Security and Trojan Detection Framework for Confidentiality Verification
HB-IJTAG	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks Persistent High-Bandwidth IJTAG Data Delivery
Hierarchical Test	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks Persistent High-Bandwidth IJTAG Data Delivery
Hw/SW co-design	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Hypergraph Theoretic Weighting	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
I
IEEE 1687	Persistent High-Bandwidth IJTAG Data Delivery
IEEE 1687 (IJTAG)	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
IEEE 1838	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications
IJTAG	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges Persistent High-Bandwidth IJTAG Data Delivery Scan Test for 99% Defect Coverage of R-2R DACs
Impedance Match	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
In Memory Computation	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
In-Field Testing	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
In-System Test	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
inter-cell bridge	Advanced fault model, diagnosis and applications for deep nanometer process
Interactive Test	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
interconnect	Chiplets' Die-to-Die Interconnect Repair Language (IRL)
intermittent fault	Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects
K
k-Way Partitioning	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
L
LA-DOS	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
LangGraph	IEA-Plugin: An AI Agent Reasoner for Test Data Analytics
language	Chiplets' Die-to-Die Interconnect Repair Language (IRL)
Large Language Model	LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale
latch array	Scan Strategies for High Quality Latch Array Testing
Latent defects	Shifting-left Zero Defect Scan Test Development to Launch Automotive PPM-ready products Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Latent gate oxide shorts	Stress Aware Quiescent Current Test Optimization
layout-aware	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
LBIST	Pseudo Random Low Power Built in Self Test
LDO	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
LLM	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
LLMs	IEA-Plugin: An AI Agent Reasoner for Test Data Analytics
Load Board	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Load Board (L/B)	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
logic diagnosis	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion Functional Logic Diagnosis with Observation Points on Next-State Variables
Low Power	Pseudo Random Low Power Built in Self Test
low-cost	Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
M
Machine Learning	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications
Manufacturing Test Setup	Persistent High-Bandwidth IJTAG Data Delivery
MBIST	Early Testing of Memory Redundant Row Elements
Measurement Variation	Influence of Automated Test Equipment Drift on Process Capability Studies
Memory Repair	Early Testing of Memory Redundant Row Elements
Memory test	Device-Aware Test for Threshold Voltage Shifting in FeFET
Microwave	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Millimeter-wave	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Mismatch	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Mixed-Signal	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Monte Carlo	Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging
Monte Carlo Sampling	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
multi-chiplet designs	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications
N
Non-Volatile Memory	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
NVM	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
O
Observability	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Offset cancelation	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Open defects	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Optics	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
optimization	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
P
P1687.2	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Passive PUF	Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection
PDL2	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Phantom	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Physical Failure Analysis	Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Physical Unclonable Function	Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection
PICS	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Power Side-channel Attack	Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis
PPM	Shifting-left Zero Defect Scan Test Development to Launch Automotive PPM-ready products
Pre-Silicon/Post-Silicon	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Probabilistic Estimation	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
Probe Card	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Probe Card (P/C)	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
Process Capability	Influence of Automated Test Equipment Drift on Process Capability Studies
Process Variation	Influence of Automated Test Equipment Drift on Process Capability Studies
Pseudo-Boolean Satisfiability	Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis
PSS	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
push-on mating mm-wave interface	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
PyTorch Models	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Q
Quantitative vulnerability	QuEST: Quantitative Entropy-based Security and Trojan Detection Framework for Confidentiality Verification
R
Register Transfer Level	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
Reliability	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
reliability analysis	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
ReLU	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
repair	Chiplets' Die-to-Die Interconnect Repair Language (IRL)
Repair prioritization	Ultra dense SRAM Cell Test Challenges
Resistive fault dominance	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Reverse Engineering	An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
RF Network	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
Ring Oscillator	Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging
RISC-V	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
RISC-V E-Trace	Embedded Trace: A Key Enabler for Silicon Lifecycle Management
RRAM	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
RTL-Level PSC Analysis	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
S
S-parameter	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
Satisfiability Modulo Theories	An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
scan	Scan Strategies for High Quality Latch Array Testing
scan chain diagnosis	Chain Cell-Aware Diagnosis
scan diagnosis	Advanced fault model, diagnosis and applications for deep nanometer process
Scan Instrumentation	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Scan Switching	Pseudo Random Low Power Built in Self Test
scan test	IC-PEPR: PEPR Testing Goes Intra-Cell Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Scan-based test	Automated Selection of Optimal EDT Input Configuration
Semiconductor	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Semiconductor Performance Modeling	Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Shift-Left	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Silent Data Corruption	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Silent Data Corruption in AI devices	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
Silent data error	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Silent Data Errors	Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Silicon Debug	Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Silicon Lifecycle Management	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Silicon Odometer Sensing	Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Silicon Photonic	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Silicon Photonics	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
silicon practice	Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2
Simulated Annealing	SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages
small delay	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
small delay defect	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
small-delay defects	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
small-delay-defect	Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2
SOC Test	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks Persistent High-Bandwidth IJTAG Data Delivery
software-hardware co-design	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
speed-up	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
SSN	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks Persistent High-Bandwidth IJTAG Data Delivery In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
Stability	Ultra dense SRAM Cell Test Challenges
State Element Identification	An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
Static Random-Access Memory (SRAM)	Scan Strategies for High Quality Latch Array Testing
Streaming Fabric	Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Streaming Scan Network	Persistent High-Bandwidth IJTAG Data Delivery
Stress coverage	Stress Aware Quiescent Current Test Optimization
Stress time	Stress Aware Quiescent Current Test Optimization
stuck-at fault (SAF)	Scan Strategies for High Quality Latch Array Testing
stuck-at faults	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
System-on-Chip (SOC)	Test Pattern Aware Streaming Fabric-based Scan Test Methodology
system-on-wafer	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications
T
Technoprobe	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
temperature	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
Test	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges Ultra dense SRAM Cell Test Challenges
Test Benchmark	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Test Bus	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Test compression setup	Automated Selection of Optimal EDT Input Configuration
test coverage	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Test Data Analytics	IEA-Plugin: An AI Agent Reasoner for Test Data Analytics
Test data compression	Automated Selection of Optimal EDT Input Configuration
Test Inerface	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
Test metrics	IC-PEPR: PEPR Testing Goes Intra-Cell
Test pattern generation	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
Test Pin	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Test Point Insertion	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
Test Points	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Test Time Reduction	Persistent High-Bandwidth IJTAG Data Delivery
Testability	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Testmethod	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
timing analysis	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Timing-aware	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
timing-based	Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2
timing-critical	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
toggle coverage	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
TPI	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Transfer Learning	Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Transfer Matrix Method	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
Transient Fault	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
transition delay fault (TDF)	Scan Strategies for High Quality Latch Array Testing
transition delay faults	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Transition Fault	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications
U
UDFM	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs Shifting-left Zero Defect Scan Test Development to Launch Automotive PPM-ready products
Unconstrained Path	Debugging and Preventing Abnormally High Vmin During Logic Scan Test Bring-up
unique fail bit	Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects
V
Vcell method	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Vector Network Analyzer (VNA)	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE)
VLSI	Shifting-left Zero Defect Scan Test Development to Launch Automotive PPM-ready products
VLV	Full enablement of Very Low Voltage testing to deliver Zero Defect Quality automotive products
Vmin	Debugging and Preventing Abnormally High Vmin During Logic Scan Test Bring-up
Voltage stress	Stress Aware Quiescent Current Test Optimization
W
wafer-level integration	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications
waveform generation	Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
Waveguide to microstrip-line transition	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
Y
Yield Analysis and Optimization	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
yield enhancement	Using Unique Fail Bits to Maximize Chain Diagnosis Coverage for Silicon Defects
Z
Zero Defect Quality	Full enablement of Very Low Voltage testing to deliver Zero Defect Quality automotive products
zero defects	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs

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