ITC 2025: IEEE INTERNATIONAL TEST CONFERENCE

This page contains an index consisting of author-provided keywords.

2
2.5D	Sharing Scan Bandwidth Across Die to Die in MCM Package
2.5D 3D heterogeneous	HPC AI Processors -- ATE-related challenges & directions
5
5G Testing Enigneering	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE)
A
ABIST	Ultra dense SRAM Cell Test Challenges
accelerated aging stress	Assessing Long-Term Reliability through Accelerated Aging Stress Tests on a On-chip Quality and Reliability Platform : A Band Gap Reference case study
ACCESSLINK	Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink
Accuracy	High performance advanced fault model diagnosis
ADC	Scan Test for 99% Defect Coverage of R-2R DACs
advance processes	Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost
advanced packaging	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications
Advanced Probe Hardware	Advancing Optical Test Strategies for AI-Driven Silicon Photonics
aging	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions An On-Chip Sensor For Online Monitoring of HCI-Induced Aging In Integrated Circuits Assessing Long-Term Reliability through Accelerated Aging Stress Tests on a On-chip Quality and Reliability Platform : A Band Gap Reference case study
AI Agent	IEA-Plugin: An AI Agent Reasoner for Test Data Analytics
AI Hardware	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
AI Hardware Accelerator	Testing of Passive Memristive Crossbars in AI Hardware Accelerators
analog test generation	Scan Test for 99% Defect Coverage of R-2R DACs
Anomaly Detection	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
Anomaly Diagnosis	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
Anti-Tamper	Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection
Anti-Tampering	Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection
arbitrary waveform generator	FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals
architecturally correct execution	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Assertion-Based Verification	LAMBDA: LLM-Assisted Malicious Bug Detection and Analysis in Hardware Designs
At-speed testing	Most Effective At-Speed Test: Hybrid Launch-Off-Shift and Capture Technique
ATE	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges The Role SLT Plays at Intel Low Noise 20-bit DAC for ATE Origen Based Test and Validation Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals New ATE needs for the Era of Advanced Packaging and Heterogeneous Integration
ATPG	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs High performance advanced fault model diagnosis Sharing Scan Bandwidth Across Die to Die in MCM Package Dynamic SCAN Shift in High Volume Manufacturing Testing for Test Time Optimization Hybrid Static Learning for ATPG Test Pattern Aware Streaming Fabric-based Scan Test Methodology Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG Test Pattern Aware Streaming Fabric-based Scan Test Methodology
ATPG Techniques	Resurgence in Advanced ATPG Techniques for High-Performance Designs
auto generated PDL	Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness
auto-range
Automated Test Equipment	Advancing ATE for EV Battery Management: Overcoming Test Challenges with Smart Solutions Influence of Automated Test Equipment Drift on Process Capability Studies Influence of Automated Test Equipment Drift on Process Capability Studies
Automated Test Equipment (ATE)	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application Optimizing Sensing Point Placement for High-Multi-Site Testing on Device Interface Boards
Automated Test Pattern Generation (ATPG)	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Automated workflows	New ATE needs for the Era of Advanced Packaging and Heterogeneous Integration
Automatic Test Equipment (ATE)	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE)
Automatic test pattern generation (ATPG)	Scan Strategies for High Quality Latch Array Testing Scan Strategies for High Quality Latch Array Testing
automation	FSWGEN: a Device-tree Specification driven System-Level Test workload generator Multi-die package and chiplet test applications
automotive	Assessment of System-Level Test programs in Automotive SoCs FSWGEN: a Device-tree Specification driven System-Level Test workload generator
automotive electronics	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
B
band gap reference BGR	Assessing Long-Term Reliability through Accelerated Aging Stress Tests on a On-chip Quality and Reliability Platform : A Band Gap Reference case study
Battery Management System	Advancing ATE for EV Battery Management: Overcoming Test Challenges with Smart Solutions
Battery Management Systems
Benchmark	A Benchmark Suite to Evaluate DNN’s Resilience
BEOL Defects
bio submission
BIST	Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages IEEE P1450.6.2: Core Test Language (CTL) for Memories An update to the existing standard
Bit line sense amplifier	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Bit-Flip Attack (BFA)	FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks
board test	Multi-die package and chiplet test applications
BTI	An On-Chip Sensor For Online Monitoring of HCI-Induced Aging In Integrated Circuits
Bug Detection	LAMBDA: LLM-Assisted Malicious Bug Detection and Analysis in Hardware Designs
Built-In Redundancy Analysis	Early Testing of Memory Redundant Row Elements
Built-In Self-Repair	Early Testing of Memory Redundant Row Elements
Built-In Self-Test	Early Testing of Memory Redundant Row Elements
built-in self-test (BIST)	Scan Strategies for High Quality Latch Array Testing Scan Strategies for High Quality Latch Array Testing
Bus Functional Model(BFM)	AMBA Qchannel based power management VIP for Efficient low power validation
C
Calibration	Influence of Automated Test Equipment Drift on Process Capability Studies Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks Influence of Automated Test Equipment Drift on Process Capability Studies
cascaded PLLs
cell aware	Chain Cell-Aware Diagnosis
cell-aware	Advanced fault model, diagnosis and applications for deep nanometer process LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
cell-aware ATPG	Advanced fault model, diagnosis and applications for deep nanometer process
cell-aware test	Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation
Central Processing Unit	LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale
chain diagnosis	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost Advanced fault model, diagnosis and applications for deep nanometer process
characterization
chip aging
chiplet	Multi-die package and chiplet test applications
Chiplet interconnects	Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging
Chiplet-based system	Chiplet Interconnect Test and Repair
chiplets	SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages Sharing Scan Bandwidth Across Die to Die in MCM Package
CIM	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
circuit reliability	Graph Attention Network Based Fault Prediction Framework for Functional Safety Verification
CLASS	The Role SLT Plays at Intel
Clock	Method for Diagnosing Clock Jitter Using FPGA
clock tree defect	Advanced fault model, diagnosis and applications for deep nanometer process
CMOS
CNN	FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks
Co-packaged Optics	CPO is Coming: Are Your Test Solutions HVM Ready?
Colored Petri Nets	Early Reliability Estimation in Hardware Accelerators through an Improved Colored Petri Net Approach
common-input learning	Hybrid Static Learning for ATPG
Compression	Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time
Computation-in-memory	Combined Array and ADC Structural Test for RRAM-based Multiply-and-accumulate Circuits
Compute-in-Memory	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks
conditionally-activated fault	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects
Confidentiality	QuEST: Quantitative Entropy-based Security and Trojan Detection Framework for Confidentiality Verification
Configuration	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
consistency verification	Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness
Contactless flange rectangular waveguide	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
Continuous Monitoring	Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Controllability	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Core	Hierarchical Test Using Running MISR Signatures
Core characteristic	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Core-V eXtension Interface (CV-X-IF)	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
Coverage closure	STARTS: Simulation Traits Assisted Random Test Selection for Multiprocessor Verification
CP Testing	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE)
CPO	CPO is Coming: Are Your Test Solutions HVM Ready?
critical circuit nodes	Graph Attention Network Based Fault Prediction Framework for Functional Safety Verification
Critical faults	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Critical Thickness Model	Stress Aware Quiescent Current Test Optimization
Cryptographic Accelerator	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
current range
Custom clock controller	Enhancing scan coverage in mixed signal designs by clock and reset manipulation during testing
Custom MBIST Algorithm	DMA Burst Mode Fault Detection: Custom MBIST Strategies for Comprehensive Testing
Custom operation set	DMA Burst Mode Fault Detection: Custom MBIST Strategies for Comprehensive Testing
Custom reset controller	Enhancing scan coverage in mixed signal designs by clock and reset manipulation during testing
CVA6	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
CWE	LAMBDA: LLM-Assisted Malicious Bug Detection and Analysis in Hardware Designs
D
D2D	Sharing Scan Bandwidth Across Die to Die in MCM Package
DAC	Scan Test for 99% Defect Coverage of R-2R DACs Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering Low Noise 20-bit DAC for ATE Statistical Analysis of the Nonlinearity Errors of Unary and Binary-Weighted DACs
Data Center Systems	Why is Rigorous PCIe LTSSM Testing is Key to Robust and Reliable Systems?
data converters	Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
Debugging	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
Deep Learning	Deep Learning-based IC Monitoring A Benchmark Suite to Evaluate DNN’s Resilience
Deep Neural Network	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
Defect activation	Stress Aware Quiescent Current Test Optimization
Defect characterization	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Defect diagnosis	Chiplet Interconnect Test and Repair
defect modeling	Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET
defect-finding	Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2
defect-oriented stress	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Defect-oriented test
defects	IC-PEPR: PEPR Testing Goes Intra-Cell
Delay fault testing	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Delay Test	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up
Delay test coverage	Precise Approach to ATPG: Handling Timing Exceptions for Better Small Delay Defect Coverage
Delay Testing	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications Deep Learning-based IC Monitoring
delay-line array
Deobfuscation	Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis
Dependability	FSWGEN: a Device-tree Specification driven System-Level Test workload generator
design for diagnosis	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects
Design for Test	Persistent High-Bandwidth IJTAG Data Delivery
Design for Test (DFT)	Most Effective At-Speed Test: Hybrid Launch-Off-Shift and Capture Technique Structural Testing on SLT Platform with HSAT IP & High-Speed I/O Access
Design Space Exploration	Early Reliability Estimation in Hardware Accelerators through an Improved Colored Petri Net Approach
Design-For-Test	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time
Design-for-Testability (DFT)	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Device Interface Board (DIB)	Optimizing Sensing Point Placement for High-Multi-Site Testing on Device Interface Boards
Device Testing	Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction
Device Under Test	Influence of Automated Test Equipment Drift on Process Capability Studies Influence of Automated Test Equipment Drift on Process Capability Studies
device-aware test	Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET
DFM and Test Diagnosis	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
DFT	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks Persistent High-Bandwidth IJTAG Data Delivery TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration Scan Test for 99% Defect Coverage of R-2R DACs Test Pattern Aware Streaming Fabric-based Scan Test Methodology Early Testing of Memory Redundant Row Elements Deep Learning-based IC Monitoring Implementation and Optimization of High-Bandwidth IJTAG for Enhanced Test Time Reduction in Complex SoCs
diagnosability	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects
Diagnose Program	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE)
Diagnosis	Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing High performance advanced fault model diagnosis Method for Diagnosing Clock Jitter Using FPGA
diagnosis control points	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects
diagnosis coverage	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects
diagnosis observe points	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects
diagnosis simulation	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects
diagnostic fault simulation	Functional Logic Diagnosis with Observation Points on Next-State Variables
Diagnostics	Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time
die test	Breaking the Memory Wall: Wafer-Level Test Strategies for Heterogeneous Integration
die-to-wafer	Breaking the Memory Wall: Wafer-Level Test Strategies for Heterogeneous Integration
Differential non-linearity (DNL)	Statistical Analysis of the Nonlinearity Errors of Unary and Binary-Weighted DACs
digital tester	A Novel Tester-Based Approach for Functional Testing of Hardware Timers
DIMM	Thermal Management in System Level Test: Analysis of existing solutions and an introduction to advanced liquid cooled memory solutions
Direct Memory Access	DMA Burst Mode Fault Detection: Custom MBIST Strategies for Comprehensive Testing
distinguishing bit	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects
dithering	Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
DNL	Low Noise 20-bit DAC for ATE
DPM	The Role SLT Plays at Intel
DPPM	Full enablement of Very Low Voltage testing to deliver Zero Defect Quality automotive products
DRAM	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
Drift	Influence of Automated Test Equipment Drift on Process Capability Studies Influence of Automated Test Equipment Drift on Process Capability Studies
Dummy
Dynamic Voltage and Frequency Scaling (DVFS)	MUX-based Polymorphic Registers and FSMs to Protect Against Non-invasive Voltage Fault Injection Attacks
Dynamic voltage and frequency scaling (DVFS) Polymorphic latch
E
ease of debuggability	Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness
EDA	New ATE needs for the Era of Advanced Packaging and Heterogeneous Integration
Electric Vehicles	Advancing ATE for EV Battery Management: Overcoming Test Challenges with Smart Solutions
Elmore Delay	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Embedded deterministic test	Automated Selection of Optimal EDT Input Configuration
Embedded test	Secure and Efficient Sharing of On-Chip Resources
Entitlement	Test Bin Entitlement: Yield Outlier Detection using Die Area and LLM based Bin-Grouping
equivalence learning	Hybrid Static Learning for ATPG
Error Injection	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
Extrinsic Variations
eye diagram	Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
F
failure analysis	Chain Cell-Aware Diagnosis
False path	Precise Approach to ATPG: Handling Timing Exceptions for Better Small Delay Defect Coverage
Fan-out wafer-level packaging	Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages
fault collapsing	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation
Fault Coverage	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency DMA Burst Mode Fault Detection: Custom MBIST Strategies for Comprehensive Testing
fault diagnosis	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
fault dominance	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation
fault equivalence	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation
Fault Injection	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis Early Reliability Estimation in Hardware Accelerators through an Improved Colored Petri Net Approach A Benchmark Suite to Evaluate DNN’s Resilience
Fault Injection Attack
Fault Injection Attack (FIA)	FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks
fault list optimization	Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation
fault mode	Advanced fault model, diagnosis and applications for deep nanometer process
Fault Modeling	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
fault models	IC-PEPR: PEPR Testing Goes Intra-Cell High performance advanced fault model diagnosis Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation
Fault Propagation	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
fault simulation	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation
Fault Tolerance	FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks
Fault-Aware Training
Fault-tolerance	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
FeFET	Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET
FeFETs
femtosecond	Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
Ferroelectric FETs (FeFETs)	FeTest: Testing of FeFET-Based Memory Arrays
flip-flop	Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
Fmax	Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction
Four-wire (Kelvin) Measurement	Optimizing Sensing Point Placement for High-Multi-Site Testing on Device Interface Boards
FPGA	FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals Method for Diagnosing Clock Jitter Using FPGA High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops A Novel Tester-Based Approach for Functional Testing of Hardware Timers
FT Testing	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE)
functional fault simulations	System-Level Test techniques for Automotive SoCs
functional launch-on-capture (FLOC) tests
Functional Safety	Graph Attention Network Based Fault Prediction Framework for Functional Safety Verification
functional sequences	Functional Logic Diagnosis with Observation Points on Next-State Variables Functional Logic Diagnosis with Observation Points on Next-State Variables
functional switching activity
functional testing	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale System-Level Test techniques for Automotive SoCs A Novel Tester-Based Approach for Functional Testing of Hardware Timers
functionally possible faults	Functional Logic Diagnosis with Observation Points on Next-State Variables
G
Gaussian noise generation	FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals
Generalized extreme value distribution	Statistical Analysis of the Nonlinearity Errors of Unary and Binary-Weighted DACs
Generative AI	Teaching Llamas to Test: A Language-Based Approach
Generic Circuit Learning	Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis
Glitter PUF	Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection
global control signal diagnosis	Advanced fault model, diagnosis and applications for deep nanometer process
Graph Attention Network	Graph Attention Network Based Fault Prediction Framework for Functional Safety Verification
Ground bounce	Chiplet Interconnect Test and Repair
Guard Bands	Machine Learning Assisted Vmin Prediction
H
Hardware Accelerator	FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks
hardware cost	Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost
Hardware Security	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF) QuEST: Quantitative Entropy-based Security and Trojan Detection Framework for Confidentiality Verification Secure and Efficient Sharing of On-Chip Resources
Hardware Telemetry	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption
hardware testing	A Novel Tester-Based Approach for Functional Testing of Hardware Timers
hardware timers	A Novel Tester-Based Approach for Functional Testing of Hardware Timers
Hardware Trojan	QuEST: Quantitative Entropy-based Security and Trojan Detection Framework for Confidentiality Verification
HB-IJTAG	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks Persistent High-Bandwidth IJTAG Data Delivery Implementation and Optimization of High-Bandwidth IJTAG for Enhanced Test Time Reduction in Complex SoCs
HBM	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
HCI	An On-Chip Sensor For Online Monitoring of HCI-Induced Aging In Integrated Circuits
Hierarchical	Hierarchical Test Using Running MISR Signatures
Hierarchical Design for test (DFT)	Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Hierarchical Test	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks Persistent High-Bandwidth IJTAG Data Delivery
High Speed Access Test (HSAT)	Structural Testing on SLT Platform with HSAT IP & High-Speed I/O Access
High-Speed IO	Why is Rigorous PCIe LTSSM Testing is Key to Robust and Reliable Systems?
High-volume Manufacturing	CPO is Coming: Are Your Test Solutions HVM Ready?
Hot Carier induced	An On-Chip Sensor For Online Monitoring of HCI-Induced Aging In Integrated Circuits
HPC	New ATE needs for the Era of Advanced Packaging and Heterogeneous Integration
HSIO	The Role SLT Plays at Intel
HVM	The Role SLT Plays at Intel CPO is Coming: Are Your Test Solutions HVM Ready?
Hw/SW co-design	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Hybrid launch-off-shift and capture	Most Effective At-Speed Test: Hybrid Launch-Off-Shift and Capture Technique
Hypergraph Theoretic Weighting	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
I
IC Monitoring	Deep Learning-based IC Monitoring
ICL	Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink
IDD
IEEE 1149.1	Test Access and Instruments Control - IEEE Std Families 1149 and 1687
IEEE 1500	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
IEEE 1687	Persistent High-Bandwidth IJTAG Data Delivery Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink Test Access and Instruments Control - IEEE Std Families 1149 and 1687
IEEE 1687 (IJTAG)	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
IEEE 1838	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications
IEEE P1687.1	Test Access and Instruments Control - IEEE Std Families 1149 and 1687
IEEE P1687.2	Test Access and Instruments Control - IEEE Std Families 1149 and 1687
IEEE Standards	Test Technology Standards Committee Overview & IEEE Std 1450 (STIL) Updates
IEEE Std. 1687	Secure and Efficient Sharing of On-Chip Resources
IEEE~1687 (IJTAG)	Implementation and Optimization of High-Bandwidth IJTAG for Enhanced Test Time Reduction in Complex SoCs
IJTAG	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges Persistent High-Bandwidth IJTAG Data Delivery Scan Test for 99% Defect Coverage of R-2R DACs Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink Secure and Efficient Sharing of On-Chip Resources
Impedance Match	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE)
implication learning	Hybrid Static Learning for ATPG
In Memory Computation	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
In-Field Testing	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
In-System Test	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
INL	Low Noise 20-bit DAC for ATE
Integral
Integral non-linearity (INL)	Statistical Analysis of the Nonlinearity Errors of Unary and Binary-Weighted DACs
inter-cell bridge	Advanced fault model, diagnosis and applications for deep nanometer process
Interactive Test	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
interconnect	Chiplets' Die-to-Die Interconnect Repair Language (IRL) Multi-die package and chiplet test applications
Interconnect ATPG	Chiplet Interconnect Test and Repair
Interconnect Repair Language	Chiplet Interconnect Test and Repair
Interconnect Test and Repair	Chiplet Interconnect Test and Repair
ITC 2025
J
Jitter	Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals Method for Diagnosing Clock Jitter Using FPGA
jitter injection	FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals
JTAG	A Novel Tester-Based Approach for Functional Testing of Hardware Timers
K
k-Way Partitioning	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
L
LA-DOS	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
LangGraph	IEA-Plugin: An AI Agent Reasoner for Test Data Analytics
language	Chiplets' Die-to-Die Interconnect Repair Language (IRL)
Large Language Model	LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale
Large Language Models	Teaching Llamas to Test: A Language-Based Approach
latch array	Scan Strategies for High Quality Latch Array Testing Scan Strategies for High Quality Latch Array Testing
Latent defects	Shifting-left Zero Defect Scan Test Development to Launch Automotive PPM-ready products Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Latent gate oxide shorts	Stress Aware Quiescent Current Test Optimization
Launch-off-capture	Most Effective At-Speed Test: Hybrid Launch-Off-Shift and Capture Technique
Launch-off-shift	Most Effective At-Speed Test: Hybrid Launch-Off-Shift and Capture Technique
layout-aware	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
LBIST	Pseudo Random Low Power Built in Self Test Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time
LDO	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Linear Regression	Machine Learning Assisted Vmin Prediction
Liquid Cooling	Thermal Management in System Level Test: Analysis of existing solutions and an introduction to advanced liquid cooled memory solutions
LLM	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration Test Bin Entitlement: Yield Outlier Detection using Die Area and LLM based Bin-Grouping
LLMs	IEA-Plugin: An AI Agent Reasoner for Test Data Analytics LAMBDA: LLM-Assisted Malicious Bug Detection and Analysis in Hardware Designs
Load Board	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Load Board (L/B)	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE)
logic diagnosis	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion Functional Logic Diagnosis with Observation Points on Next-State Variables Functional Logic Diagnosis with Observation Points on Next-State Variables
Low Power	Pseudo Random Low Power Built in Self Test
low-cost	Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
LTSSM	Why is Rigorous PCIe LTSSM Testing is Key to Robust and Reliable Systems?
M
Machine Learning	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications Machine Learning Assisted Vmin Prediction Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction A Benchmark Suite to Evaluate DNN’s Resilience
Machine learning based BIST	A Machine Learning based Built-in Self-test Method for Lifetime Frequency Drift Compensation of Precision Oscillators
Manufacturing	Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction
manufacturing test	System-Level Test techniques for Automotive SoCs
Manufacturing Test Setup	Persistent High-Bandwidth IJTAG Data Delivery
March Testing
Marginal Defects	The Role SLT Plays at Intel
MBIST	DMA Burst Mode Fault Detection: Custom MBIST Strategies for Comprehensive Testing Early Testing of Memory Redundant Row Elements
MCM	Sharing Scan Bandwidth Across Die to Die in MCM Package
Measurement Variation	Influence of Automated Test Equipment Drift on Process Capability Studies Influence of Automated Test Equipment Drift on Process Capability Studies
Memory	Thermal Management in System Level Test: Analysis of existing solutions and an introduction to advanced liquid cooled memory solutions IEEE P1450.6.2: Core Test Language (CTL) for Memories An update to the existing standard
Memory Arrays	FeTest: Testing of FeFET-Based Memory Arrays
Memory Controller	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
Memory Repair	Early Testing of Memory Redundant Row Elements
Memory test	Device-Aware Test for Threshold Voltage Shifting in FeFET Device-Aware Test for Threshold Voltage Shifting in FeFET
memory wall	Breaking the Memory Wall: Wafer-Level Test Strategies for Heterogeneous Integration
Memory-BIST	FeTest: Testing of FeFET-Based Memory Arrays
Memristor	Testing of Passive Memristive Crossbars in AI Hardware Accelerators
Memristors
Microwave	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Millimeter-wave	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Mismatch	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
MISR	Hierarchical Test Using Running MISR Signatures Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time
Mixed-Signal	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
ML in Testing	Deep Learning-based IC Monitoring
Model	IEEE P1450.6.2: Core Test Language (CTL) for Memories An update to the existing standard
Model Robustness	FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks
moderator
Monte Carlo	Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging
Monte Carlo Sampling	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
multi-chiplet designs	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications
Multi-cycle path	Precise Approach to ATPG: Handling Timing Exceptions for Better Small Delay Defect Coverage
multi-GHz testing	FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals
multi-gigahertz	Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
multiplexer	Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
Multiply-and-accumulate	Combined Array and ADC Structural Test for RRAM-based Multiply-and-accumulate Circuits
Multiprocessor verification	STARTS: Simulation Traits Assisted Random Test Selection for Multiprocessor Verification
multisite probe	Wafer Map Pattern Recognition for Multisite Probe with Synthetic Data Augmented Training
N
Neural Networks
Neuromorphic computing	Wafer Map Pattern Recognition using Ternary Spiking Neural Network
non-linearity (INL)
Non-robust tests	Deep Learning-based IC Monitoring
Non-scan Testing	Resurgence in Advanced ATPG Techniques for High-Performance Designs
Non-Volatile Memory	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
NVM	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures
O
Observability	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
observation points	Functional Logic Diagnosis with Observation Points on Next-State Variables
Offset cancelation	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
On-chip	Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time
On-chip authentication	Secure and Efficient Sharing of On-Chip Resources
On-chip calibration	A Machine Learning based Built-in Self-test Method for Lifetime Frequency Drift Compensation of Precision Oscillators
Open defects	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Optical	CPO is Coming: Are Your Test Solutions HVM Ready?
Optical Probe Card	High performances PIC probing using high-accuracy positioning flexures, ultra-short and ultra-fine pitch probes and FAU integration
Optical Test Scaling	Advancing Optical Test Strategies for AI-Driven Silicon Photonics
Optical/Electrical Co-Integration	High performances PIC probing using high-accuracy positioning flexures, ultra-short and ultra-fine pitch probes and FAU integration
Optics	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
optimization	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Origen	Origen Based Test and Validation
Oscillator frequency drift	A Machine Learning based Built-in Self-test Method for Lifetime Frequency Drift Compensation of Precision Oscillators
Outlier Detection	Test Bin Entitlement: Yield Outlier Detection using Die Area and LLM based Bin-Grouping
overclock	Dynamic SCAN Shift in High Volume Manufacturing Testing for Test Time Optimization
P
P1687.2	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Padulo
Parametric Measurement Unit	Advancing ATE for EV Battery Management: Overcoming Test Challenges with Smart Solutions
Passive Memristor Crossbar	Testing of Passive Memristive Crossbars in AI Hardware Accelerators
Passive PUF	Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection
path delay faults
pattern retargeting	Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness
PCIe Interoperability	Why is Rigorous PCIe LTSSM Testing is Key to Robust and Reliable Systems?
PDL	Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink
PDL2	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Performance	High performance advanced fault model diagnosis
Phantom	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
phase locked loops	High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops
Physical Failure Analysis	Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Physical Unclonable Function	Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflection
physically unclonable function	High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops
picosecond	Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
PICS	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Platform Level Test	Why is Rigorous PCIe LTSSM Testing is Key to Robust and Reliable Systems?
PLL	Method for Diagnosing Clock Jitter Using FPGA
Polarization Defects
polymorphic FSM	MUX-based Polymorphic Registers and FSMs to Protect Against Non-invasive Voltage Fault Injection Attacks
Polymorphic Latch	MUX-based Polymorphic Registers and FSMs to Protect Against Non-invasive Voltage Fault Injection Attacks
Polymorphic Register	MUX-based Polymorphic Registers and FSMs to Protect Against Non-invasive Voltage Fault Injection Attacks
Post-Silicon Validation	Why is Rigorous PCIe LTSSM Testing is Key to Robust and Reliable Systems?
Power management(PM)	AMBA Qchannel based power management VIP for Efficient low power validation
Power Side-channel Attack	Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis
Power-Aware	AMBA Qchannel based power management VIP for Efficient low power validation
PPM	Shifting-left Zero Defect Scan Test Development to Launch Automotive PPM-ready products
Pre-Silicon/Post-Silicon	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Probabilistic Estimation	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
Probe Card	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Probe Card (P/C)	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE)
Process Capability	Influence of Automated Test Equipment Drift on Process Capability Studies Influence of Automated Test Equipment Drift on Process Capability Studies
Process Variation	Influence of Automated Test Equipment Drift on Process Capability Studies Influence of Automated Test Equipment Drift on Process Capability Studies
Processor Trace	Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Production Testing	High performances PIC probing using high-accuracy positioning flexures, ultra-short and ultra-fine pitch probes and FAU integration
Pseudo-Boolean Satisfiability	Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis
PSS	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
push-on mating mm-wave interface	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
PyTorch Models	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Q
Q-channel	AMBA Qchannel based power management VIP for Efficient low power validation
quality and reliability	Assessing Long-Term Reliability through Accelerated Aging Stress Tests on a On-chip Quality and Reliability Platform : A Band Gap Reference case study
Quantitative vulnerability	QuEST: Quantitative Entropy-based Security and Trojan Detection Framework for Confidentiality Verification
R
Random failures	Precise Approach to ATPG: Handling Timing Exceptions for Better Small Delay Defect Coverage
Randomization	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
reconfigurable scan network	Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness
Redundancy	Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks
Refresh	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
Register Transfer Level	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
Regression	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
Reliability	Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation Assessment of System-Level Test programs in Automotive SoCs A Novel Tester-Based Approach for Functional Testing of Hardware Timers A Benchmark Suite to Evaluate DNN’s Resilience
reliability analysis	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Reliability Estimation	Early Reliability Estimation in Hardware Accelerators through an Improved Colored Petri Net Approach
ReLU	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Relxpert	An On-Chip Sensor For Online Monitoring of HCI-Induced Aging In Integrated Circuits
repair	Chiplets' Die-to-Die Interconnect Repair Language (IRL) IEEE P1450.6.2: Core Test Language (CTL) for Memories An update to the existing standard
Repair prioritization	Ultra dense SRAM Cell Test Challenges
ReRAM Test	Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks
Resistance Variation	Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks
Resistive fault dominance	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Resistive RAM	Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks
Resolution	High performance advanced fault model diagnosis
Reverse Engineering	An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
RF Network	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE)
Ring Oscillator	Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging
Ring Oscillators	Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction
RISC-V	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF) Embedded Trace: A Key Enabler for Silicon Lifecycle Management
RISC-V E-Trace	Embedded Trace: A Key Enabler for Silicon Lifecycle Management
RMS	Low Noise 20-bit DAC for ATE
RRAM	Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
RRAMs	Combined Array and ADC Structural Test for RRAM-based Multiply-and-accumulate Circuits
RTL	Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness
RTL-Level PSC Analysis	Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
S
S-parameter	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE)
SAT
Satisfiability Modulo Theories	An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
Sblindato
scan	Sharing Scan Bandwidth Across Die to Die in MCM Package Scan Strategies for High Quality Latch Array Testing Scan Strategies for High Quality Latch Array Testing
Scan Architecture	Test Pattern Aware Streaming Fabric-based Scan Test Methodology
scan chain diagnosis	Chain Cell-Aware Diagnosis
scan diagnosis	Advanced fault model, diagnosis and applications for deep nanometer process
Scan IJTAG Host (SIH)	Implementation and Optimization of High-Bandwidth IJTAG for Enhanced Test Time Reduction in Complex SoCs
Scan Instrumentation	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
scan shift	Dynamic SCAN Shift in High Volume Manufacturing Testing for Test Time Optimization
Scan Switching	Pseudo Random Low Power Built in Self Test
Scan Test	IC-PEPR: PEPR Testing Goes Intra-Cell Test Pattern Aware Streaming Fabric-based Scan Test Methodology Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Scan-based test	Automated Selection of Optimal EDT Input Configuration
selective hardening	Graph Attention Network Based Fault Prediction Framework for Functional Safety Verification
Semiconductor	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Semiconductor Performance Modeling	Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Sensing Point Placement	Optimizing Sensing Point Placement for High-Multi-Site Testing on Device Interface Boards
Sensor
sequential ATPG	Enhancing scan coverage in mixed signal designs by clock and reset manipulation during testing
serializer	Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
Server
session 13D
Shift-Left	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
SIB	Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink
SiGe	Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
Signatures	Hierarchical Test Using Running MISR Signatures
Silent Data Corruption	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale The Role SLT Plays at Intel Precise Approach to ATPG: Handling Timing Exceptions for Better Small Delay Defect Coverage CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Silent Data Corruption in AI devices	In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
Silent data error	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Silent Data Errors	Embedded Trace: A Key Enabler for Silicon Lifecycle Management TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption
Silicon Debug	Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Silicon Lifecycle Management	OCTANE: On-Chip Telemetry-based Anomaly Notification Engine Embedded Trace: A Key Enabler for Silicon Lifecycle Management Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Silicon Odometer Sensing	Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Silicon Photonic	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Silicon Photonics	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning CPO is Coming: Are Your Test Solutions HVM Ready? Advancing Optical Test Strategies for AI-Driven Silicon Photonics
silicon practice	Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2
Simulated Annealing	SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages
simulation time	Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness
Simulation Trait	STARTS: Simulation Traits Assisted Random Test Selection for Multiprocessor Verification
SLT	The Role SLT Plays at Intel Thermal Management in System Level Test: Analysis of existing solutions and an introduction to advanced liquid cooled memory solutions
small delay	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
small delay defect	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion Precise Approach to ATPG: Handling Timing Exceptions for Better Small Delay Defect Coverage
small-delay defects	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation
small-delay-defect	Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2
Smarmellato
SoC Security	LAMBDA: LLM-Assisted Malicious Bug Detection and Analysis in Hardware Designs
SOC Test	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks Persistent High-Bandwidth IJTAG Data Delivery
software-based self-tests	FSWGEN: a Device-tree Specification driven System-Level Test workload generator
software-hardware co-design	Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
SORT	The Role SLT Plays at Intel
Speed Binning	Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction
Speed Monitors	Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction
speed-up	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG
Spiking Neural Network	Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks
Spiking neural networks	Wafer Map Pattern Recognition using Ternary Spiking Neural Network
spread-spectrum clock generator PLL
SSN	Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks Persistent High-Bandwidth IJTAG Data Delivery In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs Implementation and Optimization of High-Bandwidth IJTAG for Enhanced Test Time Reduction in Complex SoCs
Stability	Ultra dense SRAM Cell Test Challenges
staggered Clocking	Enhancing scan coverage in mixed signal designs by clock and reset manipulation during testing
Standard Test Interface Language	Test Technology Standards Committee Overview & IEEE Std 1450 (STIL) Updates
Standards	Test Access and Instruments Control - IEEE Std Families 1149 and 1687
State Element Identification	An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
Static Random-Access Memory (SRAM)	Scan Strategies for High Quality Latch Array Testing Scan Strategies for High Quality Latch Array Testing
stochastic delay measurement	High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops
Streaming Fabric	Test Pattern Aware Streaming Fabric-based Scan Test Methodology Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Streaming Scan Network	Persistent High-Bandwidth IJTAG Data Delivery Implementation and Optimization of High-Bandwidth IJTAG for Enhanced Test Time Reduction in Complex SoCs
Stress coverage	Stress Aware Quiescent Current Test Optimization
Stress time	Stress Aware Quiescent Current Test Optimization
Structural test	Combined Array and ADC Structural Test for RRAM-based Multiply-and-accumulate Circuits
Structural Testing	Structural Testing on SLT Platform with HSAT IP & High-Speed I/O Access
stuck-at fault (SAF)	Scan Strategies for High Quality Latch Array Testing Scan Strategies for High Quality Latch Array Testing
stuck-at faults	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation
Support Vector Regression (SVR)	Machine Learning Assisted Vmin Prediction
synthetic data	Wafer Map Pattern Recognition for Multisite Probe with Synthetic Data Augmented Training
System Level Test	Thermal Management in System Level Test: Analysis of existing solutions and an introduction to advanced liquid cooled memory solutions
System Level Test (SLT)	Structural Testing on SLT Platform with HSAT IP & High-Speed I/O Access
System Test	The Role SLT Plays at Intel
System Validation	Why is Rigorous PCIe LTSSM Testing is Key to Robust and Reliable Systems?
System-Level test	System-Level Test techniques for Automotive SoCs Assessment of System-Level Test programs in Automotive SoCs A Novel Tester-Based Approach for Functional Testing of Hardware Timers
system-level-test	FSWGEN: a Device-tree Specification driven System-Level Test workload generator
System-on-Chip (SOC)	Test Pattern Aware Streaming Fabric-based Scan Test Methodology Test Pattern Aware Streaming Fabric-based Scan Test Methodology
system-on-wafer	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications
SystemVerilog Assertion (SVA)	LAMBDA: LLM-Assisted Malicious Bug Detection and Analysis in Hardware Designs
T
Tabular Foundation Models	Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction
TAP	Autonomously access 1687 instruments with Controllable ScanRegisters and ScanMuxes at top level with AccessLink
technical issue
Technoprobe	Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Temperature	Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
Tensor Core	Early Reliability Estimation in Hardware Accelerators through an Improved Colored Petri Net Approach
Test	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges Ultra dense SRAM Cell Test Challenges Hierarchical Test Using Running MISR Signatures Origen Based Test and Validation Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation IEEE P1450.6.2: Core Test Language (CTL) for Memories An update to the existing standard Multi-die package and chiplet test applications
Test Benchmark	CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Test Bin	Test Bin Entitlement: Yield Outlier Detection using Die Area and LLM based Bin-Grouping
Test Bus	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
test completeness	Consistency verification between the iJTAG network and its ICL description with optimized simulation time, ease of debuggability and test completeness
Test compression setup	Automated Selection of Optimal EDT Input Configuration
Test Cost	Structural Testing on SLT Platform with HSAT IP & High-Speed I/O Access
test coverage	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
Test Data Analytics	IEA-Plugin: An AI Agent Reasoner for Test Data Analytics
Test data compression	Automated Selection of Optimal EDT Input Configuration
test data volume	HPC AI Processors -- ATE-related challenges & directions
Test Generation	Teaching Llamas to Test: A Language-Based Approach
Test Generation and Simulation	Resurgence in Advanced ATPG Techniques for High-Performance Designs
Test Inerface	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE)
test methodology	Assessing Long-Term Reliability through Accelerated Aging Stress Tests on a On-chip Quality and Reliability Platform : A Band Gap Reference case study
Test metrics	IC-PEPR: PEPR Testing Goes Intra-Cell
Test pattern generation	Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
Test Pin	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Test Point Insertion	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
Test Points	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
test quality SDC	HPC AI Processors -- ATE-related challenges & directions
Test Selection	STARTS: Simulation Traits Assisted Random Test Selection for Multiprocessor Verification
Test Standards	Test Access and Instruments Control - IEEE Std Families 1149 and 1687
test time	HPC AI Processors -- ATE-related challenges & directions
test time optimization	Dynamic SCAN Shift in High Volume Manufacturing Testing for Test Time Optimization
Test Time Reduction	Persistent High-Bandwidth IJTAG Data Delivery
Testability	LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Testability and interoperability	Test Technology Standards Committee Overview & IEEE Std 1450 (STIL) Updates
tester on a probe card	Breaking the Memory Wall: Wafer-Level Test Strategies for Heterogeneous Integration
Testing	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution FeTest: Testing of FeFET-Based Memory Arrays
Testmethod	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE)
Thermal	New ATE needs for the Era of Advanced Packaging and Heterogeneous Integration
Thermal management	Thermal Management in System Level Test: Analysis of existing solutions and an introduction to advanced liquid cooled memory solutions
tie learning	Hybrid Static Learning for ATPG
Timing Analysis	Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption
Timing exception paths	Precise Approach to ATPG: Handling Timing Exceptions for Better Small Delay Defect Coverage
Timing-aware	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Timing-aware ATPG	Precise Approach to ATPG: Handling Timing Exceptions for Better Small Delay Defect Coverage
timing-based	Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2
timing-critical	DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Timings	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
toggle coverage	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs
TPI	TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Transfer Learning	Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
Transfer Matrix Method	Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
Transient Fault	A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
transition delay fault (TDF)	Scan Strategies for High Quality Latch Array Testing Scan Strategies for High Quality Latch Array Testing
transition delay faults	Exploiting the correlation with traditional fault models to speed-up cell-aware ATPG Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation
Transition Fault	NeuralTPG: A GPU-Accelerated Neural Twin-Based Test Pattern Generation Framework for Transition Delay Faults in Safety-Critical Applications
transition faults	Functional Logic Diagnosis with Observation Points on Next-State Variables
U
UDFM	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs Shifting-left Zero Defect Scan Test Development to Launch Automotive PPM-ready products
Unconstrained Path	Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up
UVM	AMBA Qchannel based power management VIP for Efficient low power validation
V
Validation	Origen Based Test and Validation
Vcell method	A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
Vector Network Analyzer (VNA)	5G RF Test Interface Diagnosis in Automatic Test Equipment (ATE) 5G FR2 Test Interface Diagnosis in Automatic Test Equipment (ATE)
Verification	Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution
Verification IP (VIP)	AMBA Qchannel based power management VIP for Efficient low power validation
Vision Transformer (ViT)	FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks
VLSI	Shifting-left Zero Defect Scan Test Development to Launch Automotive PPM-ready products
VLV	Full enablement of Very Low Voltage testing to deliver Zero Defect Quality automotive products
Vmin	Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up Machine Learning Assisted Vmin Prediction
Voltage Deviation	Optimizing Sensing Point Placement for High-Multi-Site Testing on Device Interface Boards
Voltage Droop	TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption
Voltage Fault Injection (VFI)	MUX-based Polymorphic Registers and FSMs to Protect Against Non-invasive Voltage Fault Injection Attacks
Voltage Regulators
Voltage stress	Stress Aware Quiescent Current Test Optimization
W
wafer bonding	Breaking the Memory Wall: Wafer-Level Test Strategies for Heterogeneous Integration
Wafer map pattern recognition	Wafer Map Pattern Recognition using Ternary Spiking Neural Network Wafer Map Pattern Recognition for Multisite Probe with Synthetic Data Augmented Training
wafer test	Breaking the Memory Wall: Wafer-Level Test Strategies for Heterogeneous Integration
wafer-level integration	A Novel Omnidirectional 3D Test Access Architecture for Future System-on-Wafer (SoW) Applications
Wafer-Level Testing	High performances PIC probing using high-accuracy positioning flexures, ultra-short and ultra-fine pitch probes and FAU integration
wafer-to-wafer	Breaking the Memory Wall: Wafer-Level Test Strategies for Heterogeneous Integration
waveform generation	Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
Waveguide to microstrip-line transition	Push-on mating 57- to 81-GHz mm-Wave interface with high repeatability for ATE application
weak and strong non-robust propagation conditions
Weight Permutation	FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks
Y
Yield	Test Bin Entitlement: Yield Outlier Detection using Die Area and LLM based Bin-Grouping
Yield Analysis and Optimization	Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
yield enhancement	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects DMA Burst Mode Fault Detection: Custom MBIST Strategies for Comprehensive Testing
Z
Zero Defect Quality	Full enablement of Very Low Voltage testing to deliver Zero Defect Quality automotive products
zero defects	LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Patterns Generation for Zero Defect Automotive Designs

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