ABSTRACT. Diagnosis of scan chain defects is the established methodology for improving semiconductor manufacturing yield, throughout the production cycle. Diagnosis resolution of a single scan cell per defect is the best possible result. With increased complexity and emergence of new production technologies, like backside power, we need to improve diagnosis callout and provide visibility on transistor level. Chain Cell-Aware Diagnosis (CCAD) is presented for enhancing scan chain diagnosis resolution with cell aware information. CCAD allows to isolate defects in control signals internal to cells. Volume benchmarks and silicon data present suspect area improvements that will allow for faster physical failure analysis.

ABSTRACT. This paper will present the motivation, need, and details of on-going research on Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM and targeted scan stress patterns generation to continue achieving zero defects automotives designs.

ABSTRACT. Cell-aware diagnostics identify Front-End-Of-Line (FEOL) defects in standard cells, aiding Physical Failure Analysis (PFA) and enhancing root-cause analysis. Our findings show that cell-aware diagnostics often reduce suspect areas to under 1% of the total cell area. Given the significant space cells occupy, cell faults can be a major failure mechanism. These benefits led us to create a high-volume manufacturing-friendly scan diagnostics infrastructure using cell-aware diagnostics. We present data-driven solutions for implementing and maintaining this infrastructure. We also include the results of six PFA samples, which validate the FEOL defects across four designs and three technology nodes, yielding six successful results.

ABSTRACT. Ferroelectric Field-Effect Transistors (FeFETs) are promising candidates for non-volatile memory (NVM) due to their high speed and low leakage. However, unique defects in FeFETs, such as Threshold Voltage Shifting (TVS), challenge conventional testing methods. To address this, the Device-aware Test (DAT) approach models defective devices by integrating defect impacts into electrical parameters, calibrated with measurement data. Fault analysis using defect injection and circuit-level simulation identifies realistic fault models. Tailored March tests and Design-for-Test (DfT) solutions are then proposed to detect these defects effectively, advancing FeFET testing methodologies.

ABSTRACT. Redundant elements in memory are used to enhance the manufacturing yield of silicon devices. Although redundant elements allocated during manufacturing tests are fully tested, unallocated elements remain untested. To increase reliability, all redundant elements must be tested during manufacturing. This paper presents the hardware architecture and manufacturing test flow required to systematically test all redundant row elements and permanently identify defective ones. This ensures that only reliable unallocated spare elements remain available for in-system repair. Experimental results show that the proposed solution can be integrated into existing memory built-in self-test solutions with minimal impact on area and test time.

ABSTRACT. A fault list analysis methodology is proposed to determine how many Cell-Aware Test (CAT) defects can be detected using test patterns generated targeting other fault models, including stuck-at faults (SAFs), transition-delay faults (TDFs), and small-delay defects (SDDs). Our analysis reveals that a proper ordering in pattern generation can drastically accelerate the test process. We evaluated our approach on some benchmark circuits, including a RISC-V core, synthesized using an industrial technology library. We demonstrated an innovative method to optimize CAT pattern generation by means of preliminary static fault list analysis, resulting in automatic test pattern generation runtime reduction of up to 85% for static and 45% for dynamic CAT defects.

ABSTRACT. Increasing silicon photonic integrated circuit (PIC) complexity demands robust Design-for-Test (DfT) strategies for reliability against manufacturing/operational variations. We propose an adaptable DfT methodology for large-scale PICs using physics-informed hypergraph partitioning. It leverages hypergraph weighting derived from process sensitivities (e.g., etch, doping) and operational drifts (e.g., thermal, injection), quantified via foundry data/TMM simulations, assigning risk to devices (nodes) and interconnects (hyperedges). Extending beyond bipartitioning, k-way partitioning enables finer sub-network isolation and targeted test access, crucial for vulnerability localization in complex PICs (e.g., rings, MZIs). Demonstrations show this weighted method significantly improves risk coverage and sub-network localization versus unweighted approaches with moderate overhead, enhancing yield/reliability.

ABSTRACT. As process geometry shrinks, the complexity of transistors in electrical devices has increased exponentially. Silicon devices manufactured with these new processes are used in safety-sensitive products, where reliability is crucial. To ensure high quality, advanced test patterns and scan diagnosis techniques are required. This paper presents a new methodology for 3nm and 4nm nodes, which improves screening of defective parts during production test and enhances physical failure analysis resolution of global control signals over previous techniques. Experimental results demonstrate the effectiveness of this approach in uncovering real systematic defects encountered in silicon production at Samsung Foundry.

ABSTRACT. Fan-out wafer-level packaging enables heterogeneous chiplet integration via Cu pillars and Redistribution Layers (RDL). However, defects such as opens, shorts, and coupling present significant reliability challenges. Testing for these defects, particularly shorts in many-chiplet designs, is time-consuming with Automated Test Equipment. We propose an advanced routing-aware testing framework that leverages the RDL routing information to target realistic shorts and coupling defects. By physically partitioning interconnects into regions, we enable test scheduling and leverage shared test pattern generators for launching test patterns and capturing responses to reduce test time and area overhead without compromising fault coverage. The framework’s effectiveness is demonstrated on four many-chiplet packages with varying configurations of chiplet-to-chiplet connectivity.

ABSTRACT. Software-based fault injection (FI) demonstrates low efficiency due to low simulation throughput while hardware-based FI presents challenges related to complexity of setup and limited scalability. To address this, a general purpose framework, Genshin, is proposed for rapid reliability analysis, which works with Design Under Test (DUT) chips and supports FI control based on scan chain (SC). An integrated programmable logic allows for custom FI pattern definitions. Furthermore, an architecturally correct execution (ACE) analysis generates pruned fault tables. In Genshin, the SC logic achieves 3,802-65,388 cycles/FI in different DUTs. Furthermore, the pruned fault tables achieve fault reduction rates up to 83.21%.

ABSTRACT. We proposed a novel probabilistic fault propagation method for circuit of the register transfer level (RTL), enabling early-stage fault injection analysis. For the proposed method, we formulate and compute the probability of fault propagating to the output of an RTL operator based on the input logic patterns. The proposed method can have a speedup of 35X to 158X faster than a traditional fault injection method, while achieving an average of 94.94\% accuracy in the prediction of propagation of an injected fault. Hence, the proposed method can be applied to select high-quality fault candidates and to quickly evaluate the reliability of different design choices.

ABSTRACT. Resistive Random Access Memory (RRAM)-based analog in-memory computing (IMC) AI accelerators offer significant advantages over digital accelerators, including lower power consumption, reduced data movement, and computational efficiency. However, their deployment in safety-critical and edge applications is challenging due to their hardware non-idealities such as programming error, conductance drift, and read noise, which degrade the inference accuracy of the neural networks (NNs). Existing works, including noise injection during training and activation function modifications, provides limited fault-tolerance. Therefore, in this work, we propose a fault-tolerant activation function with architectural optimization that enhances fault-tolerance with minimal hardware and NN architectural changes.