Ramanath Dharmavaram (Master 1991, Bachelor 1987) is working as Sr. Principal designer in Logic Library Group, NXP Bangalore, India. His main areas of interest are improving Power, Performance, and Area for SoC designs, DFM Yield improvements through Cell-aware UDFM and optimizing Synchronizers and other crucial Standard cell library cells. Investigates into Silicon failures and work in the root cause of it.  Ramanath has over 30+ years of experience in the semiconductor industry in various fields from synthesis to TO-ready data. He completed Masters from IIT Kanpur in 1991 in Micro-Electronics specialization and Bachelors from JNTU Anantapur, AP, India in 1987.