Senior Design Engineer with 8+ years of experience in Digital and Analog VLSI, specializing in Standard Cell Layout, Characterization, and EDA view generation and validation. Proven track record in silicon debug, failure analysis, and automation. Worked as Project Lead. Championed the adoption and exploration of FinFET technology, leveraging its potential to drive innovation and growth. Represented NXP at global forums (DAC, ITC, DVcon, Cadence-Live, Ansys-Ideas, Siemens-DFT) and hold multiple patents along with international publications.