Yu Tin graduated with a degree in Information System Engineering from Campbell University in 2008. With 17 years of experience at Intel Corporation, Yu Tin has honed expertise in design software development, ATPG test writing, and leading major projects, particularly within the INTEL Scan XEON-D and Xeon Phi domains. Her proficiency in Scan Design for Testability (DFT) and translation flow has led to significant contributions in both pre and post-silicon validation, as well as Scan content enabling and debugging activities. Yu Tin's career is marked by a strong ability to drive technological advancements and ensure product reliability through strategic project leadership and innovative problem-solving. Her contributions have consistently delivered results that ensure product quality and accelerate time to market