Saeid Karimpour is a Ph.D. candidate in Electrical Engineering at Iowa State University working at the intersection of analog/mixed-signal IC design, reliability sensing, and embedded systems. Under Prof. Degang Chen, he has designed and evaluated multiple data converters (SAR and variants), on-chip aging/HCI sensors, and layout algorithms that suppress high-order spatial gradients. His recent projects include soft-defect detection in PLLs, digital-only/transient-only trimming strategies, and FPGA-based testbenches for post-silicon characterization. Saeid’s tapeout experience covers complete flows—from schematic capture and verification through layout, sign-off, fabrication, and bring-up—in TSMC 180 nm, complemented by EM/circuit co-design and measurement. Earlier, he served as a senior embedded hardware/software engineer for four years, delivering MCU/FPGA platforms, low-noise analog front-ends, and production-ready firmware. His research interests include low-power analog front-ends, high-resolution data conversion, reliability/aging monitors (BTI/HCI/EM), RF/PLL/synthesizers, and cross-layer methods that unify circuits, signal processing, and measurement automation.