TTEP Tutorial by Prof. Li-C. Wang (UC Santa Barbara) 

The emerge of Large Language Model (LLM) have significantly impacted our view for applying Machine Learning (ML) in semiconductor test. Recent LLMs include Codex focusing on code generation and InstructGPT for capturing user intent. Their successor, ChatGPT, had demonstrated remarkable performance for engaging in dialog on a wide variety of topics, answering questions, and generating code. With these recent LLM technological developments, this tutorial provides an integrated view of how to apply LLM in semiconductor test data analytics. In particular, we will cover introductory materials for LLMs and share our experience of leveraging the power of LLMs to build an AI Agent in semiconductor test domain. We will discuss a new paradigm called Decision-Support ML (DSML). In our domain, DSML is applied in an iterative exploration process for an engineer to learning knowledge from data. We will discuss common test data analytics practices as well as the latest LLM technologies and how they fit into our DSML view to build an end-to-end LLM-Assisted AI solution. Industrial case studies will be provided to illustrate the concepts taught in this tutorial.

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial1

TTEP Tutorial by Mark Tehranipoor (University of Florida) & Farimah Farahmandi (University of Florida)

As modern system-on-chip (SoC) designs grow increasingly complex, ensuring security throughout the silicon development lifecycle has become a critical yet challenging task. Traditional verification techniques often lack security awareness and remain time-consuming, costly, and prone to human error, necessitating a shift toward automation. This talk explores LLM security verification as a transformative approach, leveraging generative AI to automate vulnerability detection, enhance formal verification, and strengthen threat modeling. By integrating AI into security workflows, engineers can significantly reduce development costs while improving the accuracy and efficiency of security validation.

The discussion will also explore the future outlook of AI-driven security solutions, offering practical strategies for engineers and practitioners to reinforce hardware security at various design and verification stages. Additionally, the talk will highlight open research challenges and opportunities for academics, paving the way for future advancements in AI-powered security verification.

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial2

TTEP Tutorial by Lee Harrison (Siemens EDA) & Peter Orlando (Siemens EDA)

In this tutorial, we will proceed to give an overview of the exciting field of AI and HPC. It will cover the critical and special characteristics and the architecture of the popular AI chips. Next we will summarize the features of the AI chips from design-for-test (DFT) perspective and introduce the DFT technologies that can help testing AI chips. We will also look at how the shift to 2.5D and 3D including Chiplet development is changing the industry and the adding new challenges for the DFT community Finally, we will present a few case studies on how DFT is implemented in the real AI chips. We will also present some of the functional monitoring techniques that are available today. An overall architecture showing how functional monitoring can be implemented and how the monitor data can be used to manage in-life capabilities. Finally, we will present a few case studies on how DFT is implemented in the real AI chips.

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial3

TTEP Tutorial by Paolo Bernardi (Politecnico di Torino)

Since the inception of IC design in the mid-1960s, IC test has been an integral part of the manufacturing process. Initially, tests were of the Functional nature of either randomly generated or created from verification suites. But as chips got larger, testing required a more targeted approach, one that needed to be easily replicated from one design to another. This led to the invention of Structural methods like scan, which made designs combinational and simplified the test generation process. After almost 50 years, the testing scenario evolved just slightly, following technology trends currently led by the complexity of the circuits under test and the field of use (i.e., Automotive). Structural methods are still dominant, at least during the manufacturing test process, but Functional techniques are now recognized to be: (i) Useful to complement structural techniques during the manufacturing test process, such as System Level Test. (ii) Able to mitigate thermal issues that may originate during stress phases like along Burn-In, thus enabling test data collection during this phase. (iii) Very helpful along with the useful life of the components in the mission field, to run a not destructive self-test and also able to capture and store information, opening possibilities for Silicon Lifetime Management (SLM). The talk will provide basic and practical information about some today-relevant functional techniques in the field of Software-Based Self-Test (SBST), Burn-In Functional Stress/Test (TDBI), and System-Level Test (SLT). Automotive chip case studies from STMicroelectronics will be illustrated.

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial4

TTEP Tutorial by Drew Walton (Microsoft) & Yogesh Varma (Intel)

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial5

TTEP Tutorial by Stephen Sunter (Siemens EDA)

This tutorial explores systematic analog and mixed-signal design-for-test, including analog fault/defect simulation. We will review widely-used basic DfT techniques, fault simulation, IEEE 1149.1/4/6/7, 1687, and ISO 26262 metrics, then BIST for ADC/DAC, PLL, SerDes/DDR, and random analog. Essential principles of practical analog BIST are presented, then practical DfT techniques, from quicker analog defect simulation, to DfT that emphasizes simplicity, diagnosis, reuse, and automation. Detailed summaries of the Analog Defect Coverage and Analog Test Access standards (IEEE P2427, P1687.2) are included, as they approach completion thanks to the effort of many people since 2014. The tutorial concludes with an introduction to digital scan-based DfT that enables ATPG for near-instantaneous high-coverage structural testing of analog circuits.

More Information: http://ttep.tttc-events.org/ttep/tutorials.html#tutorial6