Functional Coverage Sign-off Assisted by Formal Connectivity

Asheque Mohammad Zaidi and Muhammad Ul Haque Khan

Automatic Insertion of a Safety Mechanism for Registers in RTL-Modules

Holger Busch and Jonathan Ross

Securing SoC: a Scalable Hardware Security Verification Methodology

Muhammad Abdullah Al Faisal, Jaimini Nagar, Thorsten Dworzak, Sebastian Simon, Ulrich Heinkel and Djones Lettnin

OpenCar: a SysML V2 Modeling Framework for Early Analysis of BoardNet Architectures

Sebastian Post, Johannes Koch, Aida Bevrnja and Christoph Grimm

Analogous Alignments: Digital "Formally" Meets Analog

Hansa Mohanty and Deepak Gadde

A Roundtrip: from System Requirements to Circuit Variations and Back

Sören Kwasigroch, Nicolas Theobald, Johannes Koch and Christoph Grimm

A UVM Testbench for Checking the Global Convergence of Analog/Mixed-Signal Systems: an Adaptive Decision-Feedback Equalizer Example

Jaeha Kim

Libtcg -- Accurate Lifting of Executable Code Using QEMU

Anton Johansson and Alessandro Di Federico

Harnessing Regenerative AI and Machine Learning for Efficient Fault Simulation

Himanshu Vishwakarma, Lakshya Miglani and Gopi Srinivas Deepala

Retention Sufficiency Validation for Optimizing State Retention Cells in Low Power Design

Nitesh Kalwani and Mateus Silva

Enabling True System-Level, Mixed-Signal Emulation

Paul Wright, Nimay Shah, Pranav Dhayagude, Raj Mitra and Adam Sherer

Design and Verification of SEE-Tolerant ASICs at CERN: Methodologies and Challenges

Adithya Pulli, Matteo Lupi, Stefano Esposito, Simone Scarfi, Szymon Kulis and Xavier Llopart Cudie

Auto Generation Is the Key to Rapid Integration to UPF-like UPVM Libraries for Unified Power Verification

Gopi Srinivas Deepala, Lakshay Miglani, Himanshu Vishwakarma and Priyanka Gharat

Unleash the Power of Formal for Post Silicon Debugging

Jan Hahlbeck and Shreya Upadhyay

Efficient Workflow using Verilator for Processor Benchmarking in SystemC-based Automotive SoC Platforms

Johannes Sanwald, Andreas Mauderer, Mohammad Badawi, Javier Castillo, Jan-Hendrik Oetjens, Andreas Wieferink, Maryam Keeley and Tim Kogel

A New Approach to Integrated AI into Analog/Mixed-Signal Verification Workflow

Long Hoang, Emanuel Popovici and George Duffy

Automated Design Behaviour Extraction of SoC Interconnects Using Formal Property Verification

Jan Hahlbeck, Chandana Guddenahalli Palaksha and Görschwin Fey

A Novel Approach for HW/SW Co-Verification: Leveraging PSS to Orchestrate UVM and C Tests

Tom Fitzpatrick, Wael Mahmoud, Vishal Baskar and Mohamed Nafea

Functional Verification Using C Model: DPI-C VS Static Value Tables

Djordje Velickovic and Katarina Bozinovic

Single Source Library for High-Level Modelling and Hardware Synthesis

Mikhail Moiseev and Nanda Kalavai

Addressing Fixed-Point Format Issues in FPGA Prototyping with an Open-Source Framework

Vishal Chovatiya, Gabriel Rutsch and Wolfgang Ecker

Heartbeat Based Early Detection of Hang Issues

Tejbal Prasad and Vinaykumar Kori

Enable Reuse of SystemVerilog Verification IPs in Cocotb/Pyuvm

Yilou Wang, Thorsten Dworzak and Johannes Grinschgl

Deployment of Containerized Simulations in an API-Driven Distributed Infrastructure

Tim Kraus and Axel Sauer

Safety Analysis of Automated Driving Platforms Using Digital Twin Simulation and Runtime Monitoring

Tasneem A. Awaad, Hanya A. Elged, Mohamed A. Abu-Bakr, Sama Y. Fathy, Sara H. Ahmed, Mohamed Abdelsalam and M. Watheq El-Kharashi

Scalable and Mergeable Functional Coverage Flow for Highly Configurable IP Signoff and Specific Customer Deliveries

Fryderyk Koziol and Sebastian Cieslak

CPAS : Cocotb Power Aware Simulation Framework

Ahmed Alsawi, Liam O'Reilly and Evin Hughes

Virtual Prototyping Framework for Pixel Detector Electronics in High Energy Physics

Francesco Enrico Brambilla, Davide Ceresa, Jashandeep Dhaliwal, Stefano Esposito, Kostas Kloukinas and Jeffrey Prinzie

Enhanced VLSI Assertion Generation: Conforming to High-Level Specifications and Reducing LLM Hallucinations with RAG

Hafiz Abdul Quddus, Md Sanowar Hossain, Ziya Cevahir, Alexander Jesser and Md Nur Amin

UVM Portable Stimulus: Synchronized Multi-Stream Parallel-State Scenario in UVM

Ahmed Allam

Verifying Non-Friendly Formal Verification Designs: Can We Start Earlier?

Bryan Olmos, Daniel Gerl, Aman Kumar and Djones Lettnin

Trustworthiness Evaluation of Deep Learning Accelerators Using UVM-Based Verification with Error Injection

Randa Aboudeif, Tasneem A. Awaad, Mohamed Abdelsalam and Yehea Ismail

Reliable and Real-Time Anomaly Detection for Safety-Relevant Systems

Hagen Heermann, Johannes Koch and Christoph Grimm

Enhancing Automotive Security and Safety Through CSEv2.0 Test Vector Validation with Synopsys MIPI CSI VIP

Venkata Naga Srideepti Pisipati and Andrew Elias

Simulation Phases

Mark Burton, Mark Glasser, Karsten Einwich and Ramzi Karoui

Harnessing the Strength of Statistics and Visualization in Verification

Olivera Stojanovic and Uri Feigin

Streamline PCIe 6.0 Switch Design with Effective Verification Strategies

Nicolas Dai, Deep Mehta and Meghvendra Rathod

Making Code Generation Favourable

Tero Isännäinen

A Novel Approach in Proving Unreachable Paths in Hardware-Dependent Software

Bryan Daniel Olmos Suquillo, Wolfgang Kunz and Djones Lettnin

Improved Performance of Constraints

Milos Pericic