A UVM testbench capable of verifying the global convergence property of an analog/mixed-signal system is presented. For example, a sign-sign LMS adaptation algorithm for a decision-feedback equalizer (DFE) may converge to a false final state depending on the initial state. To detect the existence of such false final states, the testbench launches a sequence of trial runs, each starting from a random, unvisited initial state, until all possible states of the system are tried or traversed, or a problematic initial state is found. The simulation is run entirely in SystemVerilog by modeling the analog components of the high-speed wireline transceiver using the XMODEL primitives. To generate a sequence of trial runs based on the previous results and evaluate the termination conditions, the testbench utilizes a shared state coverage database and a global UVM event. The experimental results show that the testbench swiftly uncovers the false final states caused by high channel loss or insufficient constraints, and successfully confirms the global convergence of the adaptation loop when no such issues exist.