Implementing algorithms on FPGAs is vital for designing, developing, and prototyping algorithms in various fields. FPGAs offer improved performance compared to software implementations and the ability to test algorithms in real-world conditions. However, FPGAs have limited hardware resources and algorithms often use resource-intensive floating-point arithmetic. To address this issue, algorithm designers switch to fixed-point arithmetic, which is faster and requires fewer resources. However, switching to a fixed-point format can lead to range violation and loss of precision. Therefore, it is crucial to validate and verify the correctness of algorithms after conversion to the fixed-point format. Moreover, debugging algorithms that use fixed-point arithmetic during emulation can be challenging, particularly for hardware-in-loop or customer-design-in setups. This paper is an extension of a lightweight, open-source and tool-agnostic framework to simplify the process of algorithm implementation and verification that involves fixed-point datatypes and arithmetic onto FPGA. Additionally, the paper systematically and effectively addresses challenges related to utilizing a fixed-point format, including precision loss, range violations (overflow/underflow), and algorithm debugging during simulation and emulation. The presented method is demonstrated with the effective development of the power conversion circuit algorithm.