Power aware design and verification are important requirements of the modern system on chip flow. With the proliferation of free and open-source design and verification tools, power aware simulation is still only supported with commercial simulators. To enable power aware simulation with an open-source toolchain, a framework is introduced to enable design and verification engineers to specify power intent and run power aware simulation using Python and Cocotb. The framework implements power aware specifications with a Python frontend using popular and easy language to define and drive power aware intent. The framework also integrates with Yosys to extract design information and Cocotb to implement power aware semantics.