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![]() Title:Automated Design Behaviour Extraction of SoC Interconnects Using Formal Property Verification Conference:DVConEU 2024 Tags:Behaviour Extraction, Formal Verification, Interconnect Verification and SoC Security Abstract: This paper describes an algorithm to extract the design behaviour of SoC interconnect modules by using formal traces in an flow automated flow. The main purpose of this flow is to unveil undocumented and unintended design behaviour which might harm security relevant aspects. The extracted results can be checked against the project specifications and requirements. By means of an example design the algorithm gets demonstrated. Automated Design Behaviour Extraction of SoC Interconnects Using Formal Property Verification ![]() Automated Design Behaviour Extraction of SoC Interconnects Using Formal Property Verification | ||||
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