The radiation environment of the detectors at the CERN Large Hadron Collider (LHC) presents an unprecedented challenge for electronic system design. Since the early 1990s, CERN has been developing custom Application-Specific Integrated Circuits (ASICs) tailored to the unique requirements of LHC experiments. As ASIC complexity increases, the tolerance to Single Event Effects (SEE) emerges as a significant design and verification challenge. This article discusses the distinctive challenges in designing SEE-tolerant ASICs for high-energy physics (HEP) experiments. We provide an overview of methodologies used for the design and verification of radiation-tolerant ASICs at CERN, along with examples of SEE vulnerabilities discovered during verification.