Abstract — Constraints in SystemVerilog language are useful for randomization. When there are connections between randomized registers, parameters, and variables, then constraints could be used for randomizing everything together. In a larger project, the number of connections can grow and expand, resulting in complex randomized test scenarios. In those cases, constraints should be written as good as possible, and their performance should be tested. In this paper, a few useful techniques will be covered for improving performance of constraints.