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Title:A Novel Approach for HW/SW Co-Verification: Leveraging PSS to Orchestrate UVM and C Tests
Conference:DVConEU 2024
Tags:Constrained-Random, HW/SW Co-Verification, Portable Stimulus, siemens pss and UVM
Abstract:
The complexity of System on Chips (SoCs) continues to grow rapidly. Accordingly, new standards and methodologies are introduced to overcome these verification challenges. The Portable Test and Stimulus Standard (PSS) from Accellera is one of the standard examples used to pursue such challenges. In this paper we will show a methodology to use PSS to orchestrate the process of HW/SW co-verification by driving UVM and C tests and controlling the interaction between them.
A Novel Approach for HW/SW Co-Verification: Leveraging PSS to Orchestrate UVM and C Tests
A Novel Approach for HW/SW Co-Verification: Leveraging PSS to Orchestrate UVM and C Tests
