UVM becomes the state of art methodology in the area of digital verification. While the sequence is playing great role in UVM verification, it lacks power of scenarios in running multiple sequences in complex random manner. There was an attempt to include scenarios in UVM but it applies one to one mapping, one sequence runs one scenario. In this paper, a novel approach is developed to use multi-stream multi state scenario adding more complexity and portability in SoC verification in order to increase test coverage.