This paper shows how we adopt formal property verification to accelerate post-silicon debugging. By using simple cover properties rather than a traditional functional simulation based testbench we take advantage of the full state space exploration of formal tools. The used flow can be applied even by new adopters of formal verification as methodology as just a subset of skills is required. For most of the bugs a single cover property is sufficient for re-creation and debugging. By means of an example we show case that we were able to re-create a hard to find corner case deadlock which escaped the pre-silicon verification. It takes the formal tool just a few minutes of execution time to provide a formal trace of the deadlock.