The purpose of this paper is to address PCIe 6.0 Switch design verification challenges by providing different verification strategies and highlighting the performance metric criteria that aid in the closure of switch design verification. PCIe 6.0 Switch must translate between Flit Mode (FM) and Non-Flit Mode (NFM) Transaction Layer Packet (TLP) formats when the Ingress Port and Egress Port are in different speed or modes. Applying newly introduced translation rules, routing logic in switch design may add performance penalty that conventional data integration testing cannot detect. Verifying PCIe 6.0 switch design demands interoperability verification with FM mode and NFM mode traffic, Reserved TLP verification in FM mode traffic and Performance testing.