This paper proposes an approach to efficiently evaluate processor cores in automotive SoC architectures as part of the design space exploration process, which overcomes obstacles such as limited availability of processor models and inaccurate interface timing, providing an efficient solution for evaluating processor cores from different vendors. The approach encompasses translation of processor RTL into a SystemC model via Verilator, which is then integrated into an easily customizable SystemC platform. A case study demonstrates this, by integrating the verilated open-source RISC-V core CVA6 into a system-level automotive SoC architecture using Synopsys Platform Architect. It shows that accurate performance evaluation with minimal cycle-count deviation and easy integration is achieved.