Speaker: Adit Singh (Auburn University)

Abstract: TBD

Speakers' bios:

Dr. Adit D. Singh is Godbold Endowed Chair Professor of Electrical and Computer Engineering at Auburn University. Before joining Auburn in 1991, he served on the faculty at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. He has held several visiting positions during sabbaticals, including at the University of Tokyo in Japan, the Universities of Freiburg and Potsdam in Germany, the Indian Institutes of Technology, and as Fulbright Awardee at the University Polytechnic of Catalonia in Barcelona, Spain. He has also conducted over 70 tutorials and short courses at conferences, universities and industry worldwide. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He has published over two hundred and fifty research papers and holds international patents that have been licensed to industry. He is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing. He has served as a consultant to many major semiconductor, test and EDA companies around the world. Professor Singh was elected Fellow of IEEE in 2002.

Speakers: Lee Harrison (Siemens EDA), Peter Orlando (Siemens EDA)

Abstract: In this tutorial, we will give an overview of how the use and development of AI is driving the evolution of advanced AI hardware. It will cover the critical and special characteristics and the architecture of the popular AI chips. Next we will summarize the features of the AI chips from design-for-test (DFT) perspective and introduce the DFT technologies that can help testing AI chips. We will also cover how additional monitoring techniques that are available today are addressing the requirements of the AI hardware, developing reliability and resilience. Finally, we will present a few case studies on how DFT is implemented in real AI chips.

Speakers' bios:

Lee Harrison is Automotive IC Test Solutions Manager with Siemens EDA. He has over 20 years of industry experience with Mentor DFT products and has been involved in specifying new test features and methodologies, focusing on Automotive requirements. Lee received his BEng in MicroElectronic Engineering from Brunel University London in 1996 and regularly presents at conferences such as DAC, ITC, VTS, ETS, and DATE.

Peter Orlando is a Technical Marketing Engineer at Siemens EDA.

Speaker: Gang Qu (University of Maryland, College Park)

Abstract: Faults are inevitable in integrated circuit (IC) fabrication due to many factors such as manufacturing process variability. By adding testability features at design time, scan-based design makes test pattern generation, application and evaluation cost-effective to screen out defective ICs. It has become a common design structure for modern chips. However, the unrestrictive and ease of access to the internal states of the circuit under test makes scan chains an exploitable side channel for attacker to steal sensitive information such as cipher key of cryptographic core through in-field testing. In this tutorial, after a brief introduction of scan-based DfT, we will focus on its security vulnerabilities, the attacks based on these vulnerabilities, and corresponding countermeasures. We will also discuss DfT-based solutions to some of the hardware security problems, including digital watermarking, fingerprinting, IC metering, physical unclonable function, and random number generation.

Speakers' bios:

Gang Qu is a professor in the Electrical and Computer Engineering department at the University of Maryland at College Park. He leads the Maryland Embedded Systems and Hardware Security lab and the Wireless Sensor Laboratory. Dr. Qu has made significant contributions to hardware security and trust, co-founded multiple workshops and symposiums in the field, developed a popular hardware security MOOC on Coursera, and is a Fellow of IEEE.

Speakers: Sai Varun Puligilla, Stephen Sunter, Jason Doege, Jonathan Gaudet, Martin Keim (Siemens EDA)

Abstract: This tutorial provides a comprehensive introduction to IEEE 1687 (IJTAG), a standard designed for scalable access to embedded instruments within complex SoCs. It explains how 1687 builds on IEEE 1149.1 boundary scan. In addition, it outlines the emerging extensions P1687 (1687 refresh), P1687.1 and P1687.2. Key concepts such as instrument networks, ICL, and the procedural description framework are highlighted. The tutorial includes the different types of PDL used to describe instrument procedures and test sequences. It emphasizes how IJTAG improves flexibility, reuse, and interoperability across modern test and debug infrastructures.

Speakers' bios:

Sai Varun Puligilla is a Technology Enablement Engineer at Siemens EDA, specializing in DFT methodologies, multi-die architectures, and advanced test automation for modern semiconductor designs. Since joining Siemens in 2023, he has developed high-impact test flows, validated tool interoperability, authored application notes, and supported customers through technical guidance, demos, and training content. He holds an M.S. in Electrical and Computer Engineering from California State University, Fresno.

Steve Sunter graduated from the University of Waterloo in 1978 with a Bachelor of Applied Science in Electrical Engineering. He worked in mixed-signal IC design from 1977 to 1990 at Bell-Northern Research and Nortel. In 1996, he became Engineering Director of mixed-signal DfT at LogicVision, later part of Mentor Graphics and Siemens. Over his career he was granted 30 U.S. patents, authored many papers and book chapters, chaired IEEE working groups and served on multiple program committees. He is a Life Senior Member of IEEE and an Associate Editor of JETTA.

Jason Doege graduated from DeVry Institute of Technology in 1992 with a Bachelor of Science in Electronics Engineering Technology. He is a Product Manager at Siemens EDA, responsible for SiliconInsight products, with 30+ years in Design For Test and Debug. He was a core contributor to IEEE P1500 and P1687 and currently holds roles in multiple IEEE working groups.

Jonathan Gaudet is a Senior Engineering Manager at Siemens EDA, leading the Tessent IJTAG development team. He has contributed to IJTAG and multi-die products since 2008 and is co-inventor of High-Bandwidth IJTAG. He has authored several ITC publications and leads development for Tessent IJTAG.

Dr. Martin Keim joined Mentor Graphics' Silicon Test Solutions group in 2001 and is currently a senior technical marketing engineer. He previously worked as a Test Engineer at Infineon and is active in IEEE P1687 working group and test/failure analysis communities.

Speakers: Li-C. Wang (UC Santa Barbara), Seoyeon Kim (UC Santa Barbara)

Abstract: Large language models (LLMs) and agentic AI systems are rapidly transforming how engineers interact with software, information, and complex workflows. These technologies are beginning to reshape many aspects of semiconductor engineering. This tutorial introduces the foundations of modern LLM technologies and explains how they evolve into goal-oriented AI agents capable of reasoning, tool usage, memory management, and multi-step task execution. The tutorial is designed for semiconductor engineering professionals who want to develop a deeper understanding of why modern LLMs have become so powerful, how agentic AI systems work, and how practical AI agents can now be rapidly prototyped using modern LLM tools and effective context engineering.

Topics covered include:

• Foundations of generative AI and large language models
• Principles behind modern LLM development, including scaling laws, pretraining, supervised fine-tuning (SFT), RLHF, and emergent reasoning capabilities
• In-context learning and context engineering
• Chain-of-thought reasoning and ReAct-style agents
• Tool calling, retrieval-augmented generation (RAG), and memory
• Principles behind modern agentic AI systems

The tutorial emphasizes intuition, engineering perspectives, and practical understanding rather than low-level mathematical derivations. A brief hands-on demonstration is also included to show how modern coding agents and LLM-assisted development tools can now enable rapid prototyping of end-to-end AI agents within only a few hours through effective prompting and context engineering.

Speakers' bios:

Li-C. Wang is a professor at ECE department at University of CA, Santa Barbara. He received PhD in 1996 from University of Texas, Austin, and was previously with Motorola PowerPC Design Center. Starting from 2003, his research has focused on investigating how machine learning could be utilized in design and test flows, where he had published more than 120 papers and supervised 23 PhD theses on topics in this area. Prior to that, his research spanned across multiple topics in EDA and test, including microprocessor test and verification, statistical timing analysis, defect-oriented testing, and SAT solvers. He received 12 Best Paper Awards and 2 Honorable Mentioned Paper Awards from major conferences, including recent best paper awards from ITC. He is the recipient of the 2010 Technical Excellence Award from Semiconductor Research Corporation (SRC) for his research contributions in data mining for test and validation. He is the recipient of the 2017 IEEE-TTTC Bob Madge Innovation Award. He is an IEEE fellow and serve as the General Chair of the International Test Conference (ITC) in 2017, 2018, and 2023.

Speakers: Sandeep Goel (TSMC), Yervant Zorian (Synopsys)

Abstract: Advancements in process technology have enabled the creation of chips with billions of transistors, significantly enhancing power and performance for high-performance computing (HPC) and AI applications. This complexity has spurred the development of various 3D integration and packaging techniques utilizing multi-die/chiplet-based designs. Advanced 3D integration technologies allow for the construction of multi-die systems, each offering specific advantages and trade-offs in terms of performance, application, and cost. Similar to traditional chips, all 3DICs must be rigorously tested for manufacturing defects. This includes Known-Good Die (KGD) testing before stacking, Known-Good-Stack (KGS) testing after stacking, final tests, and system-level tests. Furthermore, given the complexity of the stacking process, in-silicon monitoring solutions are necessary to continuously check silicon health during in-field operation. This tutorial offers an overview of the advanced packaging technologies and explores the associated test flow challenges. An example of how the 3Dblox open standard simplifies the description of a 3D stack, enabling interoperability between EDA tools and allowing various test optimizations, is presented. Additionally, it covers various Design-for-Test (DFT) schemes, sensors/monitors and embedded test & repair solutions to facilitate efficient testing across different packaging configurations.

Speakers' bios:

Dr. Sandeep K Goel is an academician and senior director at Taiwan Semiconductor Manufacturing Company (TSMC), USA. He previously held research and management roles at LSI, Magma Design Automation, and Philips Research. Dr. Goel earned his M.Tech. in VLSI from IIT Delhi in 1999 and his Ph.D. in Electrical and Computer Engineering from the University of Twente in 2005. He has co-authored multiple book chapters, published over 90 conference/journal papers, and holds more than 100 US patents. He received the Most Significant Paper Award at ITC in 2010 and the Distinguished Contributor Award from the IEEE Computer Society in 2022. He is the chair of IEEE Std. P3537 standard for 3Dblox: Chiplet connectivity and physical properties description language. His research focuses on design verification, testing, diagnosis, and defect modeling of 2D/3D SOCs.

Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff at AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, and Editor-in-Chief Emeritus of IEEE Design and Test of Computers. Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous awards; he is a Fellow of IEEE.

Speaker: Adit Singh (Auburn University)

Abstract: This tutorial aims at understanding the effectiveness of functional system level tests (SLTs) as an additional final defect screen before processor SOCs are shipped for assembly. It takes an in-depth look at traditional scan based Stuck-at and TDF tests to understand potential sources of test escapes, and discusses new test generation methodologies such as Cell Aware, Gate Exhaustive, Transistor Stuck-Open, and Timing Aware tests. The tutorial identifies failures that can remain undetected by scan structural tests and require the use of functional SLTs, and suggests strategies to minimize SLTs without impacting defect levels.

Speakers' bios:

Dr. Adit D. Singh is Godbold Endowed Chair Professor of Electrical and Computer Engineering at Auburn University. Before joining Auburn in 1991, he served on the faculty at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. He has held several visiting positions during sabbaticals, including at the University of Tokyo in Japan, the Universities of Freiburg and Potsdam in Germany, the Indian Institutes of Technology, and as Fulbright Awardee at the University Polytechnic of Catalonia in Barcelona, Spain. He has also conducted over 70 tutorials and short courses at conferences, universities and industry worldwide. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He has published over two hundred and fifty research papers and holds international patents that have been licensed to industry. He is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing. He has served as a consultant to many major semiconductor, test and EDA companies around the world. Professor Singh was elected Fellow of IEEE in 2002.

Speakers: Rubin Parekhji, Mudasir Kawoosa (Texas Instruments India)

Abstract: Many semiconductor chip families are characterized by very high volumes and extremely low cost, while being unrelenting on quality in the end application system. There is little headroom in chip area and test cost, which often precludes the direct adoption of well-established DFT and test methods. This tutorial provides an industry perspective on (i) design affordability and test economics, (ii) illustrations of custom methods for DFT and test required to meet challenges due to technology, architecture and end application, and (iii) current gaps in standard methods and how to fix them through customizations and emerging landscapes in EDA and agentic AI.

Speakers' bios:

Rubin Parekhji has been with Texas Instruments (India), Bangalore, since 1996, where he has mentored and led DFT teams on various design and test technology projects across multiple groups, resulting in many DFT and test innovations, and adoption of new test technologies across TI WW. He is a distinguished member of the technical staff. He has published regularly and delivered tutorials at leading conferences, has mentored and partnered on several university projects, has been a visiting faculty member for multiple academic terms, has several issued patents on ideas co-authored with team members, and has been on the editorial board of journals. He has a Ph.D. from Indian Institute of Technology, Bombay, India.

Mudasir Kawoosa is a DFT Architect at Texas Instruments (India) Pvt. Ltd. in Bangalore, with fifteen years of industry experience. As a Senior Member of Technical Staff, he leads the centralized DFT team in Connectivity Business Unit driving transformative changes through innovative test solutions, expert silicon bring-up and widely adopted methodologies. Mudasir has architected DFT and test solutions for over fifteen complex System-on-Chip (SoC) programs. He holds master’s degree in electrical engineering from the Indian Institute of Technology, Madras, has published in several peer reviewed external conferences (and is also prolific in TI internal and other conferences), and holds eleven granted US patents. Through his work, he has established several innovative solutions in DFT, test and silicon debug, for a wide variety of chip architectures across several business units in TI, and continues to influence the EDA DFT roadmap.

Speaker: Li-C. Wang (UC Santa Barbara)

Abstract: Large language models (LLMs) are fundamentally changing how semiconductor test data analytics systems can be designed and deployed. Modern LLMs can generate code, analyze CSV tables, create plots, summarize engineering data, and perform multi-step reasoning. However, reliable semiconductor analytics requires far more than simply connecting an LLM to raw test data.

This tutorial presents a new paradigm for agentic semiconductor test-data analytics based on workflow grounding, context engineering, and analytic-ready tables (ARTs). The tutorial introduces the evolution of the Intelligent Engineering Assistant (IEA) platform toward IEA-Notebook and IEA-Sentia, a scalable agentic analytics architecture that combines workflow knowledge with LLM-based reasoning.

The tutorial discusses how modern AI agents interact with engineering environments through iterative reasoning loops involving table retrieval, code generation, tool usage, plot interpretation, contextual memory, and workflow-guided execution. A central theme of the tutorial is that the primary engineering challenge in the LLM era is no longer merely implementing analytic algorithms, but constructing grounded analytic environments that enable reliable AI reasoning over semiconductor engineering data.

Real industrial examples and deployment experiences will be discussed throughout the tutorial. The tutorial will also include demonstrations showing how modern LLM systems can now generate substantial portions of analytics workflows and software components directly from high-level engineering specifications.

The tutorial is intended for semiconductor test, product, and data engineers who want to understand how modern LLM and agentic AI technologies are reshaping the future of engineering analytics systems and semiconductor data analysis workflows.

Speakers' bios:

Li-C. Wang is a professor at ECE department at University of CA, Santa Barbara. He received PhD in 1996 from University of Texas, Austin, and was previously with Motorola PowerPC Design Center. Starting from 2003, his research has focused on investigating how machine learning could be utilized in design and test flows, where he had published more than 120 papers and supervised 23 PhD theses on topics in this area. Prior to that, his research spanned across multiple topics in EDA and test, including microprocessor test and verification, statistical timing analysis, defect-oriented testing, and SAT solvers. He received 12 Best Paper Awards and 2 Honorable Mentioned Paper Awards from major conferences, including recent best paper awards from ITC. He is the recipient of the 2010 Technical Excellence Award from Semiconductor Research Corporation (SRC) for his research contributions in data mining for test and validation. He is the recipient of the 2017 IEEE-TTTC Bob Madge Innovation Award. He is an IEEE fellow and serve as the General Chair of the International Test Conference (ITC) in 2017, 2018, and 2023.

Speakers: Debendra Das Sharma (Intel), Yervant Zorian (Synopsys)

Abstract: High-performance and power efficiency needs of emerging workloads demand on-package integration of heterogeneous processing units, memory, and electrical and optical interconnects. Applications such as artificial intelligence/machine learning, data analytics, 5G, automotive, and high-performance computing are driving these demands to meet the needs of cloud computing, intelligent edge, enterprise, client, and hand-held computing infrastructure. On-package interconnects are a critical component to deliver the power-efficient performance with the right feature set in this evolving landscape. UCIe is an open industry standard with a fully specified stack that comprehends plug-and-play interoperability of chiplets on a package; like the seamless interoperability on board with well-established and successful off-package interconnect standards such PCI Express®, Universal Serial Bus (USB)®, and Compute Express Link (CXL)®. Recently, UCIe added significant enhancements for the test and debug infrastructure to work seamlessly across the silicon life cycle. In this tutorial, we will discuss the usages and key metrics of UCIe, both planar as well as 3D. We will delve into electrical, packaging, protocol, RAS, debug, testability, manageability, and software aspects along with the compliance and interoperability mechanisms. This will address inter die and intra die requirements. The intended audience of this tutorial are architects, SoC developers, chip designers, DFT & test engineers, researchers, and system integrators.

Speakers' bios:

Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff at AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, and Editor-in-Chief Emeritus of IEEE Design and Test of Computers. Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous awards; he is a Fellow of IEEE.

Speaker: Said Hamdioui (TU Delft)

Abstract: This tutorial discusses the Device-Aware Test (DAT) approach designed to close the gap between legacy fault models and real-world defects, demonstrated on emerging industrial memory designs. DAT incorporates the impact of physical defects into technology parameters and electrical models, performs systematic fault analysis, derives appropriate fault models, and develops test solutions. Demonstrations include STT-MRAM, RRAM, FeFET, and logic chips, showing DAT sensitizes realistic and unique defects not caught by traditional approaches.

Speakers' bios:

Said Hamdioui is Chair Professor on Dependable and Emerging Computer Technologies and Head of the Quantum and Computer Engineering department at Delft University of Technology. He is a Fellow of the Netherlands Academy of Engineering and recipient of the European Innovation Council (EIC) grant in 2025. Hamdioui received the MSEE and PhD degrees with honors from TU Delft, has authored over 350 publications, holds multiple patents, and has received numerous awards for research and technology transfer. He serves on editorial boards and has extensive industry collaborations.

Speakers: Amit Pandey (Amazon), Srikanth Raman (Synopsys), Sankaran Menon (Ericsson)

Abstract: Infield Test and Debug provides deeper insights into the system behavior and structural quality while the system is running in mission-mode. It provides a non-intrusive method for testing and debug of complex computer systems. This is specifically useful in mission-critical applications such as space applications, ADAS (Advanced Driver Assistance Systems), for various industrial/robotic applications as well as virtually all real-time and datacenter/AI applications. In this tutorial we will establish the motivation for Infield system Test & Debug such as inadequacies of structural testing, and we will cover the various testing and debug techniques that are available today. We will then introduce the Infield system testing and debug mechanisms available for the closed-chassis systems using USB Type-C, PCIe and any other high-speed interfaces. We will cover the efficient design planning mechanism that would consume as much of the available bandwidth for designs using high-speed interfaces. We will conclude with results from an Infield system test and Debug used in real-world applications across the various industries.

Panel P1 - DFT at Large

DFT has its reckoning Ubiquitous AI accelerating at unprecedented speeds. Mission-critical deployments with zero tolerance for failure. Reticle-sized dies, multi-layer 3D stacking, and micro-bumps too dense to probe. A surging startup landscape challenging industry behemoths with ambitious 0-to-1 custom-silicon roadmaps.

This is today's reality. Testability can no longer be a retrofitted, one-size-fits-all commodity. The era of transactional handshakes between pre- and post-silicon silos is over—replaced by an urgent need for co-optimized, full-lifecycle ownership. At this year’s International Test Conference (ITC), we are taking this challenge head-on with a special Monday evening panel!

DFT Unboxed: The DFT Charter Has Never Been More Critical, but Are We Ready? Today’s modern test discipline must earn an equal seat at the table from day one, navigating critical trade-offs:

Strategic Alignment: Balancing test infrastructure against brutal PPA, security, schedule, and unit-cost pressures.

The Non-Negotiables: Driving near-zero DPPM at manufacturing while embedding active on-die telemetry for continuous in-mission safety and Silent Data Corruption mitigation.

Cradle-to-Grave Execution: Unifying the engineering continuum from chip architecture, physical implementation, power delivery, advanced packaging to ATE, system software, and live fleet operations.

We’re bringing together industry veterans Nitin Parimi Davide Appello Paul Freeman and Saket Goyal, to tackle the central question: Are our tools, organizations, and methodologies truly equipped to support this full-lifecycle mandate? No canned slide decks. No generic platitudes. Just an unvarnished debate on the future of our discipline.

Speakers: Omer Dossani (Amkor)

Omer Dossani heads Global Test Services at AMKOR. His brings 30+ years of semiconductor test experience to this role. Prior to AMKOR, Omer has led Test BUs at two OSATs. His strengths are in AI test enablement in HVM environments. In his role at AMKOR he helps customers new to manufacturing successfully go through the COT process.

Abstract: Artificial Intelligence (AI) and High-Performance Compute (HPC) is driving an insatiable Assembly Packaging and Test Services OSAT demand. Amkor will be presenting the OSAT perspective of the AI & HPC market segment. Production test times at every test insertion is on the rise. Multi-Chiplet advanced packages have their unique challenges and these are compounding the thermal-mechanical package performance. Wafer level and package level test access constraints and the need for DfT enhancements to simplify the production workflow, and hence the cost are warranted.

Title: The Future of DFT: Perspectives from Industry Leaders

Abstract & Speaker:

Today's test requirements are driving rapid evolution of DFT technologies and the EDA tools built to support them. Siemens is proud to welcome two distinguished DFT industry experts, Dheepak Jayaraman, ASIC Engineering Manager at Meta and Srinivas Vooka, Global Silicon DFT Lead at Google. They will share their latest experiences tackling these evolving challenges and the significant gains they've delivered to their market-leading products and the broader semiconductor market. They will also share their vision for the future and the next challenges that will need to be addressed.

(John Caruli: SPR and Diagnosis)

(Yervant, 3DIC and Memory)

Speakers: Aish Dubey (Renesas)

Aish has been working in the semiconductor industry for 20 years – building high-performance processing products for automotive and industrial markets. These products are powering automotive safety solutions in 100s of Millions of cars – saving lives and delivering in-cabin comfort. The key strategic area of interest for Aish is to build solutions that deliver a next generation of high-end premium safety and comfort experiences – that scale to mainstream markets – in collaboration with a broad eco-system spanning across automotive industry. Aish’s personal technology intent is to build – an easy to deploy, full stack safe & reliable platform for AI powered, software defined vehicles of the future. Aish has 20+ patents in his focused areas of engineering interest.

Abstract: Every chiplet architecture makes the same bet: that the seams between dies won’t become the system’s weakest link. As AI reasoning and autonomous driving push compute and memory demands beyond what monolithic silicon can economically deliver, hitting both an economic wall in yield and a power wall in logic-to-memory data movement, chiplets offer a way out by disaggregating the SoC into smaller, mixed-process dies stitched together over high-speed interconnects. The tradeoff is a new set of failure modes at exactly those seams: signal integrity loss, thermal stress, and power-delivery coupling between adjacent dies.

In this keynote, Renesas will make the case for chiplets as the right architecture for automotive AI, and detail the test strategy built to back that bet.

Speakers: Unni Vadakkan (Marvell)

Abstract: As Al accelerators and advanced networking devices scale in power and complexity, thermal management is becoming a fundamental challenge for semiconductor test. Test conditions frequently exceed product power levels and demand capabilities that differ significantly from deployed cooling solutions. This talk explores the emerging thermal barriers created by extreme power density, multi-chiplet architectures, and large advanced packages, and discusses the innovations required in thermal control, cooling infrastructure, and mechanical interfaces to enable reliable test of future high-performance semiconductor devices.

Beyond Conventional Test: Architecting In-System Test for Reliable Data-Center Silicon
Organizer: Pradipta Ghosh (Microsoft)

Session Summary: This session presents a comprehensive view of advanced in-system and in-field testing for complex data-center SoCs and AI/ML processors. They trace the path from IST architecture and DFT implementation through physical design, functional BIST, firmware integration, and post-silicon validation, highlighting the need to
also move beyond conventional Scan/ATPG. Across these layers, successful deployment depends on balancing reliability, security, throughput, diagnosability, power and timing constraints, and cross-functional coordination to deliver robust, high-quality silicon in production data centers.

In-System Test Challenges from Architecture to Physical Design for Data Center SoCs – Varun Sehgal (Broadcom)

Abstract: As data center SoCs scale in complexity, stringent RAS (Reliability, Availability, and Serviceability) requirements and low silent-data-corruption (SDC) rates demand robust In-System Test (IST) strategies. This paper presents an end-to-end overview of IST architecture focusing on In-System Test Controllers (ISTCs) bridging
IJTAG and Streaming Scan Network fabrics to drive MemoryBIST and In-System Embedded Deterministic Tests, and details practical challenges across the entire lifecycle from architecture to post-silicon validation.

At Architecture level, we address periodic coverage such as test time under boot-time budgets, test partitioning across chiplets while domains stay functional, NoC contention for pattern fetch, and pass/fail vs diagnosis needs.

At RTL/DFT, challenges include IJTAG scalability, SSN bus-width alignment, multi-controller orchestration, clock Tree, reset strategy, ISTC transparency in manufacturing mode.

In physical design, we cover ISTC-to-SSN timing closure, clock-tree load, power-domain isolation, and routing congestion at intercept logic.

Finally, we share post-silicon learnings on firmware integration, bring-up, abort recovery, and failure mapping—providing a practical checklist for achieving first-time-right IST in high-performance Data Center chips.

Anatomy of a Functional BIST Engine: Sandeep Bhatia (Google)

Abstract: Data center artificial intelligence and machine learning (AI/ML) processors often pack a large number of chips using cutting-edge technologies. They also require a very high quality and reliability due to the nature of their workloads and operating conditions. This requires testing techniques that go beyond conventional Scan/ATPG. We successfully deployed Functional BIST using a flexible, microcode-programmable Test Engine to improve the quality of TPUs at Google data centers. This technique improved TPU quality by several XXX DPPM beyond what conventional test methods achieve.

Firmware Architecture – A Behind the scenes Look at In System Test Deployment in Data Centers: Pradipta Ghosh (Microsoft)

Abstract: For in-field test to be effective in the data center, it must satisfy several practical requirements: maintain security, meet throughput targets, and provide a robust, debug-friendly architecture. Successful deployment therefore requires careful coordination across multiple engineering disciplines, with firmware serving as the key integration layer. Because firmware spans several layers that govern different aspects of SoC operation in the data-center environment, its architecture must balance a range of practical tradeoffs. This paper examines those tradeoffs and the bidirectional relationship between firmware and in-system test: firmware requirements shape the in-system architecture, while in-system test design directly influences firmware implementation.

Executive Panel

Title: Semi-Industry Disruption and the Executive Mandate for Test Subtitle: Balancing Scale, Startup Speed, and Systemic Health in the AI-Accelerated Era

The panel will bring together thought leaders from hyper-focussed
startups and well-established fabless semi companies
Here's who's confirmed:
- Michael Campbell - Sr. VP Engg, Qualcomm
- Sagar Sabade - Head of DFT, Etched
- David Greenhill - VP Engg, Cerebras
- Saidapet Ramesh - Sr. Director & Fellow - AI/ML Mfg. Operations, ARM
- Husnara Khan - Sr. Director, Si-Design/Server Health, Central DFX - AMD

Speakers: David Greenhill (Cerebras)

David Greenhill has over 30 years’ experience designing high-performance computing systems. Currently he is VP of silicon engineering at Cerebras Systems Inc. His team develops all aspects of the wafer scale engine from architecture through to productization and test. Previously he has worked on the Inmos Transputer, Sun Microsystems server CPUs, Texas Instruments OMAP processors and Altera/Intel FPGAs.

Abstract: The rapid growth of generative AI is reshaping the requirements for semiconductor systems. Trillion parameter large language models, AI reasoning, and Agentic AI push the need for very fast inference. The Cerebras Wafer Scale Engine (WSE) demonstrates a radically different approach: treating an entire silicon wafer as a single 46,225 mm² chip, integrating 4 trillion transistors and almost a million AI-optimized cores into one tightly coupled compute fabric.

(Sandeep: Defects and Testing)

Talk Title: Safe by Design in the Era of AI & AV

by Jyotika Athavale

Abstract: The compute demands of next-generation high-performance computing (HPC) and artificial intelligence (AI) accelerators are driving unprecedented silicon integration. This pushes ASIC architectures to complexity levels previously unseen in mission-critical applications, such as autonomous vehicles (AV). Ensuring functional safety and hardware dependability at this scale is a formidable challenge; traditional, localized methodologies for safety analysis, fault injection, and FMEDA can no longer keep pace with heterogeneous, multi-billion transistor designs. Today, the industry is hitting a "complexity wall," exacerbated by fragmented data formats across disparate EDA toolchains and IP blocks.

This talk explains how the high-performance silicon ecosystem can scale functional safety and dependability through standardized interoperability and advanced on-chip safety mechanisms. We will explore the critical features for building verifiably robust silicon, including In-System Test (IST) for periodic health checks, Software Diagnostic Libraries (SDL) to augment hardware self-testing, and comprehensive Silicon Lifecycle Management (SLM) to monitor device behavior from manufacturing to end-of-life. Ultimately, coupling these mechanisms with a unified data exchange format is essential to detect faults, mitigate risks, and demonstrate safety intent.

Panel and Q/A: Organized by Yervant Zorian

(Sandeep: Need for standards)

(John Caruli: Test Flow)

Tentative Agenda:

4:00-6:30pm

4:00-4:15pm - Opening remark

4:15-5:15pm - Keynote by Michael Campbell, Sr VP of Qualcomm, Inc.

Title: AI: A Hero's (Test's) Journey

Artificial intelligence is redefining the landscape of semiconductor engineering, creating new opportunities to address increasing device complexity, accelerating product cycles, and unprecedented growth in engineering data. This session explores the evolving role of technology, analytics, and intelligent systems in modern test and product engineering, highlighting how organizations are adapting to meet the demands of next-generation silicon development. Attendees will gain insights into emerging industry trends, practical applications, and the changing relationship between engineers, data, and advanced computational tools. Through a combination of real-world examples and industry perspectives, the presentation examines how innovation is reshaping engineering workflows, improving operational efficiency, and enabling teams to tackle increasingly complex challenges.

Michael Campbell is Senior Vice President of Engineering for QUALCOMM CDMA Technologies, (QCT), where he leads Product and Test Engineering, Test Automation, Failure Analysis, and Yield.

Michael joined Qualcomm in 1996. At Qualcomm, Michael has led teams across multiple areas of the business including Design Automation, FA, Yield Optimization, Product Development & Test Engineering (PDTE), Foundry Semiconductor Analysis, and Quality. Since 2014 he has been driving ML & AI test optimization internally & externally with key ATE/EDA providers for value-add AI in the test world. His drive has enabled AI boxes at multiple tester companies that enable in line real time AI functions to drive and deliver improvements in test quality and cost.
During his career at Qualcomm, Michael also has brought up Design and Test facilities in Bangalore, Singapore, Taiwan, and Mexico. In his current role, he is working to change the business and supply change through changes in PDTE and FA by driving machine learning using data available from semiconductor test to train models and automate processes.
Prior to joining QUALCOMM, Michael held engineering roles at several companies, including Mostek, INMOS and Honeywell. He holds a Bachelor of Science degree in Electrical Engineering and Computer Engineering from Clarkson University.

5:15-6:15pm - AI-Ready Infrastructure and Deployment of AI Solutions

Talk 1: Chen He, NXP: Beyond the AI Demo: Building AI-Ready Infrastructure for Scalable Engineering
Talk 2: Patty Pun, Qualcomm: AI Is Not Magic: Capturing Expertise Without Killing Autonomy

Practical Lessons and Open Questions in Engineering Knowledge Acquisition

6:15-6:30pm - Open Q&A

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The workshop aims to move beyond both AI hype and AI fear. AI can produce impressive results quickly, but fast output does not necessarily mean that a problem has been solved reliably. At the same time, the rapid adoption of AI raises important questions about job content, engineering roles, organizational investment, and future skill requirements.

The goal of the workshop is to help the community identify the right questions to ask, the appropriate criteria for evaluating AI technologies and their impact, and the key uncertainties organizations must consider when making technology, investment, and workforce decisions.

Presentations will be given by industrial practitioners with first-hand experience applying AI in real-world settings. Each session will combine a presentation with an open discussion, and active participation from attendees will be strongly encouraged. The workshop is intended not simply as a forum for presenting results, but as an opportunity for the community to collectively examine what we know, what we do not yet know, and what questions we should be asking next.

Keynote by Michael Campbell, Sr VP of Eng. Qualcomm, Inc.

Title: AI: A Hero's (Test's) Journey
Artificial intelligence is redefining the landscape of semiconductor engineering, creating new opportunities to address increasing device complexity, accelerating product cycles, and unprecedented growth in engineering data. This session explores the evolving role of technology, analytics, and intelligent systems in modern test and product engineering, highlighting how organizations are adapting to meet the demands of next-generation silicon development. Attendees will gain insights into emerging industry trends, practical applications, and the changing relationship between engineers, data, and advanced computational tools. Through a combination of real-world examples and industry perspectives, the presentation examines how innovation is reshaping engineering workflows, improving operational efficiency, and enabling teams to tackle increasingly complex challenges.

Michael Campbell is Senior Vice President of Engineering for QUALCOMM CDMA Technologies, (QCT), where he leads Product and Test Engineering, Test Automation, Failure Analysis, and Yield.

Michael joined Qualcomm in 1996. At Qualcomm, Michael has led teams across multiple areas of the business including Design Automation, FA, Yield Optimization, Product Development & Test Engineering (PDTE), Foundry Semiconductor Analysis, and Quality. Since 2014 he has been driving ML & AI test optimization internally & externally with key ATE/EDA providers for value-add AI in the test world. His drive has enabled AI boxes at multiple tester companies that enable in line real time AI functions to drive and deliver improvements in test quality and cost.
During his career at Qualcomm, Michael also has brought up Design and Test facilities in Bangalore, Singapore, Taiwan, and Mexico. In his current role, he is working to change the business and supply change through changes in PDTE and FA by driving machine learning using data available from semiconductor test to train models and automate processes.
Prior to joining QUALCOMM, Michael held engineering roles at several companies, including Mostek, INMOS and Honeywell. He holds a Bachelor of Science degree in Electrical Engineering and Computer Engineering from Clarkson University.

Tentative Agenda

8:00-9:00am – Transforming Test for the AI Era: From Test Optimization to Assistance and Autonomy (The growing complexity of AI systems is driving new challenges in semiconductor testing, including increasing test cost, engineering productivity demands, and system reliability concerns. Traditional test methodologies are being stretched by larger designs, more complex integration technologies, and the need for reliable operation throughout the product lifecycle. This session presents a path for the evolution of semiconductor testing in the AI era. It begins with AI-enabled test optimization techniques that improve test quality, reduce runtime, and lower manufacturing cost. It then explores how AI technologies can assist engineers and automate key test development activities, paving the way toward autonomous test engineering.)

Talk 1: AI Enabled Scalable Test Solution for Test QoR Improvement and Cost Reduction; MediaTek and Synopsys
Talk 2: Industrial Experience for Achieving Advanced Test Coverage Leveraging AI; Samsung and Synopsys
Talk 3: AI Applications for Test: From Optimization to Assistance and Autonomy; Srikanth Venkat Raman, Synopsys

9:00-10:00am: Panel - Building AI-native engineering (DFT organizations are being asked to support more complex SoCs, more chips and chiplets, 3D-IC integration, and heterogeneous architectures. Execution speed has become a competitive differentiator, and compressed schedules leave little room for the traditional, sequential handoffs between design, DFT, verification, and silicon validation teams. On top of that, there’s a well-known, industry-wide shortage of experienced DFT talent. AI augmentation is therefore moving from optional productivity aid to operational necessity. This panel asks a practical question: as AI agents take on DFT tasks once reserved for experienced engineers, what should the DFT engineer of the future look like, and how should organizations restructure to get there?)

10:30-12:00: Applied AI in DFT: Skill developments and customer applications (Organizer: Ron Press, Siemens EDA; Abstract: Applied AI in DFT explores how semiconductor engineers can effectively adopt and customize AI-driven Design-for-Test workflows. The session covers practical interaction with agentic EDA tools, LLMs, and supporting infrastructures. The talk includes best practices for prompting, managing AI-generated data, validating results, and troubleshooting unexpected behavior. Industry speakers will share real-world experiences deploying AI in production DFT environments. They will demonstrate how company-specific design challenges, traditionally addressed through custom scripts and DRCs, can be enhanced through reusable AI skills and workflow automation. Attendees will gain practical insights into balancing user customization with vendor capabilities, understanding the effort required to develop specialized AI solutions. They will gain practical insights in applying AI responsibly to improve productivity, quality, and scalability in modern semiconductor test design.)

Talk 1: Your role in new AI in DFT
Presenter: Amer Guettaf, Principal DFT Architect, Siemens EDA
Amer will present on what to expect and how to interact with DFT tool agentic flows.
Talk 2: Bring product context into AI
Presenter: Anusha Kotha, Lead DFT Engineer, Microsoft
Anusha is part of the DFT AI development team in Microsoft and will share experience in flow development
Talk 3: Practical implementation of AI in DFT
Presenter: Sujay Pandey, EDA Tools Software Engineer, Intel
Sujay works in Intel's Central Tools, Flow, and Methodology (TFM) team and will share how AI agents and skills can help in shift-left for Design-for-Test (DFT).

1:00-2:30pm: AI in test chips in view of heterogeneous integration, from 2.5D interposers and CoWoS to hybrid bond
Talk1: Ramune Nagisetty, PDF Solutions
Talk 2: Moran Wolf and Noam Brousard, Protean Tecs
Talk 3: Priyavadan Kumar, AMD (Beyond the Copilot: Engineering Trustworthy AI Agents for Semiconductor Test: AI agents can accelerate test-program development and debug, access to engineering knowledge, and test-data analytics, but deploying them responsibly requires more than model performance. This talk presents a practical architecture combining authoritative engineering context, controlled tools, persistent workflow state, evidence-based evaluation, and risk-based approvals. It will illustrate how engineers remain accountable as workflows progress from assistance toward bounded automation, and why these controls become increasingly important as advanced packaging expands data, identity, and provenance boundaries across die, chiplet, package, and system test.)

2:45-3:55pm: Panel - How does test engineering life will be like in the near future?
(Open Discussion with All Presenters)

3:55-4:00pm: Closing remark – Look Forward To Next Year