ABSTRACT. Large Language Models (LLMs) enable agentic systems to perform increasingly sophisticated engineering analytics. However, maximizing reasoning autonomy is not always the optimal design choice. Practical engineering environments must balance three competing objectives: leveraging the intelligence of agentic reasoning, minimizing token and computation cost, and maintaining controllability and repeatability of results. This paper presents the design philosophy underlying the IEA platform, which addresses this tradeoff through three complementary operating modes. IEA Notebook emphasizes workflow-guided analytics and code generation, providing high controllability and low token consumption. IEA Sentia leverages autonomous agentic reasoning over grounded contexts and ARTs to maximize analytic flexibility and discovery. IEA-VP introduces a higher-level reasoning model that answers executive questions by operating on previously generated analysis artifacts rather than reanalyzing raw data, significantly reducing computational cost. Together, these modes illustrate that effective engineering AI systems should not optimize solely for reasoning capability, but instead balance intelligence, cost, and control according to the needs of the user and the task.

ABSTRACT. This paper presents the Intelligent Engineering Assistant (IEA), an agentic analytics platform that captures problem-solving workflows and shares them as reusable organizational assets. IEA integrates a notebook environment for capturing analytical sessions, a shared library for workflows and tools, and agents that support inspection and natural-language adaptation. We describe the platform architecture, workflow-sharing model, and report deployment experience, including challenges in provenance, discoverability, ownership, access control, and safe modification. Early deployment shows reduced scripting effort, increased workflow reuse, and faster onboarding. Key challenges include validation, context portability, and governance, highlighting that scaling AI in engineering depends on managing reusable analytical workflows.

ABSTRACT. Semiconductor test development requires engineers to transform architecture documentation, DFT collateral, register descriptions, patterns, debug logs, and historical test content into production-ready ATE solutions. This work presents an engineer-in-the-loop workflow that applies Large Language Models (LLMs) to accelerate development on the Advantest SmarTest 8 platform. The approach focuses on three areas: AI-assisted knowledge acquisition, infrastructure generation, and test development/debug support. Representative startup and loopback case studies demonstrate how LLMs assist with requirement extraction, register-access planning, test-method skeleton generation, digital-capture debug, and documentation. All AI-generated artifacts are reviewed and validated by a test engineer. Results indicate improved onboarding, documentation review, infrastructure creation, and debug planning productivity.

ABSTRACT. As semiconductor manufacturing moves toward greater automation and data-driven decision making, the way engineers interact with complex and highly interconnected data must evolve. We present a secure, enterprise-ready approach that allows engineers to use natural language to analyze complex datasets, generate insights, and automate workflows — while keeping all data and IP fully protected. Built on an MCP-enabled architecture, the solution supports any AI assistant and executes all analyses within controlled, sandboxed environments. Through practical examples, we show how this paradigm reduces analysis cycle time, lowers the barrier to advanced analytics, and enables scalable adoption across HVM, NPI, and characterization.

ABSTRACT. Post-silicon debug of complex processor failures remains one of the most time-intensive activities in semiconductor validation. This paper presents the Scandump Pass/Fail Analyzer, an AI-agent-based proof of concept that automates the ingestion, statistical analysis, and interpretation of scan dump data from silicon debug sessions. Applied to a real voltage-marginal sighting on a server-class processor, the analyzer autonomously identified the root-cause module and mechanism: a timing violation on an integrated clock gate (ICG) enable path. The hypothesis was driven by scan-data evidence and RTL-based design context, and was confirmed through silicon experiments proposed by the agent itself. We describe the analyzer’s architecture, its application to the case study, and discuss implications for future agentic silicon debug workflows.

ABSTRACT. Scan RTL Design Rule Check (DRC) violations are identified by EDA tools, but their resolution often requires manual DFT analysis, increasing turnaround time and delaying scan readiness. This paper presents an Agentic AI methodology in which an LLM orchestrates a tool-augmented workflow using Model Context Protocols (MCPs) to autonomously analyze, trace, and resolve DRC violations. The agent parses EDA reports, traces clock and reset signals through RTL, and generates constraint fixes and RTL recommendations. MCPs enable RTL tracing and knowledge-base access within the workflow. Results on five design blocks spanning a 36× violation range demonstrate 100% coverage of async-reset and clock controllability violations associated with dedicated test clock controllers, with end-to-end execution under 24 seconds.

ABSTRACT. Array memory defect analysis conventionally requires engineers to manually correlate MBIST raster failure data against physical layout coordinates and classify spatial defect patterns, which is a time-intensive and error-prone process. In this paper, AI-Empowered ArrayInsights is developed as an agentic AI workflow within an internal MCP server to automate this pipeline. Given MBIST raster data, AI2 resolves logical-to-physical address mappings, classifies failures into eleven spatial defect categories, and generates memory-level and die-level layout heatmaps. A Union-Find clustering engine groups test instances into systematic or random defect buckets based on raster overlap, physical address signatures, and defect fingerprints. Engineers interact through natural language, reducing complex semiconductor test analytics from hours of manual processing to a single prompt.

ABSTRACT. Increasing silicon integration through chiplets and advanced process nodes is driving greater complexity in yield learning, and debug. These challenges require scalable analytics to optimize quality and test cost. At Intel, we are addressing this complexity by combining Lean Six Sigma principles with AI infrastructure designed for SCAN debug. The objective is to create a self-learning ecosystem in which new defect modes can be analyzed and reused across domains and future product generations. This paper presents the foundational infrastructure, including real-time context access, inline data collection, automated triage, cross-domain analytics, and control mechanisms for continuous improvement. It also discusses how AI agents accelerate isolation and resolution, as well as the bottlenecks that will shape future innovation in scalable silicon debug.

ABSTRACT. Failure analysis (FA) plays a critical role in semiconductor product development, particularly during New Product Introduction (NPI) and New Technology Introduction (NTI) DDPM learning. However, the exponential growth in FA data—spanning images, reports, and test logs—has made knowledge retrieval increasingly inefficient and time-consuming. This paper presents an AI-driven framework that combines computer vision, large language models (LLMs), and agentic workflows to enhance failure analysis retrieval and reporting. The proposed system automates FA report generation and enables intelligent, multimodal querying across historical datasets, supporting faster root cause identification, improved defect screening, and proactive quality assurance. The approach transforms FA workflows from manual, fragmented processes into integrated, knowledge-centric systems, improving both engineering productivity and product quality.

ABSTRACT. Engineers in semiconductor test, debug, and validation depend on workflows interleaving data extraction, statistical analysis, hardware control, and decisions. Today these workflows are stitched by hand or brittle scripts, making them slow, error-prone, and irreproducible. We present Cascade, a visual agentic workflow builder that lets engineers compose LLM agents, deterministic scripts, and enterprise tools via the MCP, into reproducible, auditable flows without writing orchestration code. Flows run interactively in VS Code or headless in CI/CD and bench hosts. We describe its architecture, a hybrid trust model (deterministic compute for data, LLMs for interpretation, human gates for irreversible actions), and deployment experience spanning offline analytics, human-gated change review, and live bench validation, and honest account of reliability limits and organizational barriers.

ABSTRACT. Array design verification (DV) reporting is a repetitive manual workflow — database extraction, multi-type post-processing, and hand-authored summaries — requiring 1–2 workdays per cycle. This paper presents DVInsights, an agentic DV skill within a GitHub Copilot-based engineering assistant that automates this full pipeline. Single natural language command triggers SQL extraction, data normalization, test category detection, and generation of four interactive HTML dashboards: voltage margin health, erratic bit characterization, ceiling voltage analysis, and trim fuse characterization . Each dashboard integrates a narrative layer that interprets metrics and generates plain-language engineering summaries. A prompt analysis answers natural language queries against a pre-aggregated summary in under one second. Evaluated on 26 production lots, DVInsights achieves a 120× to 240× reduction in cycle time.

ABSTRACT. PyOTPL is a Python abstraction layer for OpenStar Test Program Language (OTPL) module development in Automated Test Equipment workflows. Instead of manually editing flat OTPL source, engineers author compact Python that generates compliant OTPL outputs while embedding product-specific rules transparently. This improves maintainability, reduces repetitive edits, and enables stronger reuse across module variants. Because Python is broadly represented in LLM training data, AI systems can reason over PyOTPL sources more effectively than low-level OTPL, lowering context burden and token usage while improving response speed and code quality. Built on this foundation, Module Agent automates intent-to-module updates through an AI-friendly, validation-centered workflow for scalable semiconductor test program development.

ABSTRACT. LPDDR6 verification faces significant challenges due to feature complexity, configuration explosion, and manual, error‑prone coverage modeling. Traditional directed and random testing approaches fail to scale, leaving critical cross‑feature interactions, timing corner cases, and configuration transitions insufficiently covered. This work introduces an AI‑assisted, coverage‑driven verification framework combined with constrained‑random stimulus generation to systematically close coverage gaps. Feature‑specific coverage models, intelligent exploration of speed grades and densities, and automated gap identification enable comprehensive validation without proliferating simulation environments.

ABSTRACT. Modern processor verification struggles to reach deep architectural states due to the inefficiencies of traditional mutation-based fuzzing. We propose HiFuzz, a novel hierarchical reinforcement learning framework that replaces mutation with a structured, two-layer generation process: a Program Agent for global layout and a Basic Block Agent for precise instruction filling. To overcome reward sparsity, HiFuzz integrates an adaptive coverage reward mechanism and a semantic-aware basic block encoder providing intrinsic feedback. Extensive evaluations on real-world RISC-V processors demonstrate that HiFuzz significantly outperforms state-of-the-art fuzzers in coverage and bug detection.

ABSTRACT. Resistive defects in scaled FETs often escape standard structural testing. While multi-VDD testing can expose these defects, exhaustive SPICE-based simulation is computationally expensive across diverse defect sites, resistances, and VT flavors. To address this, we propose a spatio-temporal deep learning framework to predict SPICE-accurate waveforms of standard cells with transistor-level defects. We model netlists as heterogeneous graphs using a Graph Attention Network with ATPG-inspired topological features. To capture timing effects, we employ a self-attentive Temporal Convolutional Network, replacing SPICE with high-speed, GPU-accelerated time-domain predictions. We perform defect classification and test compaction, accelerating defect coverage analysis and cell-level test pattern optimization.

ABSTRACT. The aggressive shrinking of transistors at advanced nodes increases physical defects, especially in Back-End-of-Line (BEOL) interconnects, where conventional ATPG lacks physical test coverage. This paper details the novel approaches of devising physical test coverage metric for a design, intelligent extraction and identification of sensitive layout shapes, ML based categorization with physical testability enhancement techniques, inter-metal layer bridge sites extraction, targeting and diagnosis. Validation on test vehicles demonstrates marked increases in physical test coverage and successful identification of unique defect sites, highlighting the necessity of these advanced test and diagnosis strategies for yield learning.

ABSTRACT. This paper proposes a Built-In Self-Calibration scheme for enhancing the linearity of a time-to-digital converter (TDC) used for accurate clock period measurement of the clock signal produced by an All-Digital Phase-Locked Loop (ADPLL). We achieve our goal by treating the TDC and ADPLL as a "combo circuit" with two main features: (1) One-Way Varactor Cells (OWVCs) for resolution adjustment in the TDC, (2) a transfer-function-linearization process using the training clock signals produced by the ADPLL. Post-layout simulation reveals that the measurement error of the minimum clock period sample can be effectively reduced from 7.03 ps to 1.28 ps.

ABSTRACT. This paper presents results for the first silicon implementation of analog scan-based design-for-test (DfT) and automatic test pattern generation for a 12-bit SAR ADC in a 65 nm technology. The DfT consists of an IJTAG test data register, digital multiplexers, analog stimulus transistors, and analog scan inverters, to control and observe ports of the ADC and nodes deep inside it. The DfT had minimal impact on the ADC’s performance. The analog scan results were stable across process corners, supply voltages, and stimulus frequencies, and high coverage testing of defect free and intentionally defective devices was achieved in sub-millisecond test times.

ABSTRACT. Burn‑In (BI) is a critical reliability screen for semiconductor devices but adds substantial cost due to long stress times and repeated test insertions. This work introduces a production‑ready, data‑driven framework for adaptive BI reduction using an ensemble of ML models (RF, XGB, MLP). Leveraging FAB, wafer sort, and final test data, the system enables per‑device BI‑skip decisions at a pre‑BI FT insertion under a strict zero‑escape requirement. A model‑driven feature‑selection method supports scalable deployment across complex products. Validation on >500k training and >200k test units demonstrates over 25% BI cost reduction while maintaining outgoing quality.

ABSTRACT. The complexity of modern hardware systems creates a large surface for information flows that break the confidentiality or integrity of classified information. Current approaches to detecting malicious information flows, such as information flow tracking, lack scalability to complex computing systems or compromise accuracy. This paper proposes DiamondBlade, a generalized and precise information flow tracking approach based on formal verification. DiamondBlade extends a 2-instance computational model with optimizations, enabling it to scale to complex systems and provide formal security guarantees. We demonstrate DiamondBlade in case studies on an AES implementation, the Caliptra HMAC unit, the BOOM processor and the Pulpissimo SoC.

ABSTRACT. This paper presents a concurrent fault simulation methodology tailored for timing-critical and transistor-level memory peripheral circuits. Existing concurrent fault simulators support only zero-delay abstraction, and extending them to annotated delay models poses two challenges: temporal divergence may occur without logic value divergence, and delay selection depends on passive timing state that lacks explicit fanout for event-driven tracking. The proposed method addresses these challenges by extending divergence tracking to a two-dimensional space spanning both logic values and temporal state, independently maintaining passive timing contributors within faulty machines, and establishing hierarchical port fault semantics with injection flags that constrain fault effects within switch-level hierarchies. Validation on industrial DRAM circuits demonstrates an average simulation speedup of approximately 44× while maintaining a maximum coverage delta of less than 0.17% compared to the serial simulation mode.

ABSTRACT. Cell-aware test (CAT) characterization is often hindered by the high cost of SPICE simulations. While structural analysis can prune these simulations, prior methods like TrUnDeL focus on identifying structurally undetected cases and overlook significant optimization opportunities. We propose GroStra, a framework that enhances efficiency through three strategies: defect equivalence-Based simulation pruning, guaranteed-detected structural analysis, and using static analysis to accelerate dynamic graph processing. Experimental results on ASAP7 and 12nm libraries demonstrate that GroStra reduces simulation effort by up to 25.4% and 32.6% over TrUnDeL and achieves up to a 15x and 55x speedup, significantly lowering characterization costs without sacrificing accuracy.

ABSTRACT. Compute-in-memory (CiM) architectures have emerged as an effective solution to mitigate the data-movement bottleneck in modern computing systems. Among emerging memory technologies, MRAM is particularly attractive for CiM-based deep neural network accelerators due to its high density and energy efficiency. However, the integration of memory and computation introduces new security concerns. In this work, we analyze the vulnerability of MRAM-based CiM architectures to side-channel attacks that may expose stored DNN weights. To address this threat, we propose LEO-CiM, a lightweight execution obfuscation framework that perturbs computation patterns while preserving correctness, thereby significantly hindering an attacker’s ability to infer sensitive information.

ABSTRACT. This work proposes LPLL, a novel approach of linear programmingbased logic locking. LPLL reformulates key-gate selection problem as a linear optimization task to explicitly maximize output obfuscation. It innovatively translates boolean logic to linear expressions, and iteratively identifies key gate positions under quantitative objective functions. Evaluated on ISCAS-85 benchmarks, the proposed LPLL achieves about 95% corrupted output patterns.

ABSTRACT. Co-Packaged Optics (CPO) is emerging as a key technology to overcome I/O bottlenecks in data-center and high-performance systems by tightly integrating photonic and electronic components. While CPO improves bandwidth density and energy efficiency, it introduces unexplored physical attack surfaces. This paper presents the first pre-silicon electromagnetic fault injection (EMFI) vulnerability analysis framework for CPO systems. Leveraging multi-physics co-simulation across electromagnetic, thermal, and electrical domains, we analyze photonic integrated circuits and their control loops. Results show that EM-induced currents can disrupt microring thermal control, causing a change in the resonance wavelength up to 1.13 nm, which eventually leads to data corruption.

ABSTRACT. Modern flexible hardware systems demand real-time anomaly detection. We present JAMS, a JTAG-based monitoring framework for RISC-V processors that captures runtime state (registers and performance counters) via debug access. Using unsupervised techniques like PCA and outlier detection on time-series data, JAMS identifies deviations from benign execution without prior labeling. Unlike prior software-based HPC approaches, JAMS is an immutable hardware coprocessor. Implemented on a 64-bit dual-issue core on a Xilinx Versal SoC-FPGA and evaluated with cryptographic benchmarks, it achieves a median F1-score of 0.99, demonstrating robust detection of malicious microarchitectural behavior.

ABSTRACT. Resistive Random-Access Memory (ReRAM)-based computing-in-memory (CIM) architectures offer a promising path beyond von Neumann systems by reducing data movement, thereby improving energy efficiency. However, these architectures face significant challenges from temperature variations, which shift resistance states, degrade resistance ratios, and ultimately increase computational errors by perturbing the output currents. We first identify the temperature-sensitive component by analyzing real device-level measurement data. We then develop an analytical framework and design a temperature-aware compensation circuit that mitigates variations in the output current. We benchmark our methodology using VGG16 on CIFAR-10 and achieve up to 92.4% accuracy with only ±0.4% variation across -25°C-125°C.

ABSTRACT. Silicon photonic integrated circuits (PICs) offer exceptional bandwidth and energy efficiency, but their analog, wave‑based behavior makes scalable manufacturing test challenging. This paper presents a defect‑oriented, optimization‑driven automatic test pattern generation (ATPG) framework for silicon PICs that targets parametric, catastrophic, and environmental variations. Fabrication and operating variability are captured within a structured convex parameter space, and passive, analytically differentiable transfer‑matrix surrogates are used to pose ATPG as a maximin stimulus search that maximizes worst‑case defect observability under per‑channel measurement noise and bounded process/environment drift. We evaluate our ATPG on three PIC benchmark designs.