ABSTRACT. Large Language Models (LLMs) enable agentic systems to perform increasingly sophisticated engineering analytics. However, maximizing reasoning autonomy is not always the optimal design choice. Practical engineering environments must balance three competing objectives: leveraging the intelligence of agentic reasoning, minimizing token and computation cost, and maintaining controllability and repeatability of results. This paper presents the design philosophy underlying the IEA platform, which addresses this tradeoff through three complementary operating modes. IEA Notebook emphasizes workflow-guided analytics and code generation, providing high controllability and low token consumption. IEA Sentia leverages autonomous agentic reasoning over grounded contexts and ARTs to maximize analytic flexibility and discovery. IEA-VP introduces a higher-level reasoning model that answers executive questions by operating on previously generated analysis artifacts rather than reanalyzing raw data, significantly reducing computational cost. Together, these modes illustrate that effective engineering AI systems should not optimize solely for reasoning capability, but instead balance intelligence, cost, and control according to the needs of the user and the task.

ABSTRACT. This paper presents the Intelligent Engineering Assistant (IEA), an agentic analytics platform that captures problem-solving workflows and shares them as reusable organizational assets. IEA integrates a notebook environment for capturing analytical sessions, a shared library for workflows and tools, and agents that support inspection and natural-language adaptation. We describe the platform architecture, workflow-sharing model, and report deployment experience, including challenges in provenance, discoverability, ownership, access control, and safe modification. Early deployment shows reduced scripting effort, increased workflow reuse, and faster onboarding. Key challenges include validation, context portability, and governance, highlighting that scaling AI in engineering depends on managing reusable analytical workflows.

ABSTRACT. Semiconductor test development requires engineers to transform architecture documentation, DFT collateral, register descriptions, patterns, debug logs, and historical test content into production-ready ATE solutions. This work presents an engineer-in-the-loop workflow that applies Large Language Models (LLMs) to accelerate development on the Advantest SmarTest 8 platform. The approach focuses on three areas: AI-assisted knowledge acquisition, infrastructure generation, and test development/debug support. Representative startup and loopback case studies demonstrate how LLMs assist with requirement extraction, register-access planning, test-method skeleton generation, digital-capture debug, and documentation. All AI-generated artifacts are reviewed and validated by a test engineer. Results indicate improved onboarding, documentation review, infrastructure creation, and debug planning productivity.

ABSTRACT. As semiconductor manufacturing moves toward greater automation and data-driven decision making, the way engineers interact with complex and highly interconnected data must evolve. We present a secure, enterprise-ready approach that allows engineers to use natural language to analyze complex datasets, generate insights, and automate workflows — while keeping all data and IP fully protected. Built on an MCP-enabled architecture, the solution supports any AI assistant and executes all analyses within controlled, sandboxed environments. Through practical examples, we show how this paradigm reduces analysis cycle time, lowers the barrier to advanced analytics, and enables scalable adoption across HVM, NPI, and characterization.

ABSTRACT. Post-silicon debug of complex processor failures remains one of the most time-intensive activities in semiconductor validation. This paper presents the Scandump Pass/Fail Analyzer, an AI-agent-based proof of concept that automates the ingestion, statistical analysis, and interpretation of scan dump data from silicon debug sessions. Applied to a real voltage-marginal sighting on a server-class processor, the analyzer autonomously identified the root-cause module and mechanism: a timing violation on an integrated clock gate (ICG) enable path. The hypothesis was driven by scan-data evidence and RTL-based design context, and was confirmed through silicon experiments proposed by the agent itself. We describe the analyzer’s architecture, its application to the case study, and discuss implications for future agentic silicon debug workflows.

ABSTRACT. Scan RTL Design Rule Check (DRC) violations are identified by EDA tools, but their resolution often requires manual DFT analysis, increasing turnaround time and delaying scan readiness. This paper presents an Agentic AI methodology in which an LLM orchestrates a tool-augmented workflow using Model Context Protocols (MCPs) to autonomously analyze, trace, and resolve DRC violations. The agent parses EDA reports, traces clock and reset signals through RTL, and generates constraint fixes and RTL recommendations. MCPs enable RTL tracing and knowledge-base access within the workflow. Results on five design blocks spanning a 36× violation range demonstrate 100% coverage of async-reset and clock controllability violations associated with dedicated test clock controllers, with end-to-end execution under 24 seconds.

ABSTRACT. Array memory defect analysis conventionally requires engineers to manually correlate MBIST raster failure data against physical layout coordinates and classify spatial defect patterns, which is a time-intensive and error-prone process. In this paper, AI-Empowered ArrayInsights is developed as an agentic AI workflow within an internal MCP server to automate this pipeline. Given MBIST raster data, AI2 resolves logical-to-physical address mappings, classifies failures into eleven spatial defect categories, and generates memory-level and die-level layout heatmaps. A Union-Find clustering engine groups test instances into systematic or random defect buckets based on raster overlap, physical address signatures, and defect fingerprints. Engineers interact through natural language, reducing complex semiconductor test analytics from hours of manual processing to a single prompt.

ABSTRACT. Increasing silicon integration through chiplets and advanced process nodes is driving greater complexity in yield learning, and debug. These challenges require scalable analytics to optimize quality and test cost. At Intel, we are addressing this complexity by combining Lean Six Sigma principles with AI infrastructure designed for SCAN debug. The objective is to create a self-learning ecosystem in which new defect modes can be analyzed and reused across domains and future product generations. This paper presents the foundational infrastructure, including real-time context access, inline data collection, automated triage, cross-domain analytics, and control mechanisms for continuous improvement. It also discusses how AI agents accelerate isolation and resolution, as well as the bottlenecks that will shape future innovation in scalable silicon debug.

ABSTRACT. Failure analysis (FA) plays a critical role in semiconductor product development, particularly during New Product Introduction (NPI) and New Technology Introduction (NTI) DPPM learning. However, the exponential growth in FA data—spanning images, reports, and test logs—has made knowledge retrieval increasingly inefficient and time-consuming. This paper presents an AI-driven framework that combines computer vision, large language models (LLMs), and agentic workflows to enhance failure analysis retrieval and reporting. The proposed system automates FA report generation and enables intelligent, multimodal querying across historical datasets, supporting faster root cause identification, improved defect screening, and proactive quality assurance. The approach transforms FA workflows from manual, fragmented processes into integrated, knowledge-centric systems, improving both engineering productivity and product quality.

ABSTRACT. Engineers in semiconductor test, debug, and validation depend on workflows interleaving data extraction, statistical analysis, hardware control, and decisions. Today these workflows are stitched by hand or brittle scripts, making them slow, error-prone, and irreproducible. We present Cascade, a visual agentic workflow builder that lets engineers compose LLM agents, deterministic scripts, and enterprise tools via the MCP, into reproducible, auditable flows without writing orchestration code. Flows run interactively in VS Code or headless in CI/CD and bench hosts. We describe its architecture, a hybrid trust model (deterministic compute for data, LLMs for interpretation, human gates for irreversible actions), and deployment experience spanning offline analytics, human-gated change review, and live bench validation, and honest account of reliability limits and organizational barriers.

ABSTRACT. Array design verification (DV) reporting is a repetitive manual workflow — database extraction, multi-type post-processing, and hand-authored summaries — requiring 1–2 workdays per cycle. This paper presents DVInsights, an agentic DV skill within a GitHub Copilot-based engineering assistant that automates this full pipeline. Single natural language command triggers SQL extraction, data normalization, test category detection, and generation of four interactive HTML dashboards: voltage margin health, erratic bit characterization, ceiling voltage analysis, and trim fuse characterization . Each dashboard integrates a narrative layer that interprets metrics and generates plain-language engineering summaries. A prompt analysis answers natural language queries against a pre-aggregated summary in under one second. Evaluated on 26 production lots, DVInsights achieves a 120× to 240× reduction in cycle time.

ABSTRACT. PyOTPL is a Python abstraction layer for OpenStar Test Program Language (OTPL) module development in Automated Test Equipment workflows. Instead of manually editing flat OTPL source, engineers author compact Python that generates compliant OTPL outputs while embedding product-specific rules transparently. This improves maintainability, reduces repetitive edits, and enables stronger reuse across module variants. Because Python is broadly represented in LLM training data, AI systems can reason over PyOTPL sources more effectively than low-level OTPL, lowering context burden and token usage while improving response speed and code quality. Built on this foundation, Module Agent automates intent-to-module updates through an AI-friendly, validation-centered workflow for scalable semiconductor test program development.

ABSTRACT. LPDDR6 verification faces significant challenges due to feature complexity, configuration explosion, and manual, error‑prone coverage modeling. Traditional directed and random testing approaches fail to scale, leaving critical cross‑feature interactions, timing corner cases, and configuration transitions insufficiently covered. This work introduces an AI‑assisted, coverage‑driven verification framework combined with constrained‑random stimulus generation to systematically close coverage gaps. Feature‑specific coverage models, intelligent exploration of speed grades and densities, and automated gap identification enable comprehensive validation without proliferating simulation environments.

ABSTRACT. We present Pattern Clustering Analysis (PCA), a novel framework for analyzing complex frequency-voltage Shmoo test data. PCA tracks failure pattern movements across temperatures and memory configurations. This is used to classify patterns into four fundamental quadrants based on temperature response characteristics. Our method analyzes hundreds of patterns across millions of test conditions in mere hours. Use of quadrants instead of complex multi-dimensional clusters enabled faster engineering decision making. Implementation on Intel production test data demonstrates practical readiness. The framework provides intuitive visualizations that enable rapid identification of memory-specific sensitive patterns requiring targeted mitigation.

ABSTRACT. Abstract— This study introduces Active Coolant Thermal Control (ACTC), an advanced system for precise temperature management during stress voltage testing, essential for ensuring the reliability of AI chips with high power densities prone to thermal runaway and tip-burn. A predictive cooling optimization model was developed using Full Factorial Design (FFD) within the DOE. Integrated into prober construction, ACTC dynamically regulates coolant flow rates to enhance thermal stability and responsiveness. The model's accuracy was validated through ANOVA with significant p-values, stepwise regression, and residual analysis. ACTC outperforms passive PID control systems, improving precision, increasing voltage standards and yield.

ABSTRACT. High-performance computing (HPC) Device Interface Boards (DIBs) operating under high-current conditions exhibit strong electro-thermal coupling that critically affects power delivery network (PDN) integrity. This paper presents a simulation-driven, electro-thermal-aware PDN design methodology based on a unified workflow integrating static IR-drop analysis, temperature-dependent PDN impedance extraction, and system-level transient IR-drop evaluation. An iterative two-way electro-thermal co-simulation framework is employed to capture the interaction between Joule heating and PDN electrical behavior. The proposed approach enables more realistic and reliable voltage integrity assessment and supports robust PDN design for high-power HPC DIBs.

ABSTRACT. This paper presents a scalable methodology for early yield excursion detection using lot-level Defective Die Count (DDC) macros in foundry manufacturing. By aligning DDC events to specific lots and process layers, we generate high-resolution defect indicators that enable near-real-time alerts—well before final test results. Deployed in a 5nm SoC production line, the approach reduced defect density from 0.16 cm² to 0.12 cm² and enabled targeted physical failure analysis. We detail implementation, integration, and case studies demonstrating the framework’s impact on yield forecasting, excursion containment, and cost avoidance in high-volume semiconductor manufacturing.

ABSTRACT. Identifying root causes of chip failures is crucial in semiconductor manufacturing but requires analyzing vast multi-modal data generated throughout the fabrication process. To address this issue, this paper proposes a wafer multi-modal feature clustering using multi-view clustering. Separate feature extraction methods are designed for map and tabular features. For map features, we apply multi-view consensus clustering to obtain a consensus matrix, which is then integrated with the consensus matrix derived from tabular features through attention-weighted fusion. Clustering results are generated using Stable Silhouette Index. Experiments show our method effectively groups wafers with the similar underlying root cause and wafer maps.

ABSTRACT. Conventional high-speed interconnect signal integrity characterization relies on customized laboratory fixtures to evaluate connectors, PCB backplanes, and cable assemblies. While effective at the component level, this approach does not capture rack-level mechanical tolerances and mating variations between trays, PCBs, and cable backplanes. In high-speed systems, such variations can introduce impedance discontinuities that degrade signal integrity and overall performance. This paper presents an In-Situ Time Domain Reflectometry (TDR) test fixture for end-to-end characterization and debug in rack-scale servers. The method enables channel measurement under real assembly conditions, improving correlation between lab results and deployed system performance in large-scale computing environments.

ABSTRACT. This paper presents a forensic analysis of a critical InfiniBand (IB) switch failure in a customer HPC datacenter. A NVIDIA Quantum switch experienced recurrent down events, causing complete fabric isolation over 15 days. Systematic analysis of NVOS dumps, UFM sysdumps, telemetry, and ASIC register dumps identified I2C bus instability as the root cause, propagating from localized switch ASIC flapping to system-wide failure. Firmware inspection confirmed catastrophic I2C hardware damage on a switch ASIC with the SMBus controller FSM stuck and catastrophic bit set. We developed diagnostic tools for early detection, risk scoring, and analysis of multi-ASIC cascade mechanisms.

ABSTRACT. This paper presents a high-precision production test methodology for Direct RF Sampling AFEs using automated test equipment (ATE). While these architectures simplify system design, they introduce challenges in clock jitter, signal integrity, and massive data throughput. This study evaluates PLL jitter across various clock sources and proposes optimized I/O techniques tailored for specific test strategies. Experimental results across multiple process corners validate that the methodology achieves lab-grade accuracy and robust correlation, ensuring high-fidelity performance verification for high-volume semiconductor manufacturing.

ABSTRACT. As digital circuits continue to increase in size and complexity, diagnosing stuck-at and delay faults becomes increasingly difficult. This paper proposes GTFD, a gate-level fault prediction model for large-scale digital circuits. GTFD uses multi-level GCNs to learn structural representations at gate, module, and circuit levels, and employs topology-constrained hierarchical sparse attention to capture long-range dependencies along physically valid signal-propagation paths. An XOR-MUX-based auxiliary sample construction strategy is introduced to improve coverage of weakly observable fault sites. Experimental results show that GTFD achieves an average fault-prediction accuracy of 92.86%.

ABSTRACT. Static compaction is a key post-ATPG optimization for reducing deterministic pattern count, test data volume, and test application time in scan-based design for testability. In SAT-assisted static compaction, effectiveness still depends on heuristic clustering. Necessary-assignment consistency is typically used only for feasibility checking, without estimating cluster difficulty or expected compaction gain, which can waste solver effort on feasible but low-value clusters. We propose IntelliCompact, a difficulty-aware framework that combines a LightGBM-based hardness prior with a Reinforcement learning-trained clustering policy while leaving the SAT-assisted back end unchanged. Experiments preserve coverage while reducing pattern count and runtime by 7.81% and 21.23%, respectively.

ABSTRACT. As silicon systems scale, reliability is increasingly threatened by hardware defects that escape manufacturing tests. Runtime validation in data centers often requires device isolation, causing unnecessary downtime. We present an on-chip framework for continuous, in-situ health monitoring during normal operation. This framework combines spatio-temporal XOR compression with a lightweight Spiking Neural Network (SNN) to analyze microarchitectural telemetry and detect latent faults in real time. Evaluated using a gem5-based fault injection framework, our method achieves 99.3% F1 score for stuck-at fault detection with only 0.73% area and 0.53% power overhead, enabling scalable, low-overhead reliability monitoring.

ABSTRACT. This paper presents the latest advancements in our Layout-Aware Defect-Oriented Stress (LA-DOS) methodology, including an enhanced defect-based User Defined Fault Model (UDFM) generation flow (v4p2p1), a scalable ATPG pattern generation flow using the generated UDFM’s, and three new physically-grounded stress coverage KPIs: Transistor Bias Coverage%, Resistive Bridges Coverage%, and Resistive Opens Coverage%. Most importantly, we share the first largescale silicon validation of LA-DOS from a five-metric analysis of 5k+ dies across five production wafers using a checkerboard touchdown methodology comparing LA-DOS against legacy DVS stress patterns confirming production-safe yield neutrality.

ABSTRACT. ECC is mainly used for in-field soft-error correction. However, allocating a small portion of the ECC resources for hard-fail correction can greatly improve yield and reduce design-to-production time. The impact on reliability characteristics remains very small by controlling the number of error corrections at the ppm level. This type of ECC-embedded repair system requires consideration of multiple factors, such as defect level, number of faults per word, and number of specific faults identified during dedicated test phases. We reviewed different fault handling schemes in the repair flow to maximizes yield while preserving the ECC correction budget for in-field reliability.

ABSTRACT. This paper presents a flexible multi-die system-level test (SLT) architecture that leverages Tessent In-System Test Controller (ISTC) and High-Speed IO (HSIO) to deliver deterministic Automatic Test Pattern Generation (ATPG) patterns through high-speed functional interfaces such as Peripheral Component Interconnect Express (PCIe). The proposed architecture overcomes traditional Automatic Test Equipment (ATE) bandwidth limitations and supports manufacturing, system-level, and in-field testing. By enabling flexible Streaming Scan Network (SSN) datapath configurations, it validates both intra-die and inter-die test paths in multi-die systems. Silicon results demonstrate the feasibility of the proposed approach and confirm reliable, cost-effective ATPG pattern delivery under realistic operating conditions, improving defect coverage, product reliability, and yield learning.

ABSTRACT. Dual edge clocking is increasingly used in high performance processors to reduce clock frequency and dynamic power. Silicon results on a 2 nm technology node show that single edge and dual edge clocked SRAM arrays, despite sharing the same fundamental design, exhibit different minimum operating voltage behavior and therefore require different timing margins. Dual edge arrays further demonstrate higher sensitivity to clock duty cycle, with instance to instance variation in optimal centering. These effects make global duty cycle tuning for a chip challenging and expose limitations in conventional test and design margining assumptions.

ABSTRACT. Assurance testing for critical FPGA designs includes verifying the absence of Hardware Trojan Horse (HTH) circuits inserted directly into bitstreams, bypassing established netlist-level countermeasures. Bitstream Equivalence Checking (BEC) tests whether the bitstream is physically and logically equivalent to a trusted netlist verified with established methods. This work presents the methodology for creating a benchmark set that composes a diverse array of exploited bitstreams with simulated bitstream-level HTH insertion from a library of independent trigger, payload, and golden circuit designs. The efficacy of a BEC tool in detecting HTH insertions is then evaluated against the benchmark set.

ABSTRACT. We present \textit{UniWADS}, a fab-ready framework for zero-shot anomaly detection and segmentation in wafer and SEM inspection for high-volume semiconductor manufacturing. Traditional automated optical inspection (AOI) pipelines rely on hand-crafted rules or class-specific training, limiting scalability across products and process conditions. \textit{UniWADS} performs image-level anomaly detection and pixel-level localization in a single reconstruction-based architecture following a constrained reconstruction principle: robust detection requires stable token correspondence and controlled decoder capacity. The system integrates a frozen EfficientNet-B4 encoder, lightweight SpatialAdapter decoder with softmax attention, a zero-parameter Noisy Bottleneck, and a hard cosine reconstruction objective to amplify defect-sensitive discrepancies. Evaluation on Texture-AD Wafer and MIIC/IC microscopy datasets achieves 82.46\% pixel-AUROC and 58.36\% AUPRO, demonstrating a practical, deployable solution governed by the capacity--correspondence trade-off.

ABSTRACT. Growing core counts and declining chip pin availability on today's SOC designs make concurrent core testing difficult and lead to long test times. SSN enables optimized packet-based scan data delivery and simultaneous testing of multiple cores. High-bandwidth IJTAG leverages SSN to simultaneously deliver data to numerous IJTAG networks. Generic data streaming uses the full bandwidth of the SSN bus to deliver non-scan data to a single or multiple target(s). This paper describes Intel’s deployment of these technologies in their next-generation multi-die client CPU. First silicon data illustrates how Intel reduced their overall test application time across their manufacturing test flows.

ABSTRACT. Current designs with tens of chiplets lead to challenges for design for test (DFT) in terms of test time and test data volume. As design sizes have grown, we started looking at alternatives for our scan distribution network. Historically, AMD has used scan routing fabric (SRF). We explore using a third-party solution from Siemens called streaming scan network (SSN), enable SSN to perform hyper-throttling to try to improve scan bandwidth for these huge designs.

ABSTRACT. Testing large and complex system-on-chips (SoCs) presents considerable challenges in achieving an optimal balance between speed and scalability, both critical to reducing operational costs and enhancing test efficiency. Packetized scan data delivery is a trending common practice for efficient delivery of test-pattern data. If the availability of the Fast-IO interfaces can be exploited and be used in combination with the streaming scan network (SSN) bus, the overall test time can be reduced significantly. This poster explains how SSN Fast IO configuration helped achieve that for Microsoft AI accelerator design Maia200.

ABSTRACT. As automotive SoCs move to smaller geometries, screening of latent defects becomes increasingly difficult where such defects may be undetectable during specification time zero device testing. Very Low Voltage Level (VLV) Testing is a proven method to detect such defects. Here we present the challenges we encountered to enable VLV testing in a production environment, experiments performed and the final production solution. The goal is to test the devices at the lowest core voltage levels and at the fastest shift frequency, to achieve cost efficient quality.

ABSTRACT. This paper presents a scalable methodology for test program development and debug of Streaming Scan Network (SSN)-based automotive N5 SoCs targeting zero-DPPM quality by leveraging Teradyne ATE (UltraFLEXplus) and IG-XL features with custom enhancements such as core aliasing, stackable templates, and advanced fail logging which enables efficient multi-core testing and improved per-core observability without additional pattern overhead.

ABSTRACT. Bringing AI agents into semiconductor test takes more than a coding assistant. It takes a generic, extensible system that spans the test architecture, from the AI client down to the instruments, and keeps every agent action grounded in the tester's hardware. We present such an architecture. Agents reach the platform only through an open agent-to-tool protocol, and a grounding gateway holds a live model of the instrument configuration and limits and validates every action against it before it runs. Around the gateway the architecture defines typed platform tools and connectors, a multi-layer memory with gated knowledge promotion, and dual-index retrieval, each independently extensible. Everything runs on-premises. We report a first MCP-based implementation, the foundation of a longer effort.

ABSTRACT. Traditional Automated Test Equipment (ATE) test program development relies heavily on manual, error-prone, and sequential workflows. This study introduces a novel dual-agent automation framework, synergizing Codex for high-level reasoning and audit with Claude Code as an operational agent, driving a paradigm shift from "Chatting AI" to "Operating AI." By interfacing directly with Command-Line Interfaces (CLI) and ATE project environments, the framework autonomously orchestrates framework conversion, Part Name Management (PNM) tool execution, and pattern replacement. Featuring stateless adversarial code review and real-time self-healing fault tolerance, the pipeline reduces total execution time from 60+ minutes to under 15 minutes while drastically minimizing human error and ensuring exceptional operational stability in R&D and production engineering.

ABSTRACT. Packetized scan delivery moves test stimulus and response as fixed-width packets across a shared bus of width B to per-core scan hosts, one packet per shift cycle, so many cores shift concurrently instead of loading one at a time. On-Chip Compare (OCComp) adds an in-chip comparator at each scan host (expected value under a mask), letting N identical cores share a single stimulus/expected/mask packet rather than one packet per core. The result: test data volume that is essentially constant in N. We derive the packet payloads, the split-packet bus-transfer model, and the volume/time reduction factors; establish the break-even core count; quantify the diagnosis-vs-volume trade-off; and compute the absolute test data volume (TDV) and test application time (TAT).

ABSTRACT. Driven by more advanced and complex AI applications, chip sizes have increased rapidly. Consequently, the Gross Die Per Wafer (GDPW) decreases, reducing the total failing die count screened by ATPG for a given wafer volume. This scarcity degrades silicon diagnosis accuracy, hindering defect identification essential for yield optimization and DPPM reduction. Furthermore, conventional diagnosis cannot detect transistor-level defects, a critical bottleneck as process technologies transition to vertical stacking structures. To tackle these challenges, a novel Cell-Aware Diagnosis (CAD) flow is proposed. Its effectiveness is proven on the most advanced process node used by latest Cloud ASICs through highly accurate suspect localization and successful Physical Failure Analysis (PFA) hits.

ABSTRACT. As Wi-Fi 7 advances to 7GHz, FW-driven RF ATE testing is widely used but creates a critical gap while bench validation uses full-stack dongle host drivers, and ATE setups operate driverless concealing root cause from firmware misalignments or high-frequency hardware limitations. This poster presents a Hardware-Software Co-Debugging architecture to systematically resolve this black box. First, a GPIO handshake halts FW execution, enforcing an identical static state across platforms for deterministic register co-analysis. Second, we correlate and optimize the ATE load board's S11 with bench measurements, and shifting parasitic resonance away from the 7GHz band. This breakpoint-driven methodology precisely isolates dynamic software interference from physical hardware impact, hence shorten new product debugging time from weeks to days.

ABSTRACT. In modern chips, memories consume a significant portion of silicon area and are more susceptible to silicon defects than standard logic cells. Robust test requires accessing a memory at speed with no stall in accessing the addresses. Memory testing employs parallel execution, to save time. This at-speed access without stalling and testing memories in parallel makes power consumption a critical factor in the silicon design and scheduling the memory test program. Exceeding power limits can introduce false failures or worse damage the silicon. Accurate early estimation of memory peak power during MBIST is crucial for power grid design and MBIST scheduling. This poster presents a novel technique to estimate memory peak power during MBIST early in the design cycle.

ABSTRACT. Hardware Trojans (HTs) inserted after design sign-off do not appear in the golden netlist, making them difficult to detect by structural comparison alone. Power side-channel detection addresses this problem by comparing the measured power of the fabricated chip with the expected power of an HT-free design. AdaTrust adaptively modifies automatic test pattern generation (ATPG) patterns to magnify a suspicious power signal, then applies test-pattern superposition to suppress process-variation effects. Its pattern construction, however, follows a sequential, local procedure and does not explicitly compare multiple modification paths with respect to a common objective. This paper formulates the refinement and superposition-pair construction steps as a combinatorial search and applies a beam search algorithm to retain multiple promising modification paths.

ABSTRACT. Superconducting quantum computers require control circuits that operate near the qubit array to reduce wiring between room-temperature electronics and the qubits.Reliability data measured at 300K cannot be used to infer aging at cryogenic temperatures, because MOSFET characteristics and degradation rates change with temperature.This work focuses on hot-carrier injection (HCI), in which channel carriers accelerated by a high electric field are injected into the gate oxide, thereby creating defects. Prior measurements have reported larger hot-carrier degradation at cryogenic temperatures than at room temperature .We apply HCI stress to 65-nm nMOS transistors at 300K and 6K, then investigate its impact on analog circuit design by showing measured shifts in an analog design metric and the gatea rea required to recover pre-stress gain.

ABSTRACT. The increasing complexity of modern SoCs, driven by numerous functional blocks and high-pin-count interfaces for external devices and chiplets in 2.5D/3D packages, has significantly increased production test time. A key bottleneck is the conventional GPIO-based ATE interface, typically limited to a few hundred megahertz despite modern ATE platforms supporting ~10× higher throughput. This work presents a High-Speed Test I/O architecture optimized for ATE-based testing. Leveraging ATE synchronization and voltage-tracking capabilities, HSTIO eliminates protocol overheads such as CDR, encoding, calibration, and training required by interfaces like USB, DDR, and PCIe. The architecture supports configurable SDR/DDR transmit and receive lanes, enables on-chip clock observation up to 2.5 GHz, and reuses pins as low-power GPIOs, providing a compact, scalable solution for SoC testing.

ABSTRACT. Post-fabrication optimization is essential for achieving target cell distributions in NAND flash memory by tuning device parameters after manufacturing. Existing methods combine deep learning (DL) models with genetic algorithms (GAs), using DL models to generate promising initial solutions for GAs. However, DL models generate high-quality initial solutions only when trained on near-optimal samples, and their performance degrades substantially when only randomly sampled data are available. We propose a post-fabrication optimization framework robust against initialization quality. The proposed framework redesigns the objective function to provide a more favorable optimization landscape and replaces the GA with the Improved Newton–Raphson-Based Optimizer (INRBO). Experimental results show that the proposed method consistently outperforms prior approaches, particularly under poor initialization, demonstrating improved robustness.

ABSTRACT. Integrity verification of fabricated chips is increasingly important in a distributed IC supply chain, where layout modifications, such as cell insertion, deletion, or modification, may occur. Power-based verification is attractive since it is non-intrusive and can capture partially activated modifications, yet the power difference is small and easily masked. To make this difference more detectable, this paper investigates bit-width reduction, an approximate-computing technique, as a means of enhancing power-based integrity verification of gate-level netlists. Using an MLP inference engine on the MNIST dataset, we analyze the trade-off between inference accuracy and the relative power difference (RPD). We experimentally confirmed that reducing the weight bit-width from 8 to 4 bits increases RPD by 37.0\% with only a 0.27 percentage-point accuracy loss.

ABSTRACT. Integrity verification of a fabricated chip is increasingly important in a distributed IC supply chain, where unauthorized modifications may occur during the manufacturing phase. Power-based verification is attractive since it can be applied non-intrusively and can capture modifications even when they are only partially activated, yet the resulting power difference is typically small and easily masked. To make this difference observable, we repurpose automatic test pattern generation (ATPG) to induce localized switching by partitioning the fault list and applying a switching-activity budget. The impact of a modification is then quantified by the Relative Power Difference (RPD). On a multilayer perceptron with a hardware Trojan, the proposed method generally enhanced the maximum RPD over conventional ATPG.

ABSTRACT. Modern chips impose stringent low-power ATPG requirements, requiring advanced DFT hardware and ATPG methods to control scan-shift power [1]. These controls are critical for preventing power-induced damage, protecting long-term silicon reliability, and improving yield by reducing false failures caused by IR-drop and local voltage droop. Although scan compression reduces test time and cost, it also increases scan-switching activity and complicates power-failure debug. Extended ATPG Scan Power Controls enable ultra-low-power scan shift and support targeted pattern generation that can isolate power-related silicon failures beyond traditional simulation-only approaches. This poster presents extended ATPG scan power controls to enable ultra-low power scan shift and advanced ATPG patterns to isolate and debug silicon power failures beyond traditional power simulation techniques.

ABSTRACT. This poster presents a telemetry framework for observing workload activities associated with voltage droop events in SoCs using time-aligned traces. This framework was implemented using the Movellus Aeonic Insight™ voltage monitors with Siemens Tessent UltraSight functional monitoring infrastructure integrated with RISC-V Rocket cores. Low-latency triggering captures time-aligned traces of processor, interconnect, signal and bus activity, enabling workload-aware root-cause analysis of voltage droops for in-field debug and monitoring.

ABSTRACT. Standard EDA tool flows assume full RTL ownership of the TAP controller,an assumption violated when the TAP controller is delivered as a hardmacro.This poster presents a methodology in which control signals generated by a 3rd Party TAP hardmacro are reused within a custom wrapper TAP to enable IEEE 1149.1 boundary scan insertion using standard EDA tool. The custom wrapper TAP, with its own opcode set, FSM, and interfaces, was designated as the primary TAP.Its Instrument Connectivity Language (ICL) description was extended to declare the full host BSCAN interface, a host_bscan_from_so opcode, and dft_tap_idcode opcode.The resulting BSCAN chain was further extended to a 2.5D assembly comprising a center die and a satellite die, connected in series through an interposer.

ABSTRACT. Automatic Test Pattern Generation (ATPG) coverage debug is a complex, time-consuming task. This work introduces Agentic AI, an AI solution that uses orchestrator agents and skills to automate coverage debug. Integrated into a DFT application through the Model Context Protocol (MCP), the system analyzes the fault universe, identifies coverage gaps, and autonomously executes ATPG-related tasks. Experiments on a real design show measurable improvement in test coverage. This method accelerates the DFT ATPG cycle and enables transition from static execution to a more dynamic and intelligent workflow.

ABSTRACT. Progressive threshold voltage drift in MOSFET-based analog ASICs present a reliability threat. The electrical signatures are invisible at final test yet devastating to long-term circuit functionality. Post-silicon diagnosis combining FIB analysis, characterization, and simulation identified a root cause. Safe Operating Area (SOA) violations that subject gate oxides to chronic overstress, accelerating Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) and degradation. Standard simulation failed to predict these overstress conditions. We present the diagnostic methodology, validated workarounds, and targeted design corrections. Findings motivate SOA analysis and aging model integration as essential pre-silicon verification steps for analog IC designs.

ABSTRACT. Wafer-scale compute systems presents significant challenges in manufacturing yield, fault tolerance, and long-term reliability. The Cerebras Wafer-Scale Engine (WSE) addresses these challenges through a distributed redundancy architecture and comprehensive system-level Design-for-Test (DFT) infrastructure. During manufacturing and system initialization, DFT patterns identify defective compute resources and interconnects, generating a defect map for hardware-assisted repair and logical remapping. Redundant cores and routing links enable transparent bypass of defective regions, exposing a contiguous logical compute fabric to software. The same DFT framework supports periodic in-field diagnostics and re-repair, improving Reliability, Availability, and Serviceability (RAS) while maximizing effective manufacturing yield and operational lifetime.

ABSTRACT. Despite functional and structural testing to minimize defect-parts-per-million, massive server fleets and rising transistor densitiest suffer from Silent Data Corruptions (SDCs) caused by defective devices with unpredictable frequency. To address this, the proposed methodology uses an evolutionary engine to mutate the abstract-syntax tree representation of high-level functional test code targeting SDCs for increasing the repeatability of failing test programs. This approach explores diverse source code modifications derived from a common ancestor.

ABSTRACT. Packet-based scan delivery architectures, such as the Tessent Streaming Scan Network (SSN), decouple core-level test requirements from chip-level test resources, dramatically reducing manufacturing test data volume and test time. However, introducing flexible network routing by inserting multiple multiplexers (mux) creates exponential topology permutations for SSN connectivity verification, making manual configuration difficult. This paper introduces an automated framework that generates mux configurations using graph computing approach. Evaluation results from reference System-on-Chip (SoC) designs demonstrate significant configuration-time savings and maximized test coverage.

ABSTRACT. Modern processor verification struggles to reach deep architectural states due to the inefficiencies of traditional mutation-based fuzzing. We propose HiFuzz, a novel hierarchical reinforcement learning framework that replaces mutation with a structured, two-layer generation process: a Program Agent for global layout and a Basic Block Agent for precise instruction filling. To overcome reward sparsity, HiFuzz integrates an adaptive coverage reward mechanism and a semantic-aware basic block encoder providing intrinsic feedback. Extensive evaluations on real-world RISC-V processors demonstrate that HiFuzz significantly outperforms state-of-the-art fuzzers in coverage and bug detection.

ABSTRACT. Resistive defects in scaled FETs often escape standard structural testing. While multi-VDD testing can expose these defects, exhaustive SPICE-based simulation is computationally expensive across diverse defect sites, resistances, and VT flavors. To address this, we propose a spatio-temporal deep learning framework to predict SPICE-accurate waveforms of standard cells with transistor-level defects. We model netlists as heterogeneous graphs using a Graph Attention Network with ATPG-inspired topological features. To capture timing effects, we employ a self-attentive Temporal Convolutional Network, replacing SPICE with high-speed, GPU-accelerated time-domain predictions. We perform defect classification and test compaction, accelerating defect coverage analysis and cell-level test pattern optimization.

ABSTRACT. The aggressive shrinking of transistors at advanced nodes increases physical defects, especially in Back-End-of-Line (BEOL) interconnects, where conventional ATPG lacks physical test coverage. This paper details the novel approaches of devising physical test coverage metric for a design, intelligent extraction and identification of sensitive layout shapes, ML based categorization with physical testability enhancement techniques, inter-metal layer bridge sites extraction, targeting and diagnosis. Validation on test vehicles demonstrates marked increases in physical test coverage and successful identification of unique defect sites, highlighting the necessity of these advanced test and diagnosis strategies for yield learning.

ABSTRACT. This paper proposes a Built-In Self-Calibration scheme for enhancing the linearity of a time-to-digital converter (TDC) used for accurate clock period measurement of the clock signal produced by an All-Digital Phase-Locked Loop (ADPLL). We achieve our goal by treating the TDC and ADPLL as a "combo circuit" with two main features: (1) One-Way Varactor Cells (OWVCs) for resolution adjustment in the TDC, (2) a transfer-function-linearization process using the training clock signals produced by the ADPLL. Post-layout simulation reveals that the measurement error of the minimum clock period sample can be effectively reduced from 7.03 ps to 1.28 ps.

ABSTRACT. This paper presents results for the first silicon implementation of analog scan-based design-for-test (DfT) and automatic test pattern generation for a 12-bit SAR ADC in a 65 nm technology. The DfT consists of an IJTAG test data register, digital multiplexers, analog stimulus transistors, and analog scan inverters, to control and observe ports of the ADC and nodes deep inside it. The DfT had minimal impact on the ADC’s performance. The analog scan results were stable across process corners, supply voltages, and stimulus frequencies, and high coverage testing of defect free and intentionally defective devices was achieved in sub-millisecond test times.

ABSTRACT. Burn‑In (BI) is a critical reliability screen for semiconductor devices but adds substantial cost due to long stress times and repeated test insertions. This work introduces a production‑ready, data‑driven framework for adaptive BI reduction using an ensemble of ML models (RF, XGB, MLP). Leveraging FAB, wafer sort, and final test data, the system enables per‑device BI‑skip decisions at a pre‑BI FT insertion under a strict zero‑escape requirement. A model‑driven feature‑selection method supports scalable deployment across complex products. Validation on >500k training and >200k test units demonstrates over 25% BI cost reduction while maintaining outgoing quality.

ABSTRACT. The complexity of modern hardware systems creates a large surface for information flows that break the confidentiality or integrity of classified information. Current approaches to detecting malicious information flows, such as information flow tracking, lack scalability to complex computing systems or compromise accuracy. This paper proposes DiamondBlade, a generalized and precise information flow tracking approach based on formal verification. DiamondBlade extends a 2-instance computational model with optimizations, enabling it to scale to complex systems and provide formal security guarantees. We demonstrate DiamondBlade in case studies on an AES implementation, the Caliptra HMAC unit, the BOOM processor and the Pulpissimo SoC.

ABSTRACT. This paper presents a concurrent fault simulation methodology tailored for timing-critical and transistor-level memory peripheral circuits. Existing concurrent fault simulators support only zero-delay abstraction, and extending them to annotated delay models poses two challenges: temporal divergence may occur without logic value divergence, and delay selection depends on passive timing state that lacks explicit fanout for event-driven tracking. The proposed method addresses these challenges by extending divergence tracking to a two-dimensional space spanning both logic values and temporal state, independently maintaining passive timing contributors within faulty machines, and establishing hierarchical port fault semantics with injection flags that constrain fault effects within switch-level hierarchies. Validation on industrial DRAM circuits demonstrates an average simulation speedup of approximately 44× while maintaining a maximum coverage delta of less than 0.17% compared to the serial simulation mode.

ABSTRACT. Cell-aware test (CAT) characterization is often hindered by the high cost of SPICE simulations. While structural analysis can prune these simulations, prior methods like TrUnDeL focus on identifying structurally undetected cases and overlook significant optimization opportunities. We propose GroStra, a framework that enhances efficiency through three strategies: defect equivalence-Based simulation pruning, guaranteed-detected structural analysis, and using static analysis to accelerate dynamic graph processing. Experimental results on ASAP7 and 12nm libraries demonstrate that GroStra reduces simulation effort by up to 25.4% and 32.6% over TrUnDeL and achieves up to a 15x and 55x speedup, significantly lowering characterization costs without sacrificing accuracy.

ABSTRACT. Compute-in-memory (CiM) architectures have emerged as an effective solution to mitigate the data-movement bottleneck in modern computing systems. Among emerging memory technologies, MRAM is particularly attractive for CiM-based deep neural network accelerators due to its high density and energy efficiency. However, the integration of memory and computation introduces new security concerns. In this work, we analyze the vulnerability of MRAM-based CiM architectures to side-channel attacks that may expose stored DNN weights. To address this threat, we propose LEO-CiM, a lightweight execution obfuscation framework that perturbs computation patterns while preserving correctness, thereby significantly hindering an attacker’s ability to infer sensitive information.

ABSTRACT. This work proposes LPLL, a novel approach of linear programmingbased logic locking. LPLL reformulates key-gate selection problem as a linear optimization task to explicitly maximize output obfuscation. It innovatively translates boolean logic to linear expressions, and iteratively identifies key gate positions under quantitative objective functions. Evaluated on ISCAS-85 benchmarks, the proposed LPLL achieves about 95% corrupted output patterns.

ABSTRACT. Co-Packaged Optics (CPO) is emerging as a key technology to overcome I/O bottlenecks in data-center and high-performance systems by tightly integrating photonic and electronic components. While CPO improves bandwidth density and energy efficiency, it introduces unexplored physical attack surfaces. This paper presents the first pre-silicon electromagnetic fault injection (EMFI) vulnerability analysis framework for CPO systems. Leveraging multi-physics co-simulation across electromagnetic, thermal, and electrical domains, we analyze photonic integrated circuits and their control loops. Results show that EM-induced currents can disrupt microring thermal control, causing a change in the resonance wavelength up to 1.13 nm, which eventually leads to data corruption.

ABSTRACT. Modern flexible hardware systems demand real-time anomaly detection. We present JAMS, a JTAG-based monitoring framework for RISC-V processors that captures runtime state (registers and performance counters) via debug access. Using unsupervised techniques like PCA and outlier detection on time-series data, JAMS identifies deviations from benign execution without prior labeling. Unlike prior software-based HPC approaches, JAMS is an immutable hardware coprocessor. Implemented on a 64-bit dual-issue core on a Xilinx Versal SoC-FPGA and evaluated with cryptographic benchmarks, it achieves a median F1-score of 0.99, demonstrating robust detection of malicious microarchitectural behavior.

ABSTRACT. Resistive Random-Access Memory (ReRAM)-based computing-in-memory (CIM) architectures offer a promising path beyond von Neumann systems by reducing data movement, thereby improving energy efficiency. However, these architectures face significant challenges from temperature variations, which shift resistance states, degrade resistance ratios, and ultimately increase computational errors by perturbing the output currents. We first identify the temperature-sensitive component by analyzing real device-level measurement data. We then develop an analytical framework and design a temperature-aware compensation circuit that mitigates variations in the output current. We benchmark our methodology using VGG16 on CIFAR-10 and achieve up to 92.4% accuracy with only ±0.4% variation across -25°C-125°C.

ABSTRACT. Silicon photonic integrated circuits (PICs) offer exceptional bandwidth and energy efficiency, but their analog, wave‑based behavior makes scalable manufacturing test challenging. This paper presents a defect‑oriented, optimization‑driven automatic test pattern generation (ATPG) framework for silicon PICs that targets parametric, catastrophic, and environmental variations. Fabrication and operating variability are captured within a structured convex parameter space, and passive, analytically differentiable transfer‑matrix surrogates are used to pose ATPG as a maximin stimulus search that maximizes worst‑case defect observability under per‑channel measurement noise and bounded process/environment drift. We evaluate our ATPG on three PIC benchmark designs.