Program for Wednesday, October 14th: Talk View

PROGRAM FOR WEDNESDAY, OCTOBER 14TH: TALK VIEW

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9:00

9:30

10:00

10:30

11:00

11:30

12:00

12:30

13:00

13:30

14:00

14:30

15:00

15:30

16:00

16:30

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17:30

18:00

09:00-10:00 Automotive Chiplets: Testing the Seams That Hold AI-Driven Vehicles Together

10:30-10:40

IEA-Pro: From Analytics to Interactive Analytic Stories

Seoyeon Kim, Li-C Wang

10:40-10:50

Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons

Chen He, Todd Jacobs, Jialei He, Yu Su, Wells Lu, Li-C. Wang

10:50-11:00

Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8

Sohail Haroon

11:00-11:10

Scalable, Secure Chat-Based Analytics for Semiconductor Test

Michael Schuldenfrei, Eran Rousseau, David Kantorovich

10:30-10:40

Closing the Debug Loop: An LLM Agent That Root Causes Silicon Failures

Mickey Tadesse

10:40-10:50

Scan RTL DRC Fix Agent

Sujay Pandey, Pankaj Pant, Venkat Ramakrishnan, Arani Sinha, Chaitali S Oak

10:50-11:00

AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis

Koon Meng Ang, Jin Giap Koh, How Chun Ng, Kenny Kal Vin Toh

11:00-11:10

Toward Scalable AI-Driven SCAN Debug and Yield Learning

Cesar Acero Romero

11:10-11:20

Transforming Failure Analysis Retrieval with Generative AI for Product Qualification

Suhrita Mukherjee, Deepika Neethirajan, Jada Ballentine

10:30-12:00 Corporate Presentation by Platinum Supporter

10:30-10:40

Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering

Esteban Garita-Rodriguez

10:40-10:50

DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation

Calvin Tan

10:50-11:00

PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development

Garrett Cooper, Sudheer Korlam, John Delos Reyes

11:00-11:10

AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification

Shyam Sharma, Dharini Subashchandran, Gruhesh Patel, Meghna Ahuja

11:10-11:20

From Prompt to Outcome: A Domain-Grounded Multi-Agent Framework for Semiconductor Test Analytics

Prasanna Kumar Chittari, Sergio Mier, Lokesh Subramany, Saswati Giri

10:30-10:50

Machine Learning Techniques for Microcontroller Performance Screening

Nicolò Bellarmino

10:50-11:10

From Threat Models to Scalable Methodologies for Formal Hardware Security Analysis

Anna Lena Duque Antón, Wolfgang Kunz

11:10-11:30

Test and Diagnosis for Hardware Trust: Securing FPGAs and Analog/Mixed-Signal Designs

Jayeeta Chaudhuri, Krishnendu Chakrabarty

12:00-14:00 AI Track: AI User Forum Poster & Lunch

12:00-14:00

Memory Characterization using Advanced Pattern Rank-Trajectory Analysis (PRTA) utilizing state-of-the-art Frequency-Voltage (Shmoo)

Hazari, Penmatsa, Gomez Soza, Marin Gonzalez, Pandya, Irkar, Kumar Tripathi

Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing

C.C. Pan, C.K. Chang, C.W. Wang, H.T. Peng, J.T. Chen, W. Teoh, J. Chen

Electro-Thermal Analysis and Design Approach for High-Power HPC Device Interface Boards

Chien-Hui Huang, Jia-Yan Huang, Chih-Wei Wu, Hung-Hsi Tseng

DEFECTIVE DIE COUNT (DDC) FOR YIELD FORECASTING AND SEMICONDUCTOR FABS DEFECT DENSITY CONTROL

R. Salem, S. Huang, E.C.-H. Cheng, V. Ho, T. Tzeng, L. Yao

AI based Multi-modal Feature Clustering Technology for Wafer Root Cause Analysis

T. Liu, P. Guo, Z. Shen, Y. Chen, L. Yu, C. Ren, J. Huang

In-Situ TDR Test Fixture for End-to-End Signal Integrity Characterization and Debug in Rack-Scale

Sean Chen, Jack Viola

FORENSIC ANALYSIS OF I2C BUS INSTABILITY LEADING TO FAILURES IN MULTI-ASIC INFINIBAND SWITCH

Sreya Choudhury, Sean Chen

GTFD: A Graph-Based Sparse Attention Model for Fault Prediction in Digital Circuits

L. Zhang, X. Liu, Z. Wang, D. Yan, Z. Cai, Z. Gao, X. Wen, Y. Guo

IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets

Yan, He, Guo, Wang, Wang, Xu, Li, Cao, Song, Cai, Wen, Guo

In-field Monitoring of Permanent Faults in AI Accelerators Using Spiking Neural Networks

Yuanqi Yu, Fei Su

ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive

Ramesh, Brahmi, Dworak, Sun, Thota, Anjaneyareddy, Ganesh, He, J N, Dharmavaram

Combined ECC and repair strategies for yield enhancement

Jongsin Yun, Luc Romain, Wei Zou, Paul-Patrick Nordmann, Albert Au, Martin Keim

A Flexible Multi-Die System-Level Test Architecture Leveraging In- System Test Controller (ISTC) and High-Speed IO

I. Chou, B. Wang, M. Yang, P. Orlando, J. Castrence, W. Yang, J. Fan, R. Chen

Implementation Challenges of Dual-Edge Triggered SRAMs in High-Performance Processors

Uma Srinivasan, Philipp Salz, Philip Beck, Michael Kugel, Holger Wetter

Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods

F. Archuleta, J. Koiner, A.A. Sohanghpurwala, W. Batchelor, J. Graf, S. Harper

Fab-Ready Zero-Shot Anomaly Detection and Segmentation for Wafer and SEM Inspection

Shih-Chih Lin, Yuntung Chu

Test Strategies on Intel’s Next-Generation Multi-Die Client CPU

Tim Callahan, Jonathan Gaudet, Lori Schramm

Siemens Streaming Scan Network Comparision with Legacy Scan Routing Fabric

Tassanee Payakapan, Arie Margulis, Rahul Malhotra, Abhilash Kaushal, Ripu Singh

Fast-IO DDR for High Bandwidth SSN: Enabling Scalable DFT for Large SoCs

Jagjot Kaur, Mujeeb Syed, Kathy Yang, Claudia Muia-Tartevet

Enabling Full Capability of Very Low Voltage (VLV) Scan Testing in Automotive SoCs

Archana Jain, Emen Cloyd, Stephen Traynor, Stefano Larentis

Test Program Development and Debug Methods for SSN Productization on Zero DPPM Automotive N5 SoC

Archana Jain, John Gatej

From Test Floor to Thinking Floor: A Hardware-Grounded Architecture for AI Agents in Semiconductor

Mykola Zakharchuk

From Chatting to Operating: An AI-Agent Framework for Automated Test Program Generation

Chao-An Li, Zong-Han Li, Pei-Lun Hsu

Theoretical Limit Calculation: Packetized Scan Delivery with On-Chip Compare (OCComp) for N Identical

Mahmoud Abdalwahab, Ron Press

Precise Detection of FEoL Defects Using Cell-Aware Diagnosis

Anti P.H. Tseng, Hanson H.C. Peng, Emma H.Y. Chou, Joe Y.J. Chiu

Bridging ATE and Bench: A Breakpoint-Driven Debug Architecture for 7GHz WLAN Firmware Integration

Kate Cheng, Lalitha Abraham, Vishnu Karuvacheryveedu

Novel Technique To Estimate Memory Peak Power During MBIST

Mohit Madaan, Puneet Arora, Norman Card, Carl Wisnesky

Optimization-Based Refinement of ATPG Test Patterns for Power-Based Hardware Trojan Detection

Aoi Hayashi, Hajime Takayama, Alex Orailoglu, Michihiro Shintani

Cryogenic Hot-Carrier Degradation in 65-nm nMOS Transistors and Its Impact on Analog Circuit Design

K. Yumiba, H. Takayama, T. Suzuki, C. Tanaka, M. Shintani

Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O

Arpit Vijayvergia, Surendra Kumar, Nitin Bansal, Mohit Garg, Kunal Lakhani

Post-Fabrication Optimization for NAND Flash Memory Robust to Initial-Solution Quality

Soonwon Jeong, Yulhwa Kim

Effectiveness Evaluation of Bit-Width Reduction in Power-Based Integrity Verification of Gate-Level

Haruto Tokunaga, Asuka Koike, Yutaka Masuda, Tohru Ishihara

Localizing Switching Activity in ATPG for Power-Based Integrity Verification of Gate-Level Netlists

Asuka Koike, Haruto Tokunaga, Yutaka Masuda, Tohru Ishihara

ATPG Extended Scan Power Control for Silicon Power Analysis

Carl Wisnesky II, Martin Amodeo, Brion Keller, Nitin Sharma

Real-time voltage droop detection and functional monitoring telemetry for diagnosing and debugging

Robert Wilcox, Henrique Mendes, Hari Mani, Farid Hamraz

A Scalable and Flexible Test Access Port (TAP) Architecture for Chiplet-Based Systems

Kaushik Mandal, Bryan Wang, Mateusz Sienkiewicz, Ajay Purushotham

ATPG Coverage Debug: The Shift to Agentic AI

Lana Pantskalashvili, Mahmoud Abdalwahab, Ron Press

Poster Submission: Post-Silicon Diagnosis of SOA-Induced Threshold Voltage Drift

Hailin Wang, Sunny Xu, Matthew Kusbit

Wafer Scale RAS Solution: Redundancy and System DFT in Cerebras WSE

Supratik Misra, Junaid Shaik

Evolutionary techniques for high-level source of functional test programs

F. Angione, P. Bernardi, G. Filipponi, T. Macieira, A. Sinha

Accelerating Bus Connectivity Verification for Packet-Based Scan Delivery Network

Jiqing Fan, Yemi Olukade, Aaron Jin, Charles Njinda, Ben Gribstad

Learnings from PCIe Gen6 Bring-up and Debug for GPU Systems

Sean Chen, Ameet Sanghavi, Victor Castillo, Amarildo Garcia, Frank Chang

14:00-15:00 Breaking the Thermal Barrier: Next-Generation Thermal Challenges for High-Power Semiconductor Test

15:30-16:00

HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing

Ya Wang, Hanwei Fan, Zhenguo Liu, Xiaofeng Zhou, Yangdi Lyu, Jiang Xu, Wei Zhang

16:00-16:30

SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard

Gowsika Dharmaraj, Anurup Saha, Abhijit Chatterjee, Adit Singh

16:30-17:00

AI driven BEOL Testable Layout Pattern Enrichment

Puli Surya Tej Reddy, Sandeep Kumar Goel, Ankita Patidar, Frank Lee

15:30-16:00

Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement

Chih-Chia Hsu, Shi-Yu Huang

16:00-16:30

A Silicon Validation of Analog Scan Testing

W. Dobbelaere, A. Coyette, D. Dima, A. Billa, K. Jurga, V. Zivkovic, S. Sunter

16:30-17:00

Adaptive Burn-In using Ensemble Learning

Sanket Vinod Thakur, Sergio Mier, Sule Ozev

15:30-17:00 Special S3 - In-System Test

15:30-16:00

A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing

Mickey Geftler, Shay Oliver, Bhavin V Kakani

16:00-16:30

Finding the Sweet Spot for Test Point Insertion in the Design Flow

Xiaoze Lin, Liyang Lai, Biwei Xie, Huawei Li

16:30-17:00

Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level

S. Kuttuva Ravikanth, D.A. Chatterjee, E.P.M. L. Bushnell

15:30-15:45

LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel

Pourmehrani, Balbuena, Bhanushali, Dhiman, Bishnoi, Sanyal, Firouzi, Karimi

15:45-16:00

A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking

Xiaotong Cui, Weirong Qin, Linyu Zou, Kefei Cheng, Yu Wu

16:00-16:15

A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged

Sarker et.al

16:15-16:30

JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V

Hati, Mastorakis, Bruno, Tsiropoulou, Plusquellic, Chakrabarty

16:30-16:45

TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory

Hassan et.al

16:45-17:00

Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits

Lawrence Schlitt, Priyank Kalla, Steve Blair

17:00-18:00 Session P3 - Executive Panel

10:00-10:30 Session Break (Texas Ballroom DEF)

15:00-15:30 Session Break (Texas Ballroom DEF)