ITC 2026: 2026 IEEE INTERNATIONAL TEST CONFERENCE

A
Abdalwahab, Mahmoud	Theoretical Limit Calculation: Packetized Scan Delivery with On-Chip Compare (OCComp) for N Identical Cores ATPG Coverage Debug: The Shift to Agentic AI
Abdel-Hafez, Khader	Accelerated DFT Optimization Using Compression-aware ATPG Emulation
Abraham, Lalitha	Bridging ATE and Bench: A Breakpoint-Driven Debug Architecture for 7GHz WLAN Firmware Integration
Abunahla, Heba	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Acero Romero, Cesar	Toward Scalable AI-Driven SCAN Debug and Yield Learning
Adams, Klay	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Agnihotri, Pratishtha	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
Ahmad, Baleegh	Speeding up DFT Recommendation Systems with limited-compute resources
Ahuja, Meghna	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Aljuffri, Abdullah	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
Amodeo, Martin	ATPG Extended Scan Power Control for Silicon Power Analysis
Anders, Jens	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Ang, Koon Meng	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
Angione, Francesco	Evolutionary techniques for high-level source of functional test programs A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Anjaneyareddy, Arun Kumar	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Ankush, Ankush	EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits
Arapidis, Emmanouil	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level
Archuleta, Freya	Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
Arora, Puneet	Novel Technique To Estimate Memory Peak Power During MBIST
Au, Albert	Joint ECC and Repair strategies for superior yield improvements
Aziza, Hassen	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level
B
Baek, Jaehyun	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Bailey, Christopher	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Balbuena, Brandon	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
Ballentine, Jada	Transforming Failure Analysis Retrieval with Generative AI for Product Qualification
Banerjee, Sanmitra	DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration
Bansal, Nitin	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
Bantel, Linus	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Batchelor, Whitney	Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
Beck, Philip	Implementation Challenges of Dual-Edge Triggered SRAMs in High-Performance Processors
Bellarmino, Nicolò	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Bernardi, Paolo	Evolutionary techniques for high-level source of functional test programs A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Bertani, Claudia	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Bhanushali, Sumukh	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
Bhoumik, Partho	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Bian, Yanhao	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Bian, Zhengqi	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Billa, Arlind	A Silicon Validation of Analog Scan Testing
Bishnoi, Rajendra	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Biyani, Yashvardhan	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Blair, Steve	Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits
Blanton, Shawn	DEFT: Differentiable Automatic Test Pattern Generation RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects
Boddikurapati, Sirish	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Bonsu, Godfred	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
Bormann, Jörg	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Brahmi, Mohammed Zine E.	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Bruno, Sean	JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
Burton, Brandy	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
C
Cai, Zhikuang	GTFD: A Graph-Based Sparse Attention Model for Fault Prediction in Digital Circuits IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
Callahan, Tim	Test Strategies on Intel’s Next-Generation Multi-Die Client CPU
Campbell, Michael	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context
Cantoro, Riccardo	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Cao, Mingsheng	IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
Card, Norman	Novel Technique To Estimate Memory Peak Power During MBIST
Carulli, John	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
Carulli, John	ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability
Castrence, Justine	A Flexible Multi-Die System-Level Test Architecture Leveraging In- System Test Controller (ISTC) and High-Speed IO (HSIO)
Chaganti, Shravan	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
Chakrabarty, Krishnendu	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Chakrabarty, Krishnendu	THETA: Topology-Aware Secure Boot in Heterogeneous Integration for Trust and Assurance CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
Chakrabarty, Krishnendu	ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability
Chakravadhanula, Krishna	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Chakravarty, Sreejit	DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration
Chandra, Anshuman	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing
Chang, Ching-Yi	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
Chang, Chun Kai	Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing
Chang, Norman	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Chao, Zhiteng	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Chatterjee, Dr. Abhijit	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits
Chen, Degang	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
Chen, Jc	Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing
Chen, Jian Ting	Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing
Chen, Marvin	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Chen, Reinhard	A Flexible Multi-Die System-Level Test Architecture Leveraging In- System Test Controller (ISTC) and High-Speed IO (HSIO)
Chen, Sean	In-Situ TDR Test Fixture for End-to-End Signal Integrity Characterization and Debug in Rack-Scale Systems FORENSIC ANALYSIS OF I2C BUS INSTABILITY LEADING TO FAILURES IN MULTI-ASIC INFINIBAND SWITCH ARCHITECTURES
Chen, Wei-Ren	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Chen, Yijing	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Chen, Yining	AI based Multi-modal Feature Clustering Technology for Wafer Root Cause Analysis
Cheng, Eric Chung-Hao	DEFECTIVE DIE COUNT (DDC) FOR YIELD FORECASTING AND SEMICONDUCTOR FABS DEFECT DENSITY CONTROL
Cheng, Kate	Bridging ATE and Bench: A Breakpoint-Driven Debug Architecture for 7GHz WLAN Firmware Integration
Cheng, Kefei	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
Chiu, Joe Y.J.	Precise Detection of FEoL Defects Using Cell-Aware Diagnosis
Chiueh, Herming	Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
Cho, Hwiyeol	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Choi, Hyojin	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Chou, Emma H.Y.	Precise Detection of FEoL Defects Using Cell-Aware Diagnosis
Chou, Ivan	A Flexible Multi-Die System-Level Test Architecture Leveraging In- System Test Controller (ISTC) and High-Speed IO (HSIO)
Choudhury, Sreya	FORENSIC ANALYSIS OF I2C BUS INSTABILITY LEADING TO FAILURES IN MULTI-ASIC INFINIBAND SWITCH ARCHITECTURES
Chu, Yuntung	Fab-Ready Zero-Shot Anomaly Detection and Segmentation for Wafer and SEM Inspection
Cloyd, Emen	Enabling Full Capability of Very Low Voltage (VLV) Scan Testing in Automotive SoCs
Cooper, Garrett	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
Corpino, Sabrina	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Coyette, Anthony	A Silicon Validation of Analog Scan Testing
Cron, Adam	A Methodology for AI-based Defect Detection and Localization for 3D Chiplet Interconnects
Cui, Xiaotong	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
Czernitzki, Sebastian	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
D
Delgado, Francisco	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Delos Reyes, John	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
Deutschmann, Lucas	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Devarajegowda, Keerthikumara	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Dharmaraj, Gowsika	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
Dharmavaram, Ramanath	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Dhiman, Saurabh	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
di Gruttola Giardino, Nicola	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Dima, Doina	A Silicon Validation of Analog Scan Testing
Dobbelaere, Wim	A Silicon Validation of Analog Scan Testing
Duarte, Jose Angel	Accelerated DFT Optimization Using Compression-aware ATPG Emulation
Duque Antón, Anna Lena	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Dworak, Jennifer	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
E
Esteban Rodriguez Condia, Josie	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
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Fabregat Garcia, Francisco	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Fadiheh, Mohammad R.	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Fan, Hanwei	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Fan, Jeff	A Flexible Multi-Die System-Level Test Architecture Leveraging In- System Test Controller (ISTC) and High-Speed IO (HSIO)
Fan, Jiqing	Accelerating Bus Connectivity Verification for Packet-Based Scan Delivery Network
Farahmandi, Farimah	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Faridi, Mukarram Ali	Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests
Fei, Siyang	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Fieback, Moritz	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level
Filipponi, Gabriele	Evolutionary techniques for high-level source of functional test programs A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Firouzi, Farshad	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Fowler, Aric	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
Francis, David	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Fujita, Masahiro	A Methodology for AI-based Defect Detection and Localization for 3D Chiplet Interconnects
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Gandhi, Rohit	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Ganesh, Archana	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Gao, Chengcheng	LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management
Gao, Zhipeng	GTFD: A Graph-Based Sparse Attention Model for Fault Prediction in Digital Circuits
Garg, Mohit	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
Garita-Rodriguez, Esteban	Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering
Gatej, John	Test Program Development and Debug Methods for SSN Productization on Zero DPPM Automotive N5 SoC
Gaudet, Jonathan	Test Strategies on Intel’s Next-Generation Multi-Die Client CPU Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing
Gebregiorgis, Anteneh	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Geftler, Mickey	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
Geppert, Gabrielle	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
Goel, Sandeep Kumar	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators AI driven BEOL Testable Layout Pattern Enrichment Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Gomez Soza, Jazmin	Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
Goraya, Jatinder	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Graf, Jonathan	Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
Gribstad, Ben	Accelerating Bus Connectivity Verification for Packet-Based Scan Delivery Network
Guin, Ujjwal	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Guo, Jing	IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
Guo, Pang	AI based Multi-modal Feature Clustering Technology for Wafer Root Cause Analysis
Guo, Yufeng	GTFD: A Graph-Based Sparse Attention Model for Fault Prediction in Digital Circuits IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
Gupta, Sameeksha	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
H
Hamdioui, Said	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Hamraz, Farid	Real-time voltage droop detection and functional monitoring telemetry for diagnosing and debugging SoCs
Haroon, Sohail	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
Harper, Scott	Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
Hassan, K M Shadid	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Hati, Arjun	THETA: Topology-Aware Secure Boot in Heterogeneous Integration for Trust and Assurance VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
Hayashi, Aoi	Optimization-Based Refinement of ATPG Test Patterns for Power-Based Hardware Trojan Detection
Hazari, Arnab	Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
He, Chen	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
He, Jialei	Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
He, Qirun	IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
He, Xu	RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects
Ho, Victor	DEFECTIVE DIE COUNT (DDC) FOR YIELD FORECASTING AND SEMICONDUCTOR FABS DEFECT DENSITY CONTROL An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Hroub, Ayman	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
Hsieh, Cheng-Yun	Decision Diagram-based Fault Simulator for Quantum Circuits
Hsieh, Chi-Jui	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Hsu, Chi-Hsing	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Hsu, Chih-Chia	Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement
Hsu, Pei-Lun	From Chatting to Operating: An AI-Agent Framework for Automated Test Program Generation
Hua, Erbing	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Huang, Bo-Lin	Decision Diagram-based Fault Simulator for Quantum Circuits
Huang, Chien-Hui	Electro-Thermal Analysis and Design Approach for High-Power HPC Device Interface Boards
Huang, Hsuan-Ming	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Huang, Jia-Yan	Electro-Thermal Analysis and Design Approach for High-Power HPC Device Interface Boards
Huang, Junlin	AI based Multi-modal Feature Clustering Technology for Wafer Root Cause Analysis
Huang, Sharon	DEFECTIVE DIE COUNT (DDC) FOR YIELD FORECASTING AND SEMICONDUCTOR FABS DEFECT DENSITY CONTROL
Huang, Shi-Yu	Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement
I
Ilgyu, Ahn	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Irkar, Pandurang	Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
Ishihara, Tohru	Effectiveness Evaluation of Bit-Width Reduction in Power-Based Integrity Verification of Gate-Level Netlists Localizing Switching Activity in ATPG for Power-Based Integrity Verification of Gate-Level Netlists
J
J N, Ravi	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Jacobs, Todd	Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
Jain, Archana	Test Program Development and Debug Methods for SSN Productization on Zero DPPM Automotive N5 SoC Enabling Full Capability of Very Low Voltage (VLV) Scan Testing in Automotive SoCs
Jansen, Ryan	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Jauch, Tobias	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Jeon, Eunsun	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Jeong, Hyuntae	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Jeong, Soonwon	Post-Fabrication Optimization for NAND Flash Memory Robust to Initial-Solution Quality
Jin, Aaron	Accelerating Bus Connectivity Verification for Packet-Based Scan Delivery Network
Jin, Robert	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
Jitlal, Colin	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Jurga, Krzysztof	A Silicon Validation of Analog Scan Testing
K
Kakani, Bhavin V	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
Kalla, Priyank	Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits
Kan, Tianze	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Kang, Minho	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Kantorovich, David	Scalable, Secure Chat-Based Analytics for Semiconductor Test
Karimi, Naghmeh	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Karuvacheryveedu, Vishnu	Bridging ATE and Bench: A Breakpoint-Driven Debug Architecture for 7GHz WLAN Firmware Integration
Kassimi, Asmaa	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
Katoh, Kentaroh	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
Kaur, Jagjot	Fast-IO DDR for High Bandwidth SSN: Enabling Scalable DFT for Large SoCs
Kaushal, Abhilash	Siemens Streaming Scan Network Comparision with Legacy Scan Routing Fabric
Ke, Hubert	Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Keane, Nate	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Keim, Martin	Joint ECC and Repair strategies for superior yield improvements
Khan, Amjad	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Kim, Bohchang	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Kim, Jihye	Industrial Experience for Achieving Advanced Test Coverage
Kim, Jiyong	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Kim, Seoyeon	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context IEA: Balancing Intelligence, Cost, and Control in Agentic Engineering Analytics
Kim, Taeok	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Kim, Yulhwa	Post-Fabrication Optimization for NAND Flash Memory Robust to Initial-Solution Quality
Km, Hyounsoon	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Kobayashi, Haruo	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
Koh, Jin Giap	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
Koike, Asuka	Effectiveness Evaluation of Bit-Width Reduction in Power-Based Integrity Verification of Gate-Level Netlists Localizing Switching Activity in ATPG for Power-Based Integrity Verification of Gate-Level Netlists
Koiner, James	Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
Korlam, Sudheer	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
Krishna Kashyap, Suhas	Fault diagnosis of analog circuits using Bayesian framework and structural BIST
Kugel, Michael	Implementation Challenges of Dual-Edge Triggered SRAMs in High-Performance Processors
Kumar, Binod	A Methodology for AI-based Defect Detection and Localization for 3D Chiplet Interconnects
Kumar, Prakash	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Kumar, Surendra	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
Kumar Tripathi, Abhesh	Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
Kumari, Manisha	A Methodology for AI-based Defect Detection and Localization for 3D Chiplet Interconnects
Kunz, Wolfgang	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Kuo, Yihsin	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Kusbit, Matthew	Poster Submission: Post-Silicon Diagnosis of SOA-Induced Threshold Voltage Drift
Kuttuva Ravikanth, Sushkrutha	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level
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L. Bushnell, Emeritus Prof. Michael	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level
Lai, Jui-Yao	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Lai, Liyang	Finding the Sweet Spot for Test Point Insertion in the Design Flow
Lakhani, Kunal	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
Larentis, Stefano	Enabling Full Capability of Very Low Voltage (VLV) Scan Testing in Automotive SoCs
Le, James	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
Lee, Frank	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
Lee, Frank	AI driven BEOL Testable Layout Pattern Enrichment Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Lee, Seongwook	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Li, Chao	IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
Li, Chao-An	From Chatting to Operating: An AI-Agent Framework for Automated Test Program Generation
Li, Chaobo	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Li, Huawei	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation Finding the Sweet Spot for Test Point Insertion in the Design Flow Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Li, James Chien-Mo	Decision Diagram-based Fault Simulator for Quantum Circuits
Li, Peng	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
Li, Wei	DEFT: Differentiable Automatic Test Pattern Generation
Li, Wenjie	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation
Li, Xiaowei	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation
Li, Zong-Han	From Chatting to Operating: An AI-Agent Framework for Automated Test Program Generation
Liang, Di	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Liang, Jingchen	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Liang, Yixin	DEFT: Differentiable Automatic Test Pattern Generation
Liao, Zhiwei	Accelerated DFT Optimization Using Compression-aware ATPG Emulation Speeding up DFT Recommendation Systems with limited-compute resources
Lim, Hyunyul	Industrial Experience for Achieving Advanced Test Coverage
Lin, Hao-Chi	Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
Lin, Lang	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Lin, Shih-Chih	Fab-Ready Zero-Shot Anomaly Detection and Segmentation for Wafer and SEM Inspection
Lin, Xiaoze	Finding the Sweet Spot for Test Point Insertion in the Design Flow
Liu, Shiyang	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Liu, Tianyi	AI based Multi-modal Feature Clustering Technology for Wafer Root Cause Analysis
Liu, Xiaoting	GTFD: A Graph-Based Sparse Attention Model for Fault Prediction in Digital Circuits
Liu, Zhenguo	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Lu, Wells	Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons
Lu, Zelin	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Lyu, Yangdi	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
M
Macieira, Thiago	Evolutionary techniques for high-level source of functional test programs
Madaan, Mohit	Novel Technique To Estimate Memory Peak Power During MBIST
Madadi, Prakyath	Speeding up DFT Recommendation Systems with limited-compute resources
Makris, Yiorgos	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
Malhotra, Rahul	Siemens Streaming Scan Network Comparision with Legacy Scan Routing Fabric
Mandal, Kaushik	A Scalable and Flexible Test Access Port (TAP) Architecture for Chiplet-Based Systems
Mani, Hari	Real-time voltage droop detection and functional monitoring telemetry for diagnosing and debugging SoCs
Margulis, Arie	Siemens Streaming Scan Network Comparision with Legacy Scan Routing Fabric
Marin Gonzalez, Josue	Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
Marmash, Mona	Accelerated DFT Optimization Using Compression-aware ATPG Emulation
Mastorakis, Nikolaos	JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
Masuda, Yutaka	Effectiveness Evaluation of Bit-Width Reduction in Power-Based Integrity Verification of Gate-Level Netlists Localizing Switching Activity in ATPG for Power-Based Integrity Verification of Gate-Level Netlists
Meehl, Dale	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Mendes, Henrique	Real-time voltage droop detection and functional monitoring telemetry for diagnosing and debugging SoCs
Meyer, Emilia	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context
Mier, Sergio	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context Adaptive Burn-In using Ensemble Learning
Misra, Supratik	Wafer Scale RAS Solution: Redundancy and System DFT in Cerebras WSE
Mitra, Subhasish	RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects
Moura, José	DEFT: Differentiable Automatic Test Pattern Generation
Muia-Tartevet, Claudia	Fast-IO DDR for High Bandwidth SSN: Enabling Scalable DFT for Large SoCs
Mukherjee, Suhrita	Transforming Failure Analysis Retrieval with Generative AI for Product Qualification
Müller, Johannes	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
N
Nagata, Makoto	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Nahar, Amit	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Nakura, Toru	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
Nanduru, Sruthi	Accelerated DFT Optimization Using Compression-aware ATPG Emulation Industrial Experience for Achieving Advanced Test Coverage
Neethirajan, Deepika	Transforming Failure Analysis Retrieval with Generative AI for Product Qualification
Nesty, Arthur	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
Ng, How Chun	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
Ni, Hsiao-Ping	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management
Niewenhuis, Benjamin	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Nigh, Matthew	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
Njinda, Charles	Accelerating Bus Connectivity Verification for Packet-Based Scan Delivery Network
Nordmann, Paul-Patrick	Joint ECC and Repair strategies for superior yield improvements
O
Oak, Chaitali S	Scan RTL DRC Fix Agent
Oh, Eunjong	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Oh, Ghil-Geun	Layout Change-Driven Failure Risk Prediction for Fast Failure Localization
Oliver, Shay	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
Olukade, Yemi	Accelerating Bus Connectivity Verification for Packet-Based Scan Delivery Network
Orailoglu, Alex	Optimization-Based Refinement of ATPG Test Patterns for Power-Based Hardware Trojan Detection
Orlando, Pete	A Flexible Multi-Die System-Level Test Architecture Leveraging In- System Test Controller (ISTC) and High-Speed IO (HSIO)
Ortega, Eduardo	THETA: Topology-Aware Secure Boot in Heterogeneous Integration for Trust and Assurance VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management
Ozev, Sule	Adaptive Burn-In using Ensemble Learning Fault diagnosis of analog circuits using Bayesian framework and structural BIST
P
Pan, Chun Chia	Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing
Pandey, Sujay	Scan RTL DRC Fix Agent
Pandya, Gunjan H	Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
Pant, Pankaj	Scan RTL DRC Fix Agent
Pantskalashvili, Lana	ATPG Coverage Debug: The Shift to Agentic AI
Park, Cheolheui	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Park, Cheolmin	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Park, Eun-woo	Next-Generation Test Strategies for Direct RF Sampling AFEs: Achieving Lab-Grade Precision in a Production ATE Environment
Park, Jaeseok	Industrial Experience for Achieving Advanced Test Coverage
Patel, Gruhesh	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Patidar, Ankita	AI driven BEOL Testable Layout Pattern Enrichment Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Payakapan, Tassanee	Siemens Streaming Scan Network Comparision with Legacy Scan Routing Fabric
Peng, Hanson H.C.	Precise Detection of FEoL Defects Using Cell-Aware Diagnosis
Peng, Huang Tang	Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing
Penmatsa, Padma	Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
Pflüger, Dirk	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Phan, Quoc	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing
Pirsiavash, Hamed	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Plusquellic, Jim	JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
Pourahmadi, Kossar	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Pourmehrani, Hossein	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Press, Ron	Theoretical Limit Calculation: Packetized Scan Delivery with On-Chip Compare (OCComp) for N Identical Cores ATPG Coverage Debug: The Shift to Agentic AI
Puligilla, Sai Varun	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing
Pun, Patty	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context
Purdy, Ruben	RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects
Purushotham, Ajay	A Scalable and Flexible Test Access Port (TAP) Architecture for Chiplet-Based Systems Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Q
Qin, Weirong	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
R
Rajski, Janusz	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Ramakrishnan, Venkat	Scan RTL DRC Fix Agent
Ramanujam, Yatiraj	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Ramesh, Saidapet	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Rao, Shreyas	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
Rathi, Vishal	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Reddy, Puli Surya Tej	AI driven BEOL Testable Layout Pattern Enrichment
Reddy, Vineel	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Ren, Chunlin	AI based Multi-modal Feature Clustering Technology for Wafer Root Cause Analysis
Richter, Scott	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Romain, Luc	Joint ECC and Repair strategies for superior yield improvements
Rottacker, Sarah	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Rousseau, Eran	Scalable, Secure Chat-Based Analytics for Semiconductor Test
Rösslhuber, Roland	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
S
Saha, Anurup	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
Salem, Rami	DEFECTIVE DIE COUNT (DDC) FOR YIELD FORECASTING AND SEMICONDUCTOR FABS DEFECT DENSITY CONTROL
Salz, Philipp	Implementation Challenges of Dual-Edge Triggered SRAMs in High-Performance Processors
Sanyal, Arindam	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
Sarker, Pantha Protim	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Schlitt, Lawrence	Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits
Schmitz, Philipp	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Schramm, Lori	Test Strategies on Intel’s Next-Generation Multi-Die Client CPU
Schuldenfrei, Michael	Scalable, Secure Chat-Based Analytics for Semiconductor Test
Seal, Mainak	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Seetharaman, Prashant	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Seo, Jihye	Layout Change-Driven Failure Risk Prediction for Fast Failure Localization
Serlis, Emmanouil Anastasios	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level
Shah, Urmil	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Shahpari, Nima	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Shaik, Junaid	Wafer Scale RAS Solution: Redundancy and System DFT in Cerebras WSE
Sharma, Shyam	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Shen, Zixin	AI based Multi-modal Feature Clustering Technology for Wafer Root Cause Analysis
Shintani, Michihiro	Optimization-Based Refinement of ATPG Test Patterns for Power-Based Hardware Trojan Detection Cryogenic Hot-Carrier Degradation in 65-nm nMOS Transistors and Its Impact on Analog Circuit Design
Sienkiewicz, Mateusz	A Scalable and Flexible Test Access Port (TAP) Architecture for Chiplet-Based Systems
Singh, Adit	Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
Singh, Ripu	Siemens Streaming Scan Network Comparision with Legacy Scan Routing Fabric
Singh, Varun	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Sinha, Arani	Evolutionary techniques for high-level source of functional test programs Scan RTL DRC Fix Agent
Sohanghpurwala, Ali Asgar	Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
Song, Dongjae	Industrial Experience for Achieving Advanced Test Coverage
Song, Jingkuan	IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
Squillero, Giovanni	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Srinivasan, Uma	Implementation Challenges of Dual-Edge Triggered SRAMs in High-Performance Processors
Stesina, Fabrizio	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Stoffel, Dominik	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Strobel, Tim	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Su, Fei	In-field Monitoring of Permanent Faults in AI Accelerators Using Spiking Neural Networks LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management
Su, Yen-Ju	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Su, Yu	Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons
Subashchandran, Dharini	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Sun, Bin	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation
Sun, Yi	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Sun, Yutao	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Sunter, Stephen	A Silicon Validation of Analog Scan Testing
Suzuki, Tatsuya	Cryogenic Hot-Carrier Degradation in 65-nm nMOS Transistors and Its Impact on Analog Circuit Design
Syed, Abdul Rahman	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Syed, Mujeeb	Fast-IO DDR for High Bandwidth SSN: Enabling Scalable DFT for Large SoCs
T
Tadesse, Mickey	Closing the Debug Loop: An LLM Agent That Root Causes Silicon Failures
Takayama, Hajime	Optimization-Based Refinement of ATPG Test Patterns for Power-Based Hardware Trojan Detection
Takayama, Hajime	Cryogenic Hot-Carrier Degradation in 65-nm nMOS Transistors and Its Impact on Analog Circuit Design
Talukdar, Jonti	VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management
Talukdar, Jonti	THETA: Topology-Aware Secure Boot in Heterogeneous Integration for Trust and Assurance
Tamakloe, Kelvin Tamakloe	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
Tan, Calvin	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
Tan, Xuanyi	DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration
Tanaka, Chika	Cryogenic Hot-Carrier Degradation in 65-nm nMOS Transistors and Its Impact on Analog Circuit Design
Tancorre, Vincenzo	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Taouil, Mottaqiallah	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level
Tehranipoor, Mark	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Teoh, Winston	Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing
Thakur, Sanket Vinod	Adaptive Burn-In using Ensemble Learning
Thapar, Dhruv	DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration
Thapar, Dhruv	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Thekke Veetil, Ratheesh	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Thota, Kiran	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Toh, Kenny Kal Vin	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
Tokunaga, Haruto	Effectiveness Evaluation of Bit-Width Reduction in Power-Based Integrity Verification of Gate-Level Netlists Localizing Switching Activity in ATPG for Power-Based Integrity Verification of Gate-Level Netlists
Toulas, Theo	Accelerated DFT Optimization Using Compression-aware ATPG Emulation Speeding up DFT Recommendation Systems with limited-compute resources
Trawka, Maciej	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Traynor, Stephen	Enabling Full Capability of Very Low Voltage (VLV) Scan Testing in Automotive SoCs
Tseng, Anti P.H.	Precise Detection of FEoL Defects Using Cell-Aware Diagnosis
Tseng, Hung-Hsi	Electro-Thermal Analysis and Design Approach for High-Power HPC Device Interface Boards
Tsiropoulou, Eirini Eleni	JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
Tuhin Ahmed, Soyed	CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification
Tyszer, Jerzy	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Tzeng, Timmy	DEFECTIVE DIE COUNT (DDC) FOR YIELD FORECASTING AND SEMICONDUCTOR FABS DEFECT DENSITY CONTROL
U
Ul Islam, Md Fahim	CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability
V
Varadarajan, Devanathan	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Vijayvergia, Arpit	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
Viola, Jack	In-Situ TDR Test Fixture for End-to-End Signal Integrity Characterization and Debug in Rack-Scale Systems
Vis, Michael	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
W
Wang, Boning	IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
Wang, Brian	A Flexible Multi-Die System-Level Test Architecture Leveraging In- System Test Controller (ISTC) and High-Speed IO (HSIO)
Wang, Bryan	A Scalable and Flexible Test Access Port (TAP) Architecture for Chiplet-Based Systems
Wang, Changhao	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Wang, Chia Wei	Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing
Wang, Hailin	Poster Submission: Post-Silicon Diagnosis of SOA-Induced Threshold Voltage Drift
Wang, Ken	Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Wang, Li-C.	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context IEA: Balancing Intelligence, Cost, and Control in Agentic Engineering Analytics Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons
Wang, Lowry P.-T.	Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
Wang, Ya	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Wang, Zhijun	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Wang, Zhiyong	GTFD: A Graph-Based Sparse Attention Model for Fault Prediction in Digital Circuits IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
Wen, Charles H.-P.	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
Wen, Tsung-Yao	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Wen, Xiaoqing	GTFD: A Graph-Based Sparse Attention Model for Fault Prediction in Digital Circuits IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
Wetter, Holger	Implementation Challenges of Dual-Edge Triggered SRAMs in High-Performance Processors
Wezel, Alex	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Wilcox, Robert	Real-time voltage droop detection and functional monitoring telemetry for diagnosing and debugging SoCs
Wisnesky, Carl	Novel Technique To Estimate Memory Peak Power During MBIST ATPG Extended Scan Power Control for Silicon Power Analysis
Wohl, Peter	Speeding up DFT Recommendation Systems with limited-compute resources
Won, Jun Yeon	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Wu, Chih-Wei	Electro-Thermal Analysis and Design Approach for High-Power HPC Device Interface Boards
Wu, Chun-Chieh	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Wu, Kai-Chiang	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Wu, Yu	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
Włodarczak, Bartosz	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
X
Xie, Biwei	Finding the Sweet Spot for Test Point Insertion in the Design Flow
Xu, Boxun	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
Xu, Hui	IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
Xu, Jiang	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Xu, Sunny	Poster Submission: Post-Silicon Diagnosis of SOA-Induced Threshold Voltage Drift
Y
Yan, Dapeng	GTFD: A Graph-Based Sparse Attention Model for Fault Prediction in Digital Circuits IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
Yang, Jeonggyu	Industrial Experience for Achieving Advanced Test Coverage
Yang, Kathy	Fast-IO DDR for High Bandwidth SSN: Enabling Scalable DFT for Large SoCs
Yang, Mandy	A Flexible Multi-Die System-Level Test Architecture Leveraging In- System Test Controller (ISTC) and High-Speed IO (HSIO)
Yang, Wu	A Flexible Multi-Die System-Level Test Architecture Leveraging In- System Test Controller (ISTC) and High-Speed IO (HSIO)
Yao, Livio	DEFECTIVE DIE COUNT (DDC) FOR YIELD FORECASTING AND SEMICONDUCTOR FABS DEFECT DENSITY CONTROL
Ye, Jing	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation
Yen, Jessica	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Yeon, Gunwoo	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Yin, Yuxuan	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
Yu, Haiming	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Yu, Liangliang	AI based Multi-modal Feature Clustering Technology for Wafer Root Cause Analysis
Yu, Yuanqi	In-field Monitoring of Permanent Faults in AI Accelerators Using Spiking Neural Networks
Yumiba, Koshiro	Cryogenic Hot-Carrier Degradation in 65-nm nMOS Transistors and Its Impact on Analog Circuit Design
Yun, Jongsin	Joint ECC and Repair strategies for superior yield improvements
Z
Zakharchuk, Mykola	From Test Floor to Thinking Floor: A Hardware-Grounded Architecture for AI Agents in Semiconductor Test
Zhang, Luping	GTFD: A Graph-Based Sparse Attention Model for Fault Prediction in Digital Circuits
Zhang, Wei	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Zhou, Xiaofeng	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Zhou, Yuanfu	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Zivkovic, Vladimir	A Silicon Validation of Analog Scan Testing
Zou, Linyu	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
Zou, Wei	Joint ECC and Repair strategies for superior yield improvements
Zou, Yang	DEFT: Differentiable Automatic Test Pattern Generation

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