ITC 2026: 2026 IEEE INTERNATIONAL TEST CONFERENCE

A
Abdel-Hafez, Khader	Accelerated DFT Optimization Using Compression-aware ATPG Emulation
Abunahla, Heba	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Acero Romero, Cesar	Toward Scalable AI-Driven SCAN Debug and Yield Learning
Adams, Klay	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Agnihotri, Pratishtha	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
Ahmad, Baleegh	Speeding up DFT Recommendation Systems with limited-compute resources
Ahuja, Meghna	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Aljuffri, Abdullah	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
Anders, Jens	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Ang, Koon Meng	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
Angione, Francesco	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Ankush, Ankush	EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits
Arapidis, Emmanouil	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level
Aziza, Hassen	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level
B
Baek, Jaehyun	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Bailey, Christopher	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Balbuena, Brandon	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
Ballentine, Jada	Transforming Failure Analysis Retrieval with Generative AI for Product Qualification
Banerjee, Sanmitra	DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration
Bantel, Linus	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Bellarmino, Nicolò	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Bernardi, Paolo	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Bertani, Claudia	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Bhanushali, Sumukh	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
Bhoumik, Partho	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Bian, Yanhao	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Bian, Zhengqi	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Billa, Arlind	A Silicon Validation of Analog Scan Testing
Bishnoi, Rajendra	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Biyani, Yashvardhan	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Blair, Steve	Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits
Blanton, Shawn	DEFT: Differentiable Automatic Test Pattern Generation RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects
Boddikurapati, Sirish	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Bonsu, Godfred	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
Bormann, Jörg	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Bruno, Sean	JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
Burton, Brandy	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
C
Campbell, Michael	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context
Cantoro, Riccardo	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Carulli, John	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
Carulli, John	ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability
Chaganti, Shravan	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
Chakrabarty, Krishnendu	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Chakrabarty, Krishnendu	THETA: Topology-Aware Secure Boot in Heterogeneous Integration for Trust and Assurance CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
Chakrabarty, Krishnendu	ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability
Chakravadhanula, Krishna	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Chakravarty, Sreejit	DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration
Chandra, Anshuman	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing
Chang, Ching-Yi	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
Chang, Norman	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Chao, Zhiteng	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Chatterjee, Dr. Abhijit	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits
Chen, Degang	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
Chen, Marvin	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Chen, Wei-Ren	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Chen, Yijing	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Cheng, Kefei	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
Chiueh, Herming	Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
Cho, Hwiyeol	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Choi, Hyojin	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Cooper, Garrett	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
Corpino, Sabrina	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Coyette, Anthony	A Silicon Validation of Analog Scan Testing
Cron, Adam	A Methodology for AI-based Defect Detection and Localization for 3D Chiplet Interconnects
Cui, Xiaotong	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
Czernitzki, Sebastian	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
D
Delgado, Francisco	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Delos Reyes, John	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
Deutschmann, Lucas	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Devarajegowda, Keerthikumara	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Dharmaraj, Gowsika	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
Dhiman, Saurabh	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
di Gruttola Giardino, Nicola	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Dima, Doina	A Silicon Validation of Analog Scan Testing
Dobbelaere, Wim	A Silicon Validation of Analog Scan Testing
Duarte, Jose Angel	Accelerated DFT Optimization Using Compression-aware ATPG Emulation
Duque Antón, Anna Lena	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
E
Esteban Rodriguez Condia, Josie	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
F
Fabregat Garcia, Francisco	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Fadiheh, Mohammad R.	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Fan, Hanwei	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Farahmandi, Farimah	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Faridi, Mukarram Ali	Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests
Fei, Siyang	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Fieback, Moritz	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level
Filipponi, Gabriele	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Firouzi, Farshad	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Fowler, Aric	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
Francis, David	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Fujita, Masahiro	A Methodology for AI-based Defect Detection and Localization for 3D Chiplet Interconnects
G
Gandhi, Rohit	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Gao, Chengcheng	LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management
Garita-Rodriguez, Esteban	Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering
Gaudet, Jonathan	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing
Gebregiorgis, Anteneh	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Geftler, Mickey	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
Geppert, Gabrielle	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
Goel, Sandeep Kumar	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators AI driven BEOL Testable Layout Pattern Enrichment Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Goraya, Jatinder	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Guin, Ujjwal	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Gupta, Sameeksha	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
H
Hamdioui, Said	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Haroon, Sohail	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
Hassan, K M Shadid	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Hati, Arjun	THETA: Topology-Aware Secure Boot in Heterogeneous Integration for Trust and Assurance VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
He, Chen	Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
He, Jialei	Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
He, Xu	RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects
Ho, Yu-Sheng	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Hroub, Ayman	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
Hsieh, Cheng-Yun	Decision Diagram-based Fault Simulator for Quantum Circuits
Hsieh, Chi-Jui	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Hsu, Chi-Hsing	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Hsu, Chih-Chia	Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement
Hua, Erbing	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Huang, Bo-Lin	Decision Diagram-based Fault Simulator for Quantum Circuits
Huang, Hsuan-Ming	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Huang, Shi-Yu	Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement
I
Ilgyu, Ahn	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
J
Jacobs, Todd	Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
Jansen, Ryan	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Jauch, Tobias	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Jeon, Eunsun	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Jeong, Hyuntae	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Jin, Robert	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
Jitlal, Colin	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Jurga, Krzysztof	A Silicon Validation of Analog Scan Testing
K
Kakani, Bhavin V	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
Kalla, Priyank	Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits
Kan, Tianze	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Kang, Minho	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Kantorovich, David	Scalable, Secure Chat-Based Analytics for Semiconductor Test
Karimi, Naghmeh	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Kassimi, Asmaa	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
Katoh, Kentaroh	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
Ke, Hubert	Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Keane, Nate	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Khan, Amjad	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Kim, Bohchang	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Kim, Jihye	Industrial Experience for Achieving Advanced Test Coverage
Kim, Jiyong	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Kim, Seoyeon	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context IEA: Balancing Intelligence, Cost, and Control in Agentic Engineering Analytics
Kim, Taeok	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Km, Hyounsoon	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Kobayashi, Haruo	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
Koh, Jin Giap	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
Korlam, Sudheer	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
Krishna Kashyap, Suhas	Fault diagnosis of analog circuits using Bayesian framework and structural BIST
Kumar, Binod	A Methodology for AI-based Defect Detection and Localization for 3D Chiplet Interconnects
Kumar, Prakash	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Kumari, Manisha	A Methodology for AI-based Defect Detection and Localization for 3D Chiplet Interconnects
Kunz, Wolfgang	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Kuo, Yihsin	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Kuttuva Ravikanth, Sushkrutha	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level
L
L. Bushnell, Emeritus Prof. Michael	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level
Lai, Jui-Yao	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Lai, Liyang	Finding the Sweet Spot for Test Point Insertion in the Design Flow
Le, James	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
Lee, Frank	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
Lee, Frank	AI driven BEOL Testable Layout Pattern Enrichment Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Lee, Seongwook	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Li, Chaobo	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Li, Huawei	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation Finding the Sweet Spot for Test Point Insertion in the Design Flow Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Li, James Chien-Mo	Decision Diagram-based Fault Simulator for Quantum Circuits
Li, Peng	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
Li, Wei	DEFT: Differentiable Automatic Test Pattern Generation
Li, Wenjie	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation
Li, Xiaowei	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation
Liang, Di	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Liang, Jingchen	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Liang, Yixin	DEFT: Differentiable Automatic Test Pattern Generation
Liao, Zhiwei	Accelerated DFT Optimization Using Compression-aware ATPG Emulation Speeding up DFT Recommendation Systems with limited-compute resources
Lim, Hyunyul	Industrial Experience for Achieving Advanced Test Coverage
Lin, Hao-Chi	Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
Lin, Lang	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Lin, Xiaoze	Finding the Sweet Spot for Test Point Insertion in the Design Flow
Liu, Shiyang	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Liu, Zhenguo	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Lu, Wells	Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons
Lu, Zelin	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Lyu, Yangdi	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
M
Madadi, Prakyath	Speeding up DFT Recommendation Systems with limited-compute resources
Makris, Yiorgos	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
Marmash, Mona	Accelerated DFT Optimization Using Compression-aware ATPG Emulation
Mastorakis, Nikolaos	JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
Meehl, Dale	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Meyer, Emilia	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context
Mier, Sergio	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context Adaptive Burn-In using Ensemble Learning
Mitra, Subhasish	RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects
Moura, José	DEFT: Differentiable Automatic Test Pattern Generation
Mukherjee, Suhrita	Transforming Failure Analysis Retrieval with Generative AI for Product Qualification
Müller, Johannes	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
N
Nagata, Makoto	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Nahar, Amit	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Nakura, Toru	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
Nanduru, Sruthi	Accelerated DFT Optimization Using Compression-aware ATPG Emulation Industrial Experience for Achieving Advanced Test Coverage
Neethirajan, Deepika	Transforming Failure Analysis Retrieval with Generative AI for Product Qualification
Nesty, Arthur	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
Ng, How Chun	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
Ni, Hsiao-Ping	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management
Niewenhuis, Benjamin	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Nigh, Matthew	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
O
Oak, Chaitali S	Scan RTL DRC Fix Agent
Oh, Eunjong	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Oh, Ghil-Geun	Layout Change-Driven Failure Risk Prediction for Fast Failure Localization
Oliver, Shay	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
Ortega, Eduardo	THETA: Topology-Aware Secure Boot in Heterogeneous Integration for Trust and Assurance VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management
Ozev, Sule	Adaptive Burn-In using Ensemble Learning Fault diagnosis of analog circuits using Bayesian framework and structural BIST
P
Pandey, Sujay	Scan RTL DRC Fix Agent
Pant, Pankaj	Scan RTL DRC Fix Agent
Park, Cheolheui	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Park, Cheolmin	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Park, Jaeseok	Industrial Experience for Achieving Advanced Test Coverage
Patel, Gruhesh	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Patidar, Ankita	AI driven BEOL Testable Layout Pattern Enrichment Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Pflüger, Dirk	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Phan, Quoc	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing
Pirsiavash, Hamed	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Plusquellic, Jim	JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
Pourahmadi, Kossar	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Pourmehrani, Hossein	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Puligilla, Sai Varun	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing
Pun, Patty	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context
Purdy, Ruben	RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects
Purushotham, Ajay	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Q
Qin, Weirong	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
R
Rajski, Janusz	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Ramakrishnan, Venkat	Scan RTL DRC Fix Agent
Ramanujam, Yatiraj	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Rao, Shreyas	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
Rathi, Vishal	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Reddy, Puli Surya Tej	AI driven BEOL Testable Layout Pattern Enrichment
Reddy, Vineel	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Richter, Scott	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Rottacker, Sarah	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Rousseau, Eran	Scalable, Secure Chat-Based Analytics for Semiconductor Test
Rösslhuber, Roland	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
S
Saha, Anurup	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
Sanyal, Arindam	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
Sarker, Pantha Protim	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Schlitt, Lawrence	Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits
Schmitz, Philipp	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Schuldenfrei, Michael	Scalable, Secure Chat-Based Analytics for Semiconductor Test
Seal, Mainak	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Seetharaman, Prashant	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Seo, Jihye	Layout Change-Driven Failure Risk Prediction for Fast Failure Localization
Serlis, Emmanouil Anastasios	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level
Shah, Urmil	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Shahpari, Nima	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Sharma, Shyam	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Singh, Adit	Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
Singh, Varun	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Sinha, Arani	Scan RTL DRC Fix Agent
Song, Dongjae	Industrial Experience for Achieving Advanced Test Coverage
Squillero, Giovanni	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Stesina, Fabrizio	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Stoffel, Dominik	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Strobel, Tim	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Su, Fei	LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management
Su, Yen-Ju	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Su, Yu	Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons
Subashchandran, Dharini	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Sun, Bin	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation
Sun, Yutao	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Sunter, Stephen	A Silicon Validation of Analog Scan Testing
Syed, Abdul Rahman	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
T
Tadesse, Mickey	Closing the Debug Loop: An LLM Agent That Root Causes Silicon Failures
Talukdar, Jonti	VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management
Talukdar, Jonti	THETA: Topology-Aware Secure Boot in Heterogeneous Integration for Trust and Assurance
Tamakloe, Kelvin Tamakloe	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
Tan, Calvin	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
Tan, Xuanyi	DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration
Tancorre, Vincenzo	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Taouil, Mottaqiallah	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level
Tehranipoor, Mark	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Thakur, Sanket Vinod	Adaptive Burn-In using Ensemble Learning
Thapar, Dhruv	DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration
Thapar, Dhruv	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Thekke Veetil, Ratheesh	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Toh, Kenny Kal Vin	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
Toulas, Theo	Accelerated DFT Optimization Using Compression-aware ATPG Emulation Speeding up DFT Recommendation Systems with limited-compute resources
Trawka, Maciej	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Tsiropoulou, Eirini Eleni	JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
Tuhin Ahmed, Soyed	CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification
Tyszer, Jerzy	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
U
Ul Islam, Md Fahim	CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability
V
Varadarajan, Devanathan	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Vis, Michael	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
W
Wang, Changhao	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Wang, Ken	Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Wang, Li-C.	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context IEA: Balancing Intelligence, Cost, and Control in Agentic Engineering Analytics Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons
Wang, Lowry P.-T.	Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
Wang, Ya	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Wang, Zhijun	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Wen, Charles H.-P.	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
Wen, Tsung-Yao	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Wezel, Alex	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Wohl, Peter	Speeding up DFT Recommendation Systems with limited-compute resources
Won, Jun Yeon	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Wu, Chun-Chieh	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Wu, Kai-Chiang	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Wu, Yu	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
Włodarczak, Bartosz	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
X
Xie, Biwei	Finding the Sweet Spot for Test Point Insertion in the Design Flow
Xu, Boxun	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
Xu, Jiang	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Y
Yang, Jeonggyu	Industrial Experience for Achieving Advanced Test Coverage
Ye, Jing	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation
Yen, Jessica	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Yeon, Gunwoo	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Yin, Yuxuan	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
Yu, Haiming	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Z
Zhang, Wei	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Zhou, Xiaofeng	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Zhou, Yuanfu	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Zivkovic, Vladimir	A Silicon Validation of Analog Scan Testing
Zou, Linyu	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
Zou, Yang	DEFT: Differentiable Automatic Test Pattern Generation

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