ITC 2026: 2026 IEEE INTERNATIONAL TEST CONFERENCE

This page contains an index consisting of author-provided keywords.

2
2.5D	A Scalable and Flexible Test Access Port (TAP) Architecture for Chiplet-Based Systems
3
3nm Technology	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
A
Access Test Time Reduction	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
Adaptive Test	Adaptive Burn-In using Ensemble Learning
ADC	Next-Generation Test Strategies for Direct RF Sampling AFEs: Achieving Lab-Grade Precision in a Production ATE Environment
Advanced Process	Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Advanced technology nodes	Implementation Challenges of Dual-Edge Triggered SRAMs in High-Performance Processors
Advantest SmarTest 8	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
AES	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
AFE	Next-Generation Test Strategies for Direct RF Sampling AFEs: Achieving Lab-Grade Precision in a Production ATE Environment
Agent for Testing	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
agent-to-tool protocol	From Test Floor to Thinking Floor: A Hardware-Grounded Architecture for AI Agents in Semiconductor Test
agentic	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
Agentic AI	Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development Toward Scalable AI-Driven SCAN Debug and Yield Learning Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons Scan RTL DRC Fix Agent ATPG Coverage Debug: The Shift to Agentic AI
agentic workflow	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
AI	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation Scalable, Secure Chat-Based Analytics for Semiconductor Test Closing the Debug Loop: An LLM Agent That Root Causes Silicon Failures ATPG Coverage Debug: The Shift to Agentic AI
AI Agents	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context IEA: Balancing Intelligence, Cost, and Control in Agentic Engineering Analytics From Test Floor to Thinking Floor: A Hardware-Grounded Architecture for AI Agents in Semiconductor Test
AI assisted coverage	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
AI chip	Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing
AI in EDA	AI driven BEOL Testable Layout Pattern Enrichment
AI/Machine Learning	Industrial Experience for Achieving Advanced Test Coverage
all-digital	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
All-Digital Phase-Locked Loop (ADPLL)	Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement
Alternate Test	EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits
Analog ASIC Reliability	Poster Submission: Post-Silicon Diagnosis of SOA-Induced Threshold Voltage Drift
analog ATPG	A Silicon Validation of Analog Scan Testing
analog DfT	A Silicon Validation of Analog Scan Testing
Analog Test	Fault diagnosis of analog circuits using Bayesian framework and structural BIST
Analog/Mixed-Signal Circuits (AMS)	EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits
Analytics	Scalable, Secure Chat-Based Analytics for Semiconductor Test AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis IEA: Balancing Intelligence, Cost, and Control in Agentic Engineering Analytics
And-Inverter Graph (AIG)	Finding the Sweet Spot for Test Point Insertion in the Design Flow
Anomaly detection	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management Automated Issue Site Detection in Multi-Site Testing via Isolation forest
anomaly diagnosis	LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management
Approximation	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Area Optimization	Finding the Sweet Spot for Test Point Insertion in the Design Flow
array	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
Artificial Intelligence	Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
Artificial Intelligence (AI)	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
ASIC	Precise Detection of FEoL Defects Using Cell-Aware Diagnosis
ASIC Cascade Failure	FORENSIC ANALYSIS OF I2C BUS INSTABILITY LEADING TO FAILURES IN MULTI-ASIC INFINIBAND SWITCH ARCHITECTURES
Assurance	Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
ATE	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development Test Program Development and Debug Methods for SSN Productization on Zero DPPM Automotive N5 SoC From Chatting to Operating: An AI-Agent Framework for Automated Test Program Generation Bridging ATE and Bench: A Breakpoint-Driven Debug Architecture for 7GHz WLAN Firmware Integration Next-Generation Test Strategies for Direct RF Sampling AFEs: Achieving Lab-Grade Precision in a Production ATE Environment
ATE Test Pattern Generation	AI driven BEOL Testable Layout Pattern Enrichment
ATPG	DEFT: Differentiable Automatic Test Pattern Generation Industrial Experience for Achieving Advanced Test Coverage RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits Toward Scalable AI-Driven SCAN Debug and Yield Learning ATPG Extended Scan Power Control for Silicon Power Analysis ATPG Coverage Debug: The Shift to Agentic AI IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
automated test equipment	From Test Floor to Thinking Floor: A Hardware-Grounded Architecture for AI Agents in Semiconductor Test
automated test equipment (ATE)	Electro-Thermal Analysis and Design Approach for High-Power HPC Device Interface Boards
Automated Test Pattern Generation	Speeding up DFT Recommendation Systems with limited-compute resources
Automatic Test Equipment (ATE)	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8 Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing
Automatic Test Pattern Generation	Accelerated DFT Optimization Using Compression-aware ATPG Emulation Localizing Switching Activity in ATPG for Power-Based Integrity Verification of Gate-Level Netlists ATPG Coverage Debug: The Shift to Agentic AI
Automatic Test Pattern Generation (ATPG)	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation AI driven BEOL Testable Layout Pattern Enrichment
Automotive	Enabling Full Capability of Very Low Voltage (VLV) Scan Testing in Automotive SoCs
Automotive ASIL-D	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Automotive DPPM	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
B
Back-End-of-Line (BEOL)	AI driven BEOL Testable Layout Pattern Enrichment
Backend Routing	AI driven BEOL Testable Layout Pattern Enrichment
beam search	Optimization-Based Refinement of ATPG Test Patterns for Power-Based Hardware Trojan Detection
Benchmark	Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
Bias Temperature Instability (BTI)	Poster Submission: Post-Silicon Diagnosis of SOA-Induced Threshold Voltage Drift
BIST	Fault diagnosis of analog circuits using Bayesian framework and structural BIST Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
Bit-flip Fault	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
bit-width reduction	Effectiveness Evaluation of Bit-Width Reduction in Power-Based Integrity Verification of Gate-Level Netlists
Bitstream Equivalence Checking	Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
boundary scan	A Scalable and Flexible Test Access Port (TAP) Architecture for Chiplet-Based Systems
Bridge Defects	AI driven BEOL Testable Layout Pattern Enrichment
Built In Self Test	Fault diagnosis of analog circuits using Bayesian framework and structural BIST
Burn-In	Adaptive Burn-In using Ensemble Learning
C
Cable Backplane	In-Situ TDR Test Fixture for End-to-End Signal Integrity Characterization and Debug in Rack-Scale Systems
Cable Cartridge	In-Situ TDR Test Fixture for End-to-End Signal Integrity Characterization and Debug in Rack-Scale Systems
Capture	ATPG Extended Scan Power Control for Silicon Power Analysis
Capture Power	ATPG Extended Scan Power Control for Silicon Power Analysis
Capture Switching	ATPG Extended Scan Power Control for Silicon Power Analysis
Cell-Aware	Precise Detection of FEoL Defects Using Cell-Aware Diagnosis ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
cell-aware test	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Characterization	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles Next-Generation Test Strategies for Direct RF Sampling AFEs: Achieving Lab-Grade Precision in a Production ATE Environment
Chatting AI	From Chatting to Operating: An AI-Agent Framework for Automated Test Program Generation
chip probe	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Chiplet	A Methodology for AI-based Defect Detection and Localization for 3D Chiplet Interconnects DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration
CI/CD	Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering
Circuit Optimization	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation
circuit simulation	Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests
class imbalance	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Claude Code	From Chatting to Operating: An AI-Agent Framework for Automated Test Program Generation
CLI	From Chatting to Operating: An AI-Agent Framework for Automated Test Program Generation
clock gating	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
Clock violations	Scan RTL DRC Fix Agent
Cluster-Based Diagnosis	EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits
CMD-CMD spacing	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
CMOS image sensor (CIS)	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
CNOD	Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Codex	From Chatting to Operating: An AI-Agent Framework for Automated Test Program Generation
Columnar query engine	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
combinatorial optimization	Optimization-Based Refinement of ATPG Test Patterns for Power-Based Hardware Trojan Detection
Compression	ATPG Extended Scan Power Control for Silicon Power Analysis
Computation-in-memory	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level
Compute Tray	In-Situ TDR Test Fixture for End-to-End Signal Integrity Characterization and Debug in Rack-Scale Systems
Compute-in-memory	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
Computing-in-Memory (CIM)	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
concurrent fault simulation	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Conformal calibration	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management
constrained randomization	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Countermeasure	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
coverage driven verification	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
CP testing	Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing
CPA	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
CPO Circuit	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
cr_space Analysis	FORENSIC ANALYSIS OF I2C BUS INSTABILITY LEADING TO FAILURES IN MULTI-ASIC INFINIBAND SWITCH ARCHITECTURES
cross-domain robustness	Fab-Ready Zero-Shot Anomaly Detection and Segmentation for Wafer and SEM Inspection
Cross-triggering	Real-time voltage droop detection and functional monitoring telemetry for diagnosing and debugging SoCs
Cryogenic	Cryogenic Hot-Carrier Degradation in 65-nm nMOS Transistors and Its Impact on Analog Circuit Design
Custom AI Accelerator	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
customization	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
D
DAC	Next-Generation Test Strategies for Direct RF Sampling AFEs: Achieving Lab-Grade Precision in a Production ATE Environment
dashboard generation	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
Data Analysis	Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
Data Analytics	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context
Data Center Reliability	FORENSIC ANALYSIS OF I2C BUS INSTABILITY LEADING TO FAILURES IN MULTI-ASIC INFINIBAND SWITCH ARCHITECTURES
Data Insights	Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
Data Visualization	Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
Data-driven diagnosis	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management
DDR	Fast-IO DDR for High Bandwidth SSN: Enabling Scalable DFT for Large SoCs
Debug	ATPG Extended Scan Power Control for Silicon Power Analysis
Decision Diagrams	Decision Diagram-based Fault Simulator for Quantum Circuits
Deep Neural Network	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
Deep Neural Networks	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
defect	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
defect analysis	ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability
defect clustering	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Defect Density Management	DEFECTIVE DIE COUNT (DDC) FOR YIELD FORECASTING AND SEMICONDUCTOR FABS DEFECT DENSITY CONTROL
Defect detection	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Defect Diagnosis	AI driven BEOL Testable Layout Pattern Enrichment
Defect learning	Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Defect Monitoring	DEFECTIVE DIE COUNT (DDC) FOR YIELD FORECASTING AND SEMICONDUCTOR FABS DEFECT DENSITY CONTROL
Defect-based test	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
Defect-Oriented Stress	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Deploying	Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons
Design for security	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Design for Test	Accelerated DFT Optimization Using Compression-aware ATPG Emulation Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG Speeding up DFT Recommendation Systems with limited-compute resources ATPG Coverage Debug: The Shift to Agentic AI
Design for Test (DFT)	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
Design for testability	IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
Design for Testability (DFT)	AI driven BEOL Testable Layout Pattern Enrichment
design validation	Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering
Design-for-Manufacturing (DFM)	AI driven BEOL Testable Layout Pattern Enrichment
Design-for-Test	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators Accelerating Bus Connectivity Verification for Packet-Based Scan Delivery Network Test Strategies on Intel’s Next-Generation Multi-Die Client CPU
Design-for-Test (DFT)	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
Design-for-Testability	Scan RTL DRC Fix Agent
Design-for-Testability (DfT)	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
device interface board (DIB)	Electro-Thermal Analysis and Design Approach for High-Power HPC Device Interface Boards
Device Variability	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
DFT	Industrial Experience for Achieving Advanced Test Coverage Toward Scalable AI-Driven SCAN Debug and Yield Learning Test Program Development and Debug Methods for SSN Productization on Zero DPPM Automotive N5 SoC Wafer Scale RAS Solution: Redundancy and System DFT in Cerebras WSE Test Strategies on Intel’s Next-Generation Multi-Die Client CPU Siemens Streaming Scan Network Comparision with Legacy Scan Routing Fabric
diagnosis	Precise Detection of FEoL Defects Using Cell-Aware Diagnosis
Diagnostic feedback	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Die-Level Test	AI driven BEOL Testable Layout Pattern Enrichment
Differentiable Programming	DEFT: Differentiable Automatic Test Pattern Generation
diffusion models	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
diffusion transformer	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
Digital Capture Debug	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
Digital twin	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management
Direct Memory Access	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
direct RF sampling	Next-Generation Test Strategies for Direct RF Sampling AFEs: Achieving Lab-Grade Precision in a Production ATE Environment
divergence tracking	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
DMAIC	Toward Scalable AI-Driven SCAN Debug and Yield Learning
DPPM	Test Program Development and Debug Methods for SSN Productization on Zero DPPM Automotive N5 SoC Precise Detection of FEoL Defects Using Cell-Aware Diagnosis
DRAM	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Dual‑edge clocking	Implementation Challenges of Dual-Edge Triggered SRAMs in High-Performance Processors
Duty‑cycle tuning	Implementation Challenges of Dual-Edge Triggered SRAMs in High-Performance Processors
DV analysis	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
DWR	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
dynamic programming	Accelerating Bus Connectivity Verification for Packet-Based Scan Delivery Network
Dynamic scan control	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
E
E-graph	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation
early performance binning	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
ECC	Joint ECC and Repair strategies for superior yield improvements
EDA Tools	AI driven BEOL Testable Layout Pattern Enrichment
EDS Test Simulation	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
EFA	Precise Detection of FEoL Defects Using Cell-Aware Diagnosis
Elastic	ATPG Extended Scan Power Control for Silicon Power Analysis
Electrical Die Sorting (EDS)	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Electrical Test	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
electro-thermal co-simulation	Electro-Thermal Analysis and Design Approach for High-Power HPC Device Interface Boards
Electromagnetic fault injection (EMFI)	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Electromigration-induced aging	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
embedded systems	Real-time voltage droop detection and functional monitoring telemetry for diagnosing and debugging SoCs
Emerging Technology	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
Engineering Productivity	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
erratic bit detection	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
Error Correction Code	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Error Correction Code (ECC)	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
EUV-based Process	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
evolutionary techniques	Evolutionary techniques for high-level source of functional test programs
F
fabrication process variation	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
fail bit count	Joint ECC and Repair strategies for superior yield improvements
Failure Analysis	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs Layout Change-Driven Failure Risk Prediction for Fast Failure Localization Transforming Failure Analysis Retrieval with Generative AI for Product Qualification
Fan-out Wafer-Level Packaging	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Fast IO	Fast-IO DDR for High Bandwidth SSN: Enabling Scalable DFT for Large SoCs
Fault Analysis	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Fault Coverage	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures AI driven BEOL Testable Layout Pattern Enrichment
Fault diagnosis	Fault diagnosis of analog circuits using Bayesian framework and structural BIST GTFD: A Graph-Based Sparse Attention Model for Fault Prediction in Digital Circuits
fault grading	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Fault modeling	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Fault Modelling	AI driven BEOL Testable Layout Pattern Enrichment
Fault Simulation	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells Decision Diagram-based Fault Simulator for Quantum Circuits
Fault-aware Training	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Fault-Tolerant Quantum Computing	Decision Diagram-based Fault Simulator for Quantum Circuits
feature specific coverage	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Field monitoring	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management
Fine-Grain Fault Modeling	RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects
FinFET	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Firmware	Bridging ATE and Bench: A Breakpoint-Driven Debug Architecture for 7GHz WLAN Firmware Integration
Forensic Log Analysis	FORENSIC ANALYSIS OF I2C BUS INSTABILITY LEADING TO FAILURES IN MULTI-ASIC INFINIBAND SWITCH ARCHITECTURES
Formal Verification	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
FPGA	Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
FPGA oversampling-based soft logic	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Full Scan	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level
Functional monitoring	Real-time voltage droop detection and functional monitoring telemetry for diagnosing and debugging SoCs
Functional Safety Analysis	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Functional Test	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
functional testing	Evolutionary techniques for high-level source of functional test programs
G
Gaussian Mixture Models	EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits
Generative AI	Scalable, Secure Chat-Based Analytics for Semiconductor Test
generative data augmentation	CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification
Generic Data Streaming (GDS)	Test Strategies on Intel’s Next-Generation Multi-Die Client CPU
GitHub Copilot	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
GPIO	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
gradient boosting	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
graph computing	Accelerating Bus Connectivity Verification for Packet-Based Scan Delivery Network
Graph Convolutional Networks	GTFD: A Graph-Based Sparse Attention Model for Fault Prediction in Digital Circuits
Graph Neural Network	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
graph theory	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
H
Hardware coprocessor	JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
Hardware Fuzzing	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
hardware grounding	From Test Floor to Thinking Floor: A Hardware-Grounded Architecture for AI Agents in Semiconductor Test
hardware root of trust	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Hardware Security	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Hardware Telemetry	VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management
hardware Trojan detection	Optimization-Based Refinement of ATPG Test Patterns for Power-Based Hardware Trojan Detection
Hardware Trojan Horse	Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
Hardware-Software Co-Debugging	Bridging ATE and Bench: A Breakpoint-Driven Debug Architecture for 7GHz WLAN Firmware Integration
hash functions	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
HB-IJTAG	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing
HBM test	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing
Heterogeneous integration	THETA: Topology-Aware Secure Boot in Heterogeneous Integration for Trust and Assurance
Hierarchical Test	Test Strategies on Intel’s Next-Generation Multi-Die Client CPU
Hierarchical Test Strategy	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
High Bandwidth Memory (HBM)	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
High Performance Computing	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
high power	Electro-Thermal Analysis and Design Approach for High-Power HPC Device Interface Boards
high-end processors testing	Evolutionary techniques for high-level source of functional test programs
high-level source code	Evolutionary techniques for high-level source of functional test programs
High-Performance Computing (HPC)	Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing Electro-Thermal Analysis and Design Approach for High-Power HPC Device Interface Boards
High-Speed Interconnect	In-Situ TDR Test Fixture for End-to-End Signal Integrity Characterization and Debug in Rack-Scale Systems
high-speed IO	A Flexible Multi-Die System-Level Test Architecture Leveraging In- System Test Controller (ISTC) and High-Speed IO (HSIO)
High-Speed Test I/O (HSTIO)	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
High-Speed Test Interface	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
High-volume manufacturing	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Hot carrier degradation	Cryogenic Hot-Carrier Degradation in 65-nm nMOS Transistors and Its Impact on Analog Circuit Design
Hot Carrier Injection (HCI)	Poster Submission: Post-Silicon Diagnosis of SOA-Induced Threshold Voltage Drift
HPC	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
HPC Networks	FORENSIC ANALYSIS OF I2C BUS INSTABILITY LEADING TO FAILURES IN MULTI-ASIC INFINIBAND SWITCH ARCHITECTURES
HVM	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
hybrid trust model	Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering
hyperdimensional computing	LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management
I
I2C Bus Failure	FORENSIC ANALYSIS OF I2C BUS INSTABILITY LEADING TO FAILURES IN MULTI-ASIC INFINIBAND SWITCH ARCHITECTURES
IC security and reliability	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
IC testing	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
ICL	A Scalable and Flexible Test Access Port (TAP) Architecture for Chiplet-Based Systems
Identical-core testing	Theoretical Limit Calculation: Packetized Scan Delivery with On-Chip Compare (OCComp) for N Identical Cores
IEEE 1687	A Scalable and Flexible Test Access Port (TAP) Architecture for Chiplet-Based Systems
IEEE 1687 (IJTAG)	Test Strategies on Intel’s Next-Generation Multi-Die Client CPU
IEEE 1838	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
IEEE-1149.1	A Scalable and Flexible Test Access Port (TAP) Architecture for Chiplet-Based Systems
IEEE-1838	A Scalable and Flexible Test Access Port (TAP) Architecture for Chiplet-Based Systems
IJTAG	A Silicon Validation of Analog Scan Testing
Improved Newton-Rapshon-based Optimizer	Post-Fabrication Optimization for NAND Flash Memory Robust to Initial-Solution Quality
In Field Test	Wafer Scale RAS Solution: Redundancy and System DFT in Cerebras WSE
in-field debug and monitoring	Real-time voltage droop detection and functional monitoring telemetry for diagnosing and debugging SoCs
In-field test	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management
In-System Test	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs A Flexible Multi-Die System-Level Test Architecture Leveraging In- System Test Controller (ISTC) and High-Speed IO (HSIO)
InfiniBand	FORENSIC ANALYSIS OF I2C BUS INSTABILITY LEADING TO FAILURES IN MULTI-ASIC INFINIBAND SWITCH ARCHITECTURES
Infiniband Switch	FORENSIC ANALYSIS OF I2C BUS INSTABILITY LEADING TO FAILURES IN MULTI-ASIC INFINIBAND SWITCH ARCHITECTURES
Information Flow Tracking	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Inpact on analog circuit design	Cryogenic Hot-Carrier Degradation in 65-nm nMOS Transistors and Its Impact on Analog Circuit Design
integrity verification	Effectiveness Evaluation of Bit-Width Reduction in Power-Based Integrity Verification of Gate-Level Netlists Localizing Switching Activity in ATPG for Power-Based Integrity Verification of Gate-Level Netlists
Inter-cell defects	Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Inter-Metal Layer Bridges	AI driven BEOL Testable Layout Pattern Enrichment
Interconnect	A Methodology for AI-based Defect Detection and Localization for 3D Chiplet Interconnects
Interconnect test	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing
intra-cell defect	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
IP Piracy	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
Isolation Forest	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
J
jitter	Next-Generation Test Strategies for Direct RF Sampling AFEs: Achieving Lab-Grade Precision in a Production ATE Environment
L
LA-DOS	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
lab automation	Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering
Large Language Model	ATPG Coverage Debug: The Shift to Agentic AI
large language models	ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability
Large Language Models (LLMs)	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
Latent Defects	Enabling Full Capability of Very Low Voltage (VLV) Scan Testing in Automotive SoCs
Layout Similarity	Layout Change-Driven Failure Risk Prediction for Fast Failure Localization
layout-aware	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Lean Six Sigma	Toward Scalable AI-Driven SCAN Debug and Yield Learning
Linear Programming	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
LLM	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation Scalable, Secure Chat-Based Analytics for Semiconductor Test Transforming Failure Analysis Retrieval with Generative AI for Product Qualification Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering Closing the Debug Loop: An LLM Agent That Root Causes Silicon Failures ATPG Coverage Debug: The Shift to Agentic AI
LLM automation	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
LLMs	IEA: Balancing Intelligence, Cost, and Control in Agentic Engineering Analytics
Logic BIST	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Logic Locking	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
lot-level diagnostics	ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability
Low compute	Speeding up DFT Recommendation Systems with limited-compute resources
Low Pin Count Test	Test Strategies on Intel’s Next-Generation Multi-Die Client CPU
Low‑power test	Implementation Challenges of Dual-Edge Triggered SRAMs in High-Performance Processors
lpddr6	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
lumped delay	Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests
M
Machine Learning	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage Adaptive Burn-In using Ensemble Learning AI driven BEOL Testable Layout Pattern Enrichment Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
Malware Detection	JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
manufacturing test	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation Accelerating Bus Connectivity Verification for Packet-Based Scan Delivery Network
Manufacturing Test Setup	Test Strategies on Intel’s Next-Generation Multi-Die Client CPU
manufacturing testing	Evolutionary techniques for high-level source of functional test programs
Matching	DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration
Maximin Optimization	Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits
MBIST	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing Improving Yield Through Advanced Detection of High-Speed Memory Access Failures AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis Novel Technique To Estimate Memory Peak Power During MBIST
MCP	Scalable, Secure Chat-Based Analytics for Semiconductor Test Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering
Memory	Novel Technique To Estimate Memory Peak Power During MBIST Joint ECC and Repair strategies for superior yield improvements
Memory BIST	Joint ECC and Repair strategies for superior yield improvements
Memory Built-In Self-Test (MBIST)	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
Memory Power	Novel Technique To Estimate Memory Peak Power During MBIST
Memory repair	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Memory test algorithms	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Memory Testing	Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
Micro-bump	A Methodology for AI-based Defect Detection and Localization for 3D Chiplet Interconnects
Minimum operating voltage	Implementation Challenges of Dual-Edge Triggered SRAMs in High-Performance Processors
MIPI C-PHY	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
MIPI Camera Serial Interface (CSI-2)	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
MIPI D-PHY	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Mirroring modulators	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
mission-mode testing	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
ML	Scalable, Secure Chat-Based Analytics for Semiconductor Test
ML attacks	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
ML in EDA	AI driven BEOL Testable Layout Pattern Enrichment
model collapse	CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification
Model Context Protocol	From Test Floor to Thinking Floor: A Hardware-Grounded Architecture for AI Agents in Semiconductor Test
Monte Carlo Simulation	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
MOS transister	Cryogenic Hot-Carrier Degradation in 65-nm nMOS Transistors and Its Impact on Analog Circuit Design
MOSFET Degradation	Poster Submission: Post-Silicon Diagnosis of SOA-Induced Threshold Voltage Drift
MRAM	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
multi-agent reasoning	ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability
Multi-Chiplet Integration	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
Multi-Die	A Scalable and Flexible Test Access Port (TAP) Architecture for Chiplet-Based Systems A Flexible Multi-Die System-Level Test Architecture Leveraging In- System Test Controller (ISTC) and High-Speed IO (HSIO)
Multi-Lane SDR/DDR	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
multi-layer memory	From Test Floor to Thinking Floor: A Hardware-Grounded Architecture for AI Agents in Semiconductor Test
multi-modal	AI based Multi-modal Feature Clustering Technology for Wafer Root Cause Analysis
multi-mode SoC testing	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
multi-site testing	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
multi-stage test data integration	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
multi-view clustering	AI based Multi-modal Feature Clustering Technology for Wafer Root Cause Analysis
Multimodal Retrieval	Transforming Failure Analysis Retrieval with Generative AI for Product Qualification
Multivariate Outlier Detection	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
N
NAND Flash Memory	Post-Fabrication Optimization for NAND Flash Memory Robust to Initial-Solution Quality
Neural Network	DEFT: Differentiable Automatic Test Pattern Generation
Noisy Intermediate-Scale Quantum	Decision Diagram-based Fault Simulator for Quantum Circuits
nonlinear ciphers	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
NVRAM	Bridging ATE and Bench: A Breakpoint-Driven Debug Architecture for 7GHz WLAN Firmware Integration
O
Obfuscation	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
on-chip calibration	Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement
On-Chip Compare (OCComp)	Theoretical Limit Calculation: Packetized Scan Delivery with On-Chip Compare (OCComp) for N Identical Cores
on-chip diagnosis	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
On-die voltage telemetry	Real-time voltage droop detection and functional monitoring telemetry for diagnosing and debugging SoCs
on-premises deployment	From Test Floor to Thinking Floor: A Hardware-Grounded Architecture for AI Agents in Semiconductor Test
One-Way Varactor Cell (OWVC)	Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement
Operating AI	From Chatting to Operating: An AI-Agent Framework for Automated Test Program Generation
Optimization	Accelerated DFT Optimization Using Compression-aware ATPG Emulation
OTPL	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
Otsu thresholding	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
Output Obfuscation	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
P
Package-Level Test	AI driven BEOL Testable Layout Pattern Enrichment
Packet-based scan delivery	Accelerating Bus Connectivity Verification for Packet-Based Scan Delivery Network
Packetized scan data delivery	Fast-IO DDR for High Bandwidth SSN: Enabling Scalable DFT for Large SoCs
Packetized scan delivery	Theoretical Limit Calculation: Packetized Scan Delivery with On-Chip Compare (OCComp) for N Identical Cores
path delay testing	Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests
Pattern Recognition	Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
Pattern-aware difference	Layout Change-Driven Failure Risk Prediction for Fast Failure Localization
PCB Backplane	In-Situ TDR Test Fixture for End-to-End Signal Integrity Characterization and Debug in Rack-Scale Systems
Peak Power	Novel Technique To Estimate Memory Peak Power During MBIST
Peak Power Estimation	Novel Technique To Estimate Memory Peak Power During MBIST
PEPR	RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects
Per Core Analysis	Test Program Development and Debug Methods for SSN Productization on Zero DPPM Automotive N5 SoC
performance binning prediction	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Performance Optimization	Finding the Sweet Spot for Test Point Insertion in the Design Flow
PFA	Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study Precise Detection of FEoL Defects Using Cell-Aware Diagnosis
photonics	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
Physical tampering	THETA: Topology-Aware Secure Boot in Heterogeneous Integration for Trust and Assurance
Physical Test Coverage	AI driven BEOL Testable Layout Pattern Enrichment
PLL	Next-Generation Test Strategies for Direct RF Sampling AFEs: Achieving Lab-Grade Precision in a Production ATE Environment
PNM	From Chatting to Operating: An AI-Agent Framework for Automated Test Program Generation
Post Silicon Validation	Adaptive Burn-In using Ensemble Learning
Post-Fabrication Optimization	Post-Fabrication Optimization for NAND Flash Memory Robust to Initial-Solution Quality
Post-Si Debug	Closing the Debug Loop: An LLM Agent That Root Causes Silicon Failures
Post-Silicon Diagnosis	Poster Submission: Post-Silicon Diagnosis of SOA-Induced Threshold Voltage Drift
Post-Silicon Testing	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
Post-Silicon Tuning	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Power	Novel Technique To Estimate Memory Peak Power During MBIST ATPG Extended Scan Power Control for Silicon Power Analysis
Power Delivery Network	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
power delivery network (PDN)	Electro-Thermal Analysis and Design Approach for High-Power HPC Device Interface Boards
Power Estimation	Novel Technique To Estimate Memory Peak Power During MBIST
power side-channel analysis	Optimization-Based Refinement of ATPG Test Patterns for Power-Based Hardware Trojan Detection Effectiveness Evaluation of Bit-Width Reduction in Power-Based Integrity Verification of Gate-Level Netlists Localizing Switching Activity in ATPG for Power-Based Integrity Verification of Gate-Level Netlists
Power Supply Failure	FORENSIC ANALYSIS OF I2C BUS INSTABILITY LEADING TO FAILURES IN MULTI-ASIC INFINIBAND SWITCH ARCHITECTURES
Power Supply Noise	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Power-On Self-Test	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
PRAC	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Predictive Analytics	VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management
Process Control	DEFECTIVE DIE COUNT (DDC) FOR YIELD FORECASTING AND SEMICONDUCTOR FABS DEFECT DENSITY CONTROL
Process Control Monitoring	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
process resilient	Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement
Process Validation	AI driven BEOL Testable Layout Pattern Enrichment
process variation	Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests
Production Test	Next-Generation Test Strategies for Direct RF Sampling AFEs: Achieving Lab-Grade Precision in a Production ATE Environment
Production Test Time Reduction	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
prompt analysis	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
PRPG	ATPG Extended Scan Power Control for Silicon Power Analysis
PyOTPL	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
Q
Quantum Circuit	Decision Diagram-based Fault Simulator for Quantum Circuits
R
Rack-Scale System	In-Situ TDR Test Fixture for End-to-End Signal Integrity Characterization and Debug in Rack-Scale Systems
rad-hard	Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
RAG	Transforming Failure Analysis Retrieval with Generative AI for Product Qualification ATPG Coverage Debug: The Shift to Agentic AI
Random Forest Classifiers	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
rank-to-rank spacing	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Rapid Yield Learning	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
RAS	Wafer Scale RAS Solution: Redundancy and System DFT in Cerebras WSE
raster	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
RDQS pattern coverage	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Redistribution Layer (RDL) Interconnects	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Redundancy	Joint ECC and Repair strategies for superior yield improvements
Register Transfer Level (RTL)	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level
Reinforcement learning	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
Reliability	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC Cryogenic Hot-Carrier Degradation in 65-nm nMOS Transistors and Its Impact on Analog Circuit Design Real-time voltage droop detection and functional monitoring telemetry for diagnosing and debugging SoCs
Repair	Joint ECC and Repair strategies for superior yield improvements
Repair Algorithm (RA)	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
reset control	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
Reset violations	Scan RTL DRC Fix Agent
Resistive defects	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
Resistive Random-Access Memory (ReRAM)	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
retrieval-augmented generation	From Test Floor to Thinking Floor: A Hardware-Grounded Architecture for AI Agents in Semiconductor Test ATPG Coverage Debug: The Shift to Agentic AI
RF	Bridging ATE and Bench: A Breakpoint-Driven Debug Architecture for 7GHz WLAN Firmware Integration
ring resonators	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
RISC-V	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
root cause analysis	ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability Transforming Failure Analysis Retrieval with Generative AI for Product Qualification AI based Multi-modal Feature Clustering Technology for Wafer Root Cause Analysis
root cause diagnosis	AI based Multi-modal Feature Clustering Technology for Wafer Root Cause Analysis
root-cause analysis	Toward Scalable AI-Driven SCAN Debug and Yield Learning
RRAMs	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level
S
S11 Correlation	Bridging ATE and Bench: A Breakpoint-Driven Debug Architecture for 7GHz WLAN Firmware Integration
Safe Operating Area (SOA)	Poster Submission: Post-Silicon Diagnosis of SOA-Induced Threshold Voltage Drift
Safety Critical Application	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
SBST	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Scan	Test Program Development and Debug Methods for SSN Productization on Zero DPPM Automotive N5 SoC Enabling Full Capability of Very Low Voltage (VLV) Scan Testing in Automotive SoCs ATPG Extended Scan Power Control for Silicon Power Analysis
scan compression	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
SCAN debug	Toward Scalable AI-Driven SCAN Debug and Yield Learning
scan design	Industrial Experience for Achieving Advanced Test Coverage
Scan Distribution Architecture	Test Strategies on Intel’s Next-Generation Multi-Die Client CPU
Scan Fabric	Test Strategies on Intel’s Next-Generation Multi-Die Client CPU
Scan Power	ATPG Extended Scan Power Control for Silicon Power Analysis
Scan Routing Fabric	Siemens Streaming Scan Network Comparision with Legacy Scan Routing Fabric
scan RTL DRC violations	Scan RTL DRC Fix Agent
Scan Shift Frequency Ramping	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Scan Switching	ATPG Extended Scan Power Control for Silicon Power Analysis
scan-based designs	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Schmoo plots	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
SDC	Precise Detection of FEoL Defects Using Cell-Aware Diagnosis
SDR	Fast-IO DDR for High Bandwidth SSN: Enabling Scalable DFT for Large SoCs
self-referencing	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
Semiconductor Manufacturing	DEFECTIVE DIE COUNT (DDC) FOR YIELD FORECASTING AND SEMICONDUCTOR FABS DEFECT DENSITY CONTROL
semiconductor test	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8 DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
Semiconductor Testing	AI driven BEOL Testable Layout Pattern Enrichment Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
Sensitive Layout Shapes	AI driven BEOL Testable Layout Pattern Enrichment
Sequence-Dependent Faults	RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects
Shannon entropy	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level
SHAP interpretability	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Sharpness-Aware Minimization (SAM)	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Shmoo Data	Memory Characterization using Advanced Pattern Clustering Analysis (PCA) utilizing state-of-the-art Frequency-Voltage (Shmoo) Tests
short and coupling defects	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
Side-channel Attack	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
Signal Integrity	In-Situ TDR Test Fixture for End-to-End Signal Integrity Characterization and Debug in Rack-Scale Systems
Silent Data Corruptions	In-field Monitoring of Permanent Faults in AI Accelerators Using Spiking Neural Networks
Silicon	ATPG Extended Scan Power Control for Silicon Power Analysis
Silicon Debug	ATPG Extended Scan Power Control for Silicon Power Analysis
Silicon Defects	AI driven BEOL Testable Layout Pattern Enrichment
Silicon Lifecycle Management	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management In-field Monitoring of Permanent Faults in AI Accelerators Using Spiking Neural Networks
Silicon Photonic Integrated Circuits	Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits
silicon test	Toward Scalable AI-Driven SCAN Debug and Yield Learning
Silicon Testing	AI driven BEOL Testable Layout Pattern Enrichment
Silicon Validation	Closing the Debug Loop: An LLM Agent That Root Causes Silicon Failures
Single-trace attack	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
site-to-site variation	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
small delay defect	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
SMBus	FORENSIC ANALYSIS OF I2C BUS INSTABILITY LEADING TO FAILURES IN MULTI-ASIC INFINIBAND SWITCH ARCHITECTURES
SoC	Enabling Full Capability of Very Low Voltage (VLV) Scan Testing in Automotive SoCs
SoC debug	Real-time voltage droop detection and functional monitoring telemetry for diagnosing and debugging SoCs
SOC Test	Test Strategies on Intel’s Next-Generation Multi-Die Client CPU
soft error	Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
Software-Based Self-Test	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Sparse Attention Mechanism	GTFD: A Graph-Based Sparse Attention Model for Fault Prediction in Digital Circuits
Specification Setting	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
Spectral Analysis	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level
Spiking Neural Networks	In-field Monitoring of Permanent Faults in AI Accelerators Using Spiking Neural Networks
SRAM	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products Joint ECC and Repair strategies for superior yield improvements
SRAM test	Implementation Challenges of Dual-Edge Triggered SRAMs in High-Performance Processors
SSN	Fast-IO DDR for High Bandwidth SSN: Enabling Scalable DFT for Large SoCs Test Program Development and Debug Methods for SSN Productization on Zero DPPM Automotive N5 SoC
Static compaction	IntelliCompact: RL-Guided Fault Clustering for Static Compaction of Deterministic Test Sets
static IR drop	Electro-Thermal Analysis and Design Approach for High-Power HPC Device Interface Boards
Stimulus Optimization	EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits
streaming scan network	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG Siemens Streaming Scan Network Comparision with Legacy Scan Routing Fabric
Streaming Scan Network (SSN)	Test Strategies on Intel’s Next-Generation Multi-Die Client CPU
Stress	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Structural test	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level A Silicon Validation of Analog Scan Testing Fault diagnosis of analog circuits using Bayesian framework and structural BIST
Supervised Fine-Tuning (SFT)	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Surrogate Modeling	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits
Switch Tray	In-Situ TDR Test Fixture for End-to-End Signal Integrity Characterization and Debug in Rack-Scale Systems
switch-level networks	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Switching	ATPG Extended Scan Power Control for Silicon Power Analysis
Synthetic Data	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
System Level Test	Wafer Scale RAS Solution: Redundancy and System DFT in Cerebras WSE
system-level test	A Flexible Multi-Die System-Level Test Architecture Leveraging In- System Test Controller (ISTC) and High-Speed IO (HSIO)
System-Level Test (SLT)	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
system-level validation	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
System-on-Chip	Accelerating Bus Connectivity Verification for Packet-Based Scan Delivery Network
System-on-Chip (SoC) Testing	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
Systematic Defects	AI driven BEOL Testable Layout Pattern Enrichment
T
TAP controller	A Scalable and Flexible Test Access Port (TAP) Architecture for Chiplet-Based Systems
target impedance	Electro-Thermal Analysis and Design Approach for High-Power HPC Device Interface Boards
TDR	In-Situ TDR Test Fixture for End-to-End Signal Integrity Characterization and Debug in Rack-Scale Systems
TDR Test Fixture	In-Situ TDR Test Fixture for End-to-End Signal Integrity Characterization and Debug in Rack-Scale Systems
Technology Mapping	Finding the Sweet Spot for Test Point Insertion in the Design Flow
Telemetry analytics	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management
Temperature-Aware Compensation	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Temporal Convolutional Network	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
Test	Test Program Development and Debug Methods for SSN Productization on Zero DPPM Automotive N5 SoC
Test application time (TAT)	Theoretical Limit Calculation: Packetized Scan Delivery with On-Chip Compare (OCComp) for N Identical Cores
test automation	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8 Accelerating Bus Connectivity Verification for Packet-Based Scan Delivery Network
Test Bandwidth Enhancement	Breaking the SoC Test Bottleneck: Faster, Protocol‑Free High‑Speed Test I/O
Test Compaction	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
Test Compression	Accelerated DFT Optimization Using Compression-aware ATPG Emulation
test cost	Industrial Experience for Achieving Advanced Test Coverage
Test Cost Optimization	AI driven BEOL Testable Layout Pattern Enrichment
Test Cost Reduction	Adaptive Burn-In using Ensemble Learning
Test Coverage	Industrial Experience for Achieving Advanced Test Coverage AI driven BEOL Testable Layout Pattern Enrichment ATPG Coverage Debug: The Shift to Agentic AI ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Test Data	Transforming Failure Analysis Retrieval with Generative AI for Product Qualification
Test data management	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Test data volume (TDV) reduction	Theoretical Limit Calculation: Packetized Scan Delivery with On-Chip Compare (OCComp) for N Identical Cores
test efficiency	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
test pattern generation	Optimization-Based Refinement of ATPG Test Patterns for Power-Based Hardware Trojan Detection
test point	Industrial Experience for Achieving Advanced Test Coverage
Test Point Insertion	Finding the Sweet Spot for Test Point Insertion in the Design Flow
test program automation	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
Test Program Development	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
test space optimization	Industrial Experience for Achieving Advanced Test Coverage
Test time	Fast-IO DDR for High Bandwidth SSN: Enabling Scalable DFT for Large SoCs
Test Time Reduction	Test Strategies on Intel’s Next-Generation Multi-Die Client CPU
Test-to-Design Feedback	Poster Submission: Post-Silicon Diagnosis of SOA-Induced Threshold Voltage Drift
Testability Improvement	Finding the Sweet Spot for Test Point Insertion in the Design Flow
testable	Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
Testing	EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Testpoint Insertion	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level
thermal control	Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing
Threshold Voltage Drift	Poster Submission: Post-Silicon Diagnosis of SOA-Induced Threshold Voltage Drift
Time-to-Digital Converter (TDC)	Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement
Timer	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
timing failures	Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests
Timing margins	Implementation Challenges of Dual-Edge Triggered SRAMs in High-Performance Processors
timing-aware	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
tip burn	Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing
toggle coverage	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Tokens	IEA: Balancing Intelligence, Cost, and Control in Agentic Engineering Analytics
Topology Authentication	THETA: Topology-Aware Secure Boot in Heterogeneous Integration for Trust and Assurance
TPA	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
transient IR drop	Electro-Thermal Analysis and Design Approach for High-Power HPC Device Interface Boards
transition delay fault	Localizing Switching Activity in ATPG for Power-Based Integrity Verification of Gate-Level Netlists
trim fuse characterization	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
Trojan Detection	Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
true random number generation	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Trust	Developing Hardware Trojan Benchmarks for Testing Bitstream-level Detection Methods
U
UDFM	Precise Detection of FEoL Defects Using Cell-Aware Diagnosis ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
UltraflexPlus	Test Program Development and Debug Methods for SSN Productization on Zero DPPM Automotive N5 SoC
unsupervised learning	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
User defined MBIST Algorithm	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
User defined operation set	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
V
Vernier effect	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
VLSI Testing	AI driven BEOL Testable Layout Pattern Enrichment
VLV	Enabling Full Capability of Very Low Voltage (VLV) Scan Testing in Automotive SoCs
Vmax test	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Vmin analysis	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
vmin comparison	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Voltage droop detection	Real-time voltage droop detection and functional monitoring telemetry for diagnosing and debugging SoCs
Voltage-Aware Testing	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
W
wafer and SEM inspection	Fab-Ready Zero-Shot Anomaly Detection and Segmentation for Wafer and SEM Inspection
wafer defect classification	CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification
wafer level thermal issue	Temperature Management with Active Coolant Thermal Control (ACTC) in High-Power AI Chip Testing
wafer map pattern recognition	AI based Multi-modal Feature Clustering Technology for Wafer Root Cause Analysis
Wafer Scale	Wafer Scale RAS Solution: Redundancy and System DFT in Cerebras WSE
wafer study	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Wafer-Level Test	AI driven BEOL Testable Layout Pattern Enrichment
Warpage	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Workflow	Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons
workflow orchestration	Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering
X
XOR-MUX	GTFD: A Graph-Based Sparse Attention Model for Fault Prediction in Digital Circuits
Y
Yeild Optimization	DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration
yield	Toward Scalable AI-Driven SCAN Debug and Yield Learning Precise Detection of FEoL Defects Using Cell-Aware Diagnosis
Yield Analysis	Layout Change-Driven Failure Risk Prediction for Fast Failure Localization
Yield enhancement	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Yield Learning	AI driven BEOL Testable Layout Pattern Enrichment
Yield Optimization	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Yield Prediction	DEFECTIVE DIE COUNT (DDC) FOR YIELD FORECASTING AND SEMICONDUCTOR FABS DEFECT DENSITY CONTROL
Z
zero defects	ASPG: Automated Stress Pattern Generation using Layout-Aware Defect-Oriented Stress (LA-DOS) UDFM for Zero Defect Automotive Designs
Zero-shot anomaly detection	Fab-Ready Zero-Shot Anomaly Detection and Segmentation for Wafer and SEM Inspection

Disclaimer | Powered by EasyChair Smart Program