ITC 2026: 2026 IEEE INTERNATIONAL TEST CONFERENCE

This page contains an index consisting of author-provided keywords.

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3nm Technology	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
A
Adaptive Test	Adaptive Burn-In using Ensemble Learning
Advanced Process	Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Advantest SmarTest 8	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
AES	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
Agent for Testing	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
agentic	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
agentic AI	Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development Toward Scalable AI-Driven SCAN Debug and Yield Learning Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons Scan RTL DRC Fix Agent
agentic workflow	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
AI	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation Scalable, Secure Chat-Based Analytics for Semiconductor Test Closing the Debug Loop: An LLM Agent That Root Causes Silicon Failures
AI Agents	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context IEA: Balancing Intelligence, Cost, and Control in Agentic Engineering Analytics
AI assisted coverage	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
AI in EDA	AI driven BEOL Testable Layout Pattern Enrichment
AI/Machine Learning	Industrial Experience for Achieving Advanced Test Coverage
all-digital	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
All-Digital Phase-Locked Loop (ADPLL)	Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement
Alternate Test	EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits
analog ATPG	A Silicon Validation of Analog Scan Testing
analog DfT	A Silicon Validation of Analog Scan Testing
Analog Test	Fault diagnosis of analog circuits using Bayesian framework and structural BIST
Analog/Mixed-Signal Circuits (AMS)	EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits
Analytics	Scalable, Secure Chat-Based Analytics for Semiconductor Test AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis IEA: Balancing Intelligence, Cost, and Control in Agentic Engineering Analytics
And-Inverter Graph (AIG)	Finding the Sweet Spot for Test Point Insertion in the Design Flow
anomaly detection	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management Automated Issue Site Detection in Multi-Site Testing via Isolation forest
anomaly diagnosis	LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management
Approximation	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Area Optimization	Finding the Sweet Spot for Test Point Insertion in the Design Flow
array	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
Artificial Intelligence (AI)	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
ATE	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
ATE Test Pattern Generation	AI driven BEOL Testable Layout Pattern Enrichment
ATPG	DEFT: Differentiable Automatic Test Pattern Generation Industrial Experience for Achieving Advanced Test Coverage RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits Toward Scalable AI-Driven SCAN Debug and Yield Learning
Automated Test Pattern Generation	Speeding up DFT Recommendation Systems with limited-compute resources
automatic test equipment (ATE)	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
Automatic Test Pattern Generation	Accelerated DFT Optimization Using Compression-aware ATPG Emulation
Automatic Test Pattern Generation (ATPG)	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation AI driven BEOL Testable Layout Pattern Enrichment
Automotive ASIL-D	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Automotive DPPM	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
B
Back-End-of-Line (BEOL)	AI driven BEOL Testable Layout Pattern Enrichment
Backend Routing	AI driven BEOL Testable Layout Pattern Enrichment
BIST	Fault diagnosis of analog circuits using Bayesian framework and structural BIST Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
Bit-flip Fault	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Bridge Defects	AI driven BEOL Testable Layout Pattern Enrichment
Built In Self Test	Fault diagnosis of analog circuits using Bayesian framework and structural BIST
Burn-In	Adaptive Burn-In using Ensemble Learning
C
cell-aware test	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Characterization	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
chip probe	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Chiplet	A Methodology for AI-based Defect Detection and Localization for 3D Chiplet Interconnects DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration
CI/CD	Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering
Circuit Optimization	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation
circuit simulation	Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests
class imbalance	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
clock gating	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
Clock violations	Scan RTL DRC Fix Agent
Cluster-Based Diagnosis	EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits
CMD-CMD spacing	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
CMOS image sensor (CIS)	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
CNOD	Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Columnar query engine	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Computation-in-memory	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level
Compute-in-memory	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
Computing-in-Memory (CIM)	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
concurrent fault simulation	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Conformal calibration	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management
constrained randomization	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Countermeasure	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
coverage driven verification	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
CPA	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
CPO Circuit	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Custom AI Accelerator	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
customization	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
D
dashboard generation	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
Data Analytics	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context
Data-driven diagnosis	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management
Decision Diagrams	Decision Diagram-based Fault Simulator for Quantum Circuits
Deep Neural Network	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
Deep Neural Networks	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
defect	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
defect analysis	ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability
defect clustering	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
Defect detection	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Defect Diagnosis	AI driven BEOL Testable Layout Pattern Enrichment
Defect learning	Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Defect-based test	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
Deploying	Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons
Design for security	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Design for Test	Accelerated DFT Optimization Using Compression-aware ATPG Emulation Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG Speeding up DFT Recommendation Systems with limited-compute resources
Design for Test (DFT)	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
Design for Testability (DFT)	AI driven BEOL Testable Layout Pattern Enrichment
design validation	Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering
Design-for-Manufacturing (DFM)	AI driven BEOL Testable Layout Pattern Enrichment
Design-for-test	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
Design-for-Test (DFT)	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
Design-for-Testability	Scan RTL DRC Fix Agent
Device Variability	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
DFT	Industrial Experience for Achieving Advanced Test Coverage Toward Scalable AI-Driven SCAN Debug and Yield Learning
Diagnostic feedback	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
Die-Level Test	AI driven BEOL Testable Layout Pattern Enrichment
Differentiable Programming	DEFT: Differentiable Automatic Test Pattern Generation
diffusion models	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
diffusion transformer	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
Digital Capture Debug	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
Digital twin	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management
Direct Memory Access	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
divergence tracking	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
DMAIC	Toward Scalable AI-Driven SCAN Debug and Yield Learning
DRAM	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
DV analysis	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
DWR	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
Dynamic scan control	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
E
E-graph	E-ATPG: Testability-Aware E-graph Rewriting for Automatic Test Pattern Generation
early performance binning	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
EDA Tools	AI driven BEOL Testable Layout Pattern Enrichment
EDS Test Simulation	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Electrical Die Sorting (EDS)	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
Electrical Test	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
Electromagnetic fault injection (EMFI)	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
Electromigration-induced aging	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Emerging Technology	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
Engineering Productivity	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
erratic bit detection	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
Error Correction Code	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Error Correction Code (ECC)	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
EUV-based Process	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
F
fabrication process variation	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
Failure Analysis	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs Layout Change-Driven Failure Risk Prediction for Fast Failure Localization Transforming Failure Analysis Retrieval with Generative AI for Product Qualification
Fan-out Wafer-Level Packaging	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Fault Analysis	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Fault Coverage	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures AI driven BEOL Testable Layout Pattern Enrichment
Fault diagnosis	Fault diagnosis of analog circuits using Bayesian framework and structural BIST
fault grading	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Fault modeling	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Fault Modelling	AI driven BEOL Testable Layout Pattern Enrichment
Fault Simulation	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells Decision Diagram-based Fault Simulator for Quantum Circuits
Fault-aware Training	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Fault-Tolerant Quantum Computing	Decision Diagram-based Fault Simulator for Quantum Circuits
feature specific coverage	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Field monitoring	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management
Fine-Grain Fault Modeling	RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects
FinFET	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Formal Verification	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
FPGA oversampling-based soft logic	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Full Scan	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level
Functional Safety Analysis	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Functional Test	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
G
Gaussian Mixture Models	EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits
Generative AI	Scalable, Secure Chat-Based Analytics for Semiconductor Test
generative data augmentation	CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification
GitHub Copilot	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
gradient boosting	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Graph Neural Network	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
graph theory	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
H
Hardware coprocessor	JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
Hardware Fuzzing	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
hardware root of trust	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Hardware Security	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Hardware Telemetry	VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management
hash functions	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
HB-IJTAG	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing
HBM test	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing
Heterogeneous integration	THETA: Topology-Aware Secure Boot in Heterogeneous Integration for Trust and Assurance
Hierarchical Test Strategy	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
High Bandwidth Memory (HBM)	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
High Performance Computing	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
High-volume manufacturing	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
HPC	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
HVM	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
hybrid trust model	Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering
hyperdimensional computing	LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management
I
IC security and reliability	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
IC testing	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
IEEE 1838	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
IJTAG	A Silicon Validation of Analog Scan Testing
In-field test	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management
In-System Test	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Information Flow Tracking	DiamondBlade: Scalable Information Flow Tracking Based on Semantic Path Decomposition
Inter-cell defects	Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
Inter-Metal Layer Bridges	AI driven BEOL Testable Layout Pattern Enrichment
Interconnect	A Methodology for AI-based Defect Detection and Localization for 3D Chiplet Interconnects
Interconnect test	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing
intra-cell defect	Accelerating Cell-Aware Test Characterization via Defect Equivalence-Based Simulation Pruning and Structural Analysis
IP Piracy	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
Isolation Forest	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
L
lab automation	Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering
large language models	ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability
Large Language Models (LLMs)	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
Layout Similarity	Layout Change-Driven Failure Risk Prediction for Fast Failure Localization
Lean Six Sigma	Toward Scalable AI-Driven SCAN Debug and Yield Learning
Linear Programming	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
LLM	IEA-Connect: One Engineer's Solution Becomes Another Engineer's Context Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation Scalable, Secure Chat-Based Analytics for Semiconductor Test Transforming Failure Analysis Retrieval with Generative AI for Product Qualification Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering Closing the Debug Loop: An LLM Agent That Root Causes Silicon Failures
LLM automation	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
LLMs	IEA: Balancing Intelligence, Cost, and Control in Agentic Engineering Analytics
Logic BIST	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Logic Locking	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
lot-level diagnostics	ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability
Low compute	Speeding up DFT Recommendation Systems with limited-compute resources
lpddr6	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
lumped delay	Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests
M
Machine Learning	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage Adaptive Burn-In using Ensemble Learning AI driven BEOL Testable Layout Pattern Enrichment
Malware Detection	JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
Manufacturing Test	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
Matching	DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration
Maximin Optimization	Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits
MBIST	Parallelized Instrument Access via High-Bandwidth IJTAG for Efficient HBM Testing Improving Yield Through Advanced Detection of High-Speed Memory Access Failures AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
MCP	Scalable, Secure Chat-Based Analytics for Semiconductor Test Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering
Memory Built-In Self-Test (MBIST)	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
Memory repair	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Memory test algorithms	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Micro-bump	A Methodology for AI-based Defect Detection and Localization for 3D Chiplet Interconnects
MIPI C-PHY	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
MIPI Camera Serial Interface (CSI-2)	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
MIPI D-PHY	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Mirroring modulators	A Pre-Silicon Multi-Physics Framework for Electromagnetic Fault Injection Analysis in Co-Packaged Optics
mission-mode testing	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
ML	Scalable, Secure Chat-Based Analytics for Semiconductor Test
ML attacks	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
ML in EDA	AI driven BEOL Testable Layout Pattern Enrichment
model collapse	CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification
Monte Carlo Simulation	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
MRAM	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
multi-agent reasoning	ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability
Multi-Chiplet Integration	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
multi-mode SoC testing	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
multi-site testing	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
multi-stage test data integration	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Multimodal Retrieval	Transforming Failure Analysis Retrieval with Generative AI for Product Qualification
Multivariate Outlier Detection	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
N
Neural Network	DEFT: Differentiable Automatic Test Pattern Generation
Noisy Intermediate-Scale Quantum	Decision Diagram-based Fault Simulator for Quantum Circuits
nonlinear ciphers	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
O
Obfuscation	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
on-chip calibration	Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement
on-chip diagnosis	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
One-Way Varactor Cell (OWVC)	Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement
Optimization	Accelerated DFT Optimization Using Compression-aware ATPG Emulation
OTPL	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
Otsu thresholding	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
Output Obfuscation	A Novel Integer Linear Programming Approach for Maximizing Output Obfuscation in Logic Locking
P
Package-Level Test	AI driven BEOL Testable Layout Pattern Enrichment
path delay testing	Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests
Pattern-aware difference	Layout Change-Driven Failure Risk Prediction for Fast Failure Localization
PEPR	RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects
performance binning prediction	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Performance Optimization	Finding the Sweet Spot for Test Point Insertion in the Design Flow
PFA	Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study
photonics	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
Physical tampering	THETA: Topology-Aware Secure Boot in Heterogeneous Integration for Trust and Assurance
Physical Test Coverage	AI driven BEOL Testable Layout Pattern Enrichment
Post Silicon Validation	Adaptive Burn-In using Ensemble Learning
Post-Si Debug	Closing the Debug Loop: An LLM Agent That Root Causes Silicon Failures
Post-Silicon Tuning	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles
Power Delivery Network	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Power Supply Noise	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
Power-On Self-Test	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
PRAC	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Predictive Analytics	VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management
Process Control Monitoring	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
process resilient	Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement
Process Validation	AI driven BEOL Testable Layout Pattern Enrichment
process variation	Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests
prompt analysis	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
PyOTPL	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
Q
Quantum Circuit	Decision Diagram-based Fault Simulator for Quantum Circuits
R
rad-hard	Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
RAG	Transforming Failure Analysis Retrieval with Generative AI for Product Qualification
Random Forest Classifiers	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
rank-to-rank spacing	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Rapid Yield Learning	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
raster	AI-Empowered ArrayInsights: An Agentic Workflow for Layout-Aware MBIST Defect Analysis
RDQS pattern coverage	AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage
Redistribution Layer (RDL) Interconnects	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Register Transfer Level (RTL)	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level
Reinforcement Learning	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
Reliability	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
Repair Algorithm (RA)	A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM
reset control	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
Reset violations	Scan RTL DRC Fix Agent
Resistive defects	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
Resistive Random-Access Memory (ReRAM)	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
ring resonators	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
RISC-V	HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing JTAG-Based Coprocessor for Wear-Out, Fault Injection and Malware Detection in RISC-V
root cause analysis	ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and Explainability Transforming Failure Analysis Retrieval with Generative AI for Product Qualification
root-cause analysis	Toward Scalable AI-Driven SCAN Debug and Yield Learning
RRAMs	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level
S
Safety Critical Application	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
SBST	Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
scan compression	A Dynamic Scan Architecture for Unified Reset and Clock-Gate Control in Multi-Mode SoC Testing
SCAN debug	Toward Scalable AI-Driven SCAN Debug and Yield Learning
scan design	Industrial Experience for Achieving Advanced Test Coverage
scan RTL DRC violations	Scan RTL DRC Fix Agent
Scan Shift Frequency Ramping	Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server SoCs
scan-based designs	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Schmoo plots	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
self-referencing	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
semiconductor test	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8 DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
Semiconductor Testing	AI driven BEOL Testable Layout Pattern Enrichment
Sensitive Layout Shapes	AI driven BEOL Testable Layout Pattern Enrichment
Sequence-Dependent Faults	RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects
Shannon entropy	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level
SHAP interpretability	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
Sharpness-Aware Minimization (SAM)	RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate ECC
short and coupling defects	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
Side-channel Attack	LEO-CIM: Lightweight Execution Obfuscation to Secure MRAM-Based Compute-in-Memory against Side-Channel Attacks
Silicon Defects	AI driven BEOL Testable Layout Pattern Enrichment
Silicon Lifecycle Management	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management
Silicon Photonic Integrated Circuits	Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits
silicon test	Toward Scalable AI-Driven SCAN Debug and Yield Learning
Silicon Testing	AI driven BEOL Testable Layout Pattern Enrichment
Silicon Validation	Closing the Debug Loop: An LLM Agent That Root Causes Silicon Failures
Single-trace attack	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
site-to-site variation	Automated Issue Site Detection in Multi-Site Testing via Isolation forest
small delay defect	An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die Packages
soft error	Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
Software-Based Self-Test	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
Specification Setting	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
Spectral Analysis	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level
SRAM	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Stimulus Optimization	EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits
streaming scan network	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
Stress	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
structural test	Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level A Silicon Validation of Analog Scan Testing Fault diagnosis of analog circuits using Bayesian framework and structural BIST
Supervised Fine-Tuning (SFT)	Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL Design
Surrogate Modeling	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles Defect-Oriented, Optimization-Driven ATPG for Silicon Photonic Integrated Circuits
switch-level networks	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Synthetic Data	Beyond Monte Carlo: Improved Wafer Acceptance Test (WAT) Limit Setting via Correlation-Aware Synthetic Data Generation
System-Level Test (SLT)	A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level Validation
system-level validation	An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY Support
Systematic Defects	AI driven BEOL Testable Layout Pattern Enrichment
T
Technology Mapping	Finding the Sweet Spot for Test Point Insertion in the Design Flow
telemetry analytics	DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management
Temperature-Aware Compensation	TAC-CIM: Temperature-Aware Current Compensation for Accurate ReRAM-Based Computing-in-Memory Architectures
Temporal Convolutional Network	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
Test Automation	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
Test Compaction	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
Test Compression	Accelerated DFT Optimization Using Compression-aware ATPG Emulation
test cost	Industrial Experience for Achieving Advanced Test Coverage
Test Cost Optimization	AI driven BEOL Testable Layout Pattern Enrichment
Test Cost Reduction	Adaptive Burn-In using Ensemble Learning
test coverage	Industrial Experience for Achieving Advanced Test Coverage AI driven BEOL Testable Layout Pattern Enrichment
Test Data	Transforming Failure Analysis Retrieval with Generative AI for Product Qualification
Test data management	AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs
test efficiency	An Interpretable, Production-Scale Machine-Learning Framework for Early CPU Performance Binning at the CP Stage
test point	Industrial Experience for Achieving Advanced Test Coverage
Test Point Insertion	Finding the Sweet Spot for Test Point Insertion in the Design Flow
test program automation	PyOTPL: A Python Abstraction Layer for Scalable, AI-Friendly ATE Test Program Development
Test Program Development	Accelerating Semiconductor Test Development Using Large Language Models on Advantest SmarTest 8
test space optimization	Industrial Experience for Achieving Advanced Test Coverage
Testability Improvement	Finding the Sweet Spot for Test Point Insertion in the Design Flow
testable	Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops
Testing	EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal Circuits Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation
Testpoint Insertion	Spectral-Entropy for Enhanced Testability and Efficient Scan Insertion at RTL Level
Time-to-Digital Converter (TDC)	Built-In Self-Calibration for Time-to-Digital Converter Used in Clock Period Measurement
Timer	A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules
timing failures	Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests
timing-aware	Scalable Timing-aware Concurrent Fault Simulation for Transistor-level DRAM Peripheral Circuits
Tokens	IEA: Balancing Intelligence, Cost, and Control in Agentic Engineering Analytics
Topology Authentication	THETA: Topology-Aware Secure Boot in Heterogeneous Integration for Trust and Assurance
TPA	Towards Single-Trace AES Key Recovery Using Random Forest Classifiers Based on Key Values
trim fuse characterization	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
true random number generation	Hardware Root of Trust for SSN-based Designs with High-Bandwidth IJTAG
U
unsupervised learning	Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection
User defined MBIST Algorithm	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
User defined operation set	Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
V
Vernier effect	A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators
VLSI Testing	AI driven BEOL Testable Layout Pattern Enrichment
Vmax test	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products
Vmin analysis	DVInsights: An Agentic Workflow for Automated Array Design Verification Dashboard Generation
Voltage-Aware Testing	SPADE-AI: A SPICE-Accurate, DEfect-Aware AI Surrogate Model Driven Ultra-Efficient Test Generation for Resistive Defects in Standard Cells
W
wafer defect classification	CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification
Wafer-Level Test	AI driven BEOL Testable Layout Pattern Enrichment
Warpage	STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level Packaging
Workflow	Deploying Agentic AI in the Semiconductor Industry: Challenges and Lessons
workflow orchestration	Cascade: Visual Agentic Workflow Orchestration for Semiconductor Test and Validation Engineering
Y
Yeild Optimization	DT-MATCH: Defect- and Topology-Aware Chiplet Matching for Yield Optimization in Heterogeneous Integration
yield	Toward Scalable AI-Driven SCAN Debug and Yield Learning
Yield Analysis	Layout Change-Driven Failure Risk Prediction for Fast Failure Localization
Yield enhancement	An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products Improving Yield Through Advanced Detection of High-Speed Memory Access Failures
Yield Learning	AI driven BEOL Testable Layout Pattern Enrichment
Yield Optimization	Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model Ensembles

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