ABSTRACT. Pre-silicon critical node identification is essential for RTL reliability analysis, yet conventional fault simulation is costly in early design stages. We propose an LLM-based framework that reframes this task as structured report generation from RTL and testbench context. A hierarchy-aware preprocessing pipeline enables scalability via report merging, indexed node compression, and adaptive simplification. Using an AVF-aligned SFT dataset, a PEFT-tuned Qwen3.5 model generates machine-readable fault reports, whose outputs further guide a GPT-based hardening agent, enabling an efficient shift-left workflow for reliability analysis and RTL refinement.

ABSTRACT. SBST for microprocessors remains expert-intensive, and unconstrained LLMs often violate microarchitectural constraints. We propose a closed-loop framework that converts gate-level fault simulation into feedback for iterative test generation, combining deterministic synthesis, LLM-guided exploration, AST-aware micro-fuzzing, sanitization, and watchdog-bounded execution. On the CV32E40P RISC-V core, it achieves 83.26% overall stuck-at fault coverage and 95.38% on the Multiplier by the 7th generation iteration with Claude Sonnet 3.5. The default run costs about $5 in API fees, while DeepSeek reduces cost to $0.64 with comparable overall effectiveness.

ABSTRACT. Rapid yield learning while ensuring automotive quality of <1 DPPM is a challenge for automotive SOCs in advanced EUV-based process technologies. This paper presents casestudies of AI-driven test efficiency tools spanning a columnar Parquet-based lakehouse enabling accelerated analytical query performance through in-memory processing; unifying fragmented multi-insertion test data with failure analysis and design databases; a cross-layer diagnostic feedback loop linking confirmed failure analysis outcomes to enable targeted wafer selection; and an autoencoder-based multivariate outlier screen for escape reduction beyond traditional parametric limits. All are deployed in HVM production on automotive SoCs targeting sub-1 DPPM.

ABSTRACT. Massive multi-site testing underpins high-throughput semiconductor manufacturing, yet its parallel architecture introduces hardware-induced systematic errors that corrupt measurements. Detection is difficult because affected site count is unknown a priori, and production test distributions are rarely Gaussian. Existing methods require hand-tuned reference distributions or user-specified contamination thresholds unavailable in unsupervised environments. We present a fully automated, distribution-agnostic framework casting site detection as an unsupervised anomaly detection problem. Normalized histogram density vectors represent each site; an Isolation Forest scores them, and adaptive Otsu thresholding yields binary classification without user input. Validated on Texas Instruments production data, the framework outperforms state-of-the-art approaches.

ABSTRACT. The growing adoption of custom AI accelerators by hyperscalers and fabless companies demands a manufacturing test methodology that goes beyond conventional GPU validation paradigms. This paper establishes a hierarchical, end-to-end test strategy spanning ATE, board, system, and network-level validation framework for multi-chiplet AI ASICs. The methodology integrates a CI/CD-driven test release pipeline, generation-agnostic parameterized test assets, and a structured DFT strategy combining MBIST, ATPG, and system-level test. Quantitative ATE escape analysis provides empirical justification for system-level test infrastructure. Together, these principles form a replicable blueprint for maximizing fault coverage, reducing time-to-market, and sustaining test quality at scale.

ABSTRACT. Selection of optimal test compressor configuration in a DFT architecture is crucial for minimizing test cost. Exploration of this configuration can be a time-consuming process for large and complex designs. In limited-compute scenarios, this problem is exacerbated as several configurations may not be run in parallel. This work explores the effectiveness of methods such as stopping runs early, word-level parallelism, truncation of secondary faults and selection of a subset of total faults to drastically reduce exploration time without inflating test cost. All DFT exploration experiments in this work utilize ATPG to give accurate estimates for test cost and test coverage.

ABSTRACT. The complexity of modern hardware systems creates a large surface for information flows that break the confidentiality or integrity of classified information. Current approaches to detecting malicious information flows, such as information flow tracking, lack scalability to complex computing systems or compromise accuracy. This paper proposes DiamondBlade, a generalized and precise information flow tracking approach based on formal verification. DiamondBlade extends a 2-instance computational model with optimizations, enabling it to scale to complex systems and provide formal security guarantees. We demonstrate DiamondBlade in case studies on an AES implementation, the Caliptra HMAC unit, the BOOM processor and the Pulpissimo SoC.

ABSTRACT. This paper presents a concurrent fault simulation methodology tailored for timing-critical and transistor-level memory peripheral circuits. Existing concurrent fault simulators support only simplified timing abstractions, and extending them to annotated delay models poses two challenges: temporal divergence may occur without logic value divergence, and delay selection depends on passive state that lacks explicit fanout for event-driven tracking. The proposed method addresses these challenges by extending divergence tracking to a two-dimensional space spanning both logic values and temporal state, independently maintaining passive contributors within faulty machines, and establishing hierarchical port fault semantics with injection flags that constrain fault effects within switch-level hierarchies. Validation on industrial DRAM circuits demonstrates an average simulation speedup of approximately 44× while maintaining a coverage delta of at most 0.17% compared to the serial simulation mode.

ABSTRACT. Cell-aware test (CAT) characterization is often hindered by the high cost of SPICE simulations. While structural analysis can prune these simulations, prior methods like TrUnDeL focus on identifying structurally undetected cases and overlook significant optimization opportunities. We propose GroStra, a framework that enhances efficiency through three strategies: defect equivalence-Based simulation pruning, guaranteed-detected structural analysis, and using static analysis to accelerate dynamic graph processing. Experimental results on ASAP7 and 12nm libraries demonstrate that GroStra reduces simulation effort by up to 25.4% and 32.6% over TrUnDeL and achieves up to a 15x and 55x speedup, significantly lowering characterization costs without sacrificing accuracy.

ABSTRACT. As high operating voltages are required to meet HPC high clock frequency operations (>5.5GHz), memory failure rates under Vmax have become comparable to those under Vnom (0.75V) and Vmin (0.6V). This work presents Vmax defect analysis of 0.28MBit 6T-SRAM IP (4096×69) in 3nm FinFET HPC chips. An innovative Vmax test methodology combining multiple voltage/frequency tests, diverse memory algorithms, and weak read/write assist enables Vmax defect screening and redundancy repair, reducing Vmax failures by >90%, improving overall Vmax-to-total memory yield loss ratio to <15%, with only 0.2% test time increase. PFA results and fault model are included.

ABSTRACT. Abnormal behavior in semiconductor memory IPs can significantly impact overall yield, requiring flexible mitigation strategies. This work presents a case where conventional MBIST techniques proved insufficient. Certain chips exhibited functional failures during Direct Memory Access burst mode, where address transitions occur every clock cycle. Despite passing MBIST tests and showing no abnormalities in Schmoo plots, failures persisted in functional testing. Analysis revealed the root cause as the memory’s inability to do continuous read and write, requiring address transitions every cycle for detection. Leveraging the capabilities of Siemens Tessent, a custom operation set was developed to effectively detect such failures.

ABSTRACT. In advanced nodes, unmodeled faults escape scan testing, making functional system-level tests essential but insufficient post-manufacturing screens. We target hard-to-detect timing failures from random process variations impacting multiple circuit-path gates-undetected by TDF, cell-aware, and timing-aware tests assuming a single localized defect. Using a hybrid simulation strategy-equivalent to 1.9 trillion Monte Carlo SPICE simulations-we characterize rare, extremely slow paths. We find at low voltages, a single extremely slow transistor dominates path delays-enabling lumped-delay TDF detection-while above an 'inflection' voltage, delay distributes across moderately slow transistors. We explain this abrupt compositional shift and propose testing strategy spanning entire range of operating voltages.

ABSTRACT. Silicon photonics is advancing rapidly due to increasing demand for high-speed data transmission in computing, communication, and AI systems. This growth necessitates improved testing techniques for photonic circuits. This paper presents a Vernier-based self-referencing test cell for detecting local fabrication imperfections in silicon photonic ring resonators without external references or power tapping. The proposed test cell magnifies picometer-scale resonance errors by approximately 15 times, improving observability. Its self-referencing mechanism suppresses global temperature effect, enabling the detection of local fabrication process variations. The proposed test cell therefore provides a compact on-chip design-for-test solution for process variation detection in photonic integrated circuits.

ABSTRACT. Resistive Random Access Memory (RRAM) is a promising technology to implement deep neural network (DNN) accelerators. Current test approaches provide mitigation schemes at system-level with inaccurate fault modeling or March-type circuit-level test sequences that cannot scale to full system. We provide a 3-step testing framework for RRAM DNN Accelerators that covers all 3 levels of a hardware accelerator: circuit, single-layer, and the full DNN. We develop fault models that bridge all 3 DNN levels, which are used to develop efficient structural test images for the complete system. Results show a 50% test time reduction without losing defect coverage.

ABSTRACT. Chiplet-based fan-out wafer-level packaging (FOWLP) enables ultra-dense redistribution layer (RDL) interconnects for emerging high-bandwidth systems, but also increases vulnerability to thermo-mechanical stress and electromigration (EM)-induced degradation under non-uniform chiplet power dissipation. Conventional finite-element analysis is too expensive for repeated workload-dependent reliability evaluation, while compact EM models often rely on simplified stress conditions. We present a multi-scale, stress-aware framework for EM reliability assessment in FOWLP interconnects. A POD-ridge reduced-order model predicts package deformation from thermal profiles, and an adapted StressNet model predicts local RDL stress from deformation and layout geometry. These stresses are then incorporated into a compact EM model.

ABSTRACT. Generative data augmentation for wafer map defect classification suffers from iterative model collapse, where repeated retraining on synthetic data narrows the generated distribution and erodes rare defect diversity. We present CREW, a collapse-resilient framework that combines a physics-informed diffusion model with fabrication priors, a tail-aware sample selection strategy, and an involution-based classifier with spatially adaptive kernels. Experiments on a public wafer defect dataset demonstrate 99.3% classification accuracy, 19–138% improvement in structural similarity index measure (SSIM), and 12–34% improvement in peak signal-to-noise ratio (PSNR) over state-of-the-art baselines, while preserving rare defect coverage across iterative retraining cycles.

ABSTRACT. Wafer map defect classification and root cause attribution are typically treated as disconnected stages, ignoring lot-wide manufacturing context and yielding fragmented, unverifiable diagnostics. We propose ORACLE (Orchestrated Reasoning Agents for Classification and Lot-aware Explanation), a multi-agent framework integrating vision, language-model reasoning, and knowledge-graph retrieval for explainable defect classification and automated root-cause attribution. ORACLE introduces rotation-invariant geometric feature extraction, dynamic evidence quality fusion with calibrated per-source weights, and a lot context aggregation agent that consolidates sibling wafer evidence to distinguish systematic equipment failures from random excursions. Experiments on an industry benchmark demonstrate 94.3% classification accuracy with actionable, lot-aware diagnostic intelligence.

ABSTRACT. Latent defect screening is challenged by extremely low failure rates, high-dimensional test data, and absence of labeled anomalies. We propose the first unsupervised anomaly detection framework incorporating a Diffusion Transformer. Raw test measurements are first compressed by an autoencoder, then reshaped into a structured token sequence enriched with sinusoidal and per-device wafer-position embeddings. Anomaly scores are derived from the noise-prediction error over mid-range diffusion timesteps, enabling fast wafer-scale screening without any labeled defects or manual feature engineering. Our approach achieves state-of-the-art performance on industrial 16nm IC test data under extreme class imbalance, offering interpretable failure localization through latent-space reconstruction residuals.

ABSTRACT. Fine-tuning the operational parameters of mixed-signal ASICs is becoming increasingly challenging due to the growing complexity of modern designs. We propose a multi-objective tuning approach based on ensembles of probabilistic surrogate models to efficiently identify operating points satisfying a given specification. The method explicitly leverages predictive uncertainty to guide sampling while characterization, reducing the number of required measurements compared to baseline methods. We evaluate the approach using measurement data from nine ring oscillator ASICs, optimizing for frequency, jitter, and power consumption. To support reproducibility and further research, the characterization measurement dataset is publicly released with this work.

ABSTRACT. Diagnosis of modular Analog/Mixed-Signal (AMS) circuits is challenging because faults arising in different constituent blocks can produce indistinguishable response behaviors under conventional test generation, limiting the ability to localize the source of failure. This is because existing test generation approaches are primarily designed for pass/fail discrimination rather than module-level diagnosis. This paper presents a test optimization and response analysis framework for diagnosis of modular AMS circuits using Gaussian Mixture Models (GMMs). It is shown that careful test stimulus optimization enables GMM clustering such that faulty behavior can be mapped to faults in specific modules with high probability.

ABSTRACT. The integration of analog and digital components in SoCs makes analog circuits susceptible to defects, while accurate transistor-level fault diagnosis remains challenging. This paper presents a Bayesian framework for diagnosis using delay-based structural BIST. Multiple delay measurements, captured from injected perturbations, are used as diagnostic signatures and processed using probabilistic inference to estimate fault likelihoods under process variations. The framework is validated on a 65nm circuit with 416 transistor-level faults, achieving up to 0.993 diagnostic efficiency. The proposed method incurs minimal hardware overhead (0.002%) and sub-second execution time, making it suitable for post-silicon debug and in-field applications.

ABSTRACT. Scan-based LBIST is central to automotive ASIL-D fault coverage and increasingly used for in-system test in server platforms. As geometries scale, abrupt transitions between scan-shift inactivity and full-speed clocking produce inductive power supply noise that causes yield-impacting test failures, particularly under mission-mode PDN conditions on customer boards. This paper presents a programmable LBIST controller enhancement that introduces scan shift frequency ramp-up and ramp-down around every scan operation. The ramp profile is post-silicon tunable across PVT corners with negligible area overhead and no fault-coverage loss. PDN-aware simulations on representative automotive SoC designs quantify supply-rail droop reduction across multiple ramp configurations.

ABSTRACT. Radiation-hardened flip-flops (FFs) in automotive and aerospace silicon leave their single-event-upset (SEU) tolerance margin unobservable after fabrication: beam irradiation is costly, value-flipping bypasses the hardened storage nodes, and prior self-testable FFs target defects or single-event transients rather than SEU margin. his paper presents the first scan-based BIST that verifies SEU-tolerance by on-die charge injection on a radiation-hardened FF’s internal storage nodes. Instantiated on DN-FF in ASAP7 7 nm FinFET, the STDN-FF_X1/X2/X4 family covers 20, 32, and 60 MeV·cm²/mg linear-energy-transfer (LET) test levels and completes an 8615-FF self-test in 10.2 µs at a 1 GHz scan clock.

ABSTRACT. Accurate defect modeling is critical for defect-oriented test generation, especially for hard-to-detect defects influenced by input history and local electrical conditions. PEPR is a pseudo-exhaustive, physically aware region-based framework for targeting localized defects. However, its conventional formulation is limited in modeling defects governed by temporal dependence and intra-cell electrical variation. This work extends PEPR with a two-cycle formulation for sequence-dependent faults and a fine-grain refinement for electrically distinct but logically equivalent conditions. In this paper, these extensions improve defect modeling fidelity and test effectiveness.

ABSTRACT. Automatic test equipment (ATE) for CMOS image sensors (CIS) requires mission-mode testing during fabrication to detect pixel defects. Conventional ASIC-based capture boards limit upgrade flexibility and increase cost. This paper presents an FPGA-upgradable ATE architecture using only off-the-shelf components and oversampling-based soft logic to support MIPI C-/D-PHY interfaces, including newly introduced features for improved transport efficiency and simplified interface implementation. Implemented on a Stratix 10 GX FPGA, the proposed system supports up to 4.5-Gbps D-PHY and 3.5-Gsps C-PHY. The architecture was integrated into a CIS ATE platform, where wafer sorting and defect screening were demonstrated on multiple CIS devices.

ABSTRACT. Achieving high-quality test targets in advanced nodes is increasingly difficult as conventional test point insertion (TPI) saturates. This work evaluates hybrid TPI techniques and an enhanced test point (TP) structure developed with Synopsys to improve testability. We incorporate TSO.ai to optimize pattern count while preserving test coverage. By analyzing the root cause of unresolved coverage loss after automated TPI, we identify a structural testability barrier and propose novel scan-based architectures to address it. Validated on five 5nm industrial blocks, our methods achieve 99.5% stuck-at (SA) and 95.0% transition delay (TD) coverage, remaining compatible with standard design for testability (DFT) flows.

ABSTRACT. The intricate layouts of standard cells in advanced process nodes, particularly with the N5 node's Continuous Diffusion (CNOD) abutment rules, introduce unique defect susceptibility. These CNOD-related boundary defects can manifest as increased leak- age or functional failures, posing a significant challenge for yield learning and defect isolation. To address this, we present a novel methodology for the testing and diagnosis of such defects. Our ap- proach models bridge faults between adjacent cells as independ- ent, cell-level leakage faults, thereby ensuring design and chip in- dependence. We then extend cell-aware Automatic Test Pattern Generation (ATPG) to specifically generate patterns and diagnose these CNOD leakage defects. This method has been successfully validated on multiple test chips and adopted by customers.

ABSTRACT. This paper proposes a failure analysis that improves productivity by integrating the repair algorithm (RA) in electrical die sorting (EDS) with multi-bit on-die error correction code (ECC) of high bandwidth memory (HBM) using cell-failure data. Leveraging the shared error correction goals of RA and ECC, we demonstrate analytical reliability by simulating RA and 16-bit burst error correction of ECC, and conducting a stepwise analysis—from the EDS repair unit to the DRAM single-bit level. Validated on HBM, it provides a scalable solution for the rising test cost of high-density HBM and DRAM products

ABSTRACT. This paper proposes an IEEE 1838‑compliant all‑digital on‑chip diagnosis technique for 3D IC interconnects. The method employs a newly designed Die Wrapper Register to enable two diagnosis modes: Small Delay Defect (SDD) diagnosis using stochastic delay measurement, and Short/Coupling Defect (SCD) diagnosis using an additional PLL clock. The on‑chip, fully digital architecture provides high reliability, fine resolution, and intuitive control through simple scan‑in data. Experimental results demonstrate 12.6-ps resolution for SDD detection and correct operation of SCD diagnosis, confirming the method’s suitability for in‑field testing of advanced 3D IC interconnects.

ABSTRACT. Deep neural networks are increasingly deployed in safety-critical and edge systems, where hardware faults such as radiation-induced bit flips or unstable operating conditions may corrupt weights and degrade model reliability. We propose RED-SAM, a fault-aware training framework that improves robustness against such faults. RED-SAM combines Sharpness-Aware Minimization (SAM) with a constraint-aware training strategy that limits parameter sensitivity, guiding model toward flatter and stable minima. To further enhance reliability, the framework can be augmented with our approximate error-correction scheme that estimates corrupted parameters rather than restoring them, providing a lightweight approach to improve DNN robustness against hardware-induced bit-flip faults.

ABSTRACT. Silicon lifecycle management (SLM) relies on runtime telemetry for post-deployment monitoring, but existing analytics often depend on off-chip processing or offline-trained models, which are costly under on-chip constraints. This paper presents LOCUS, an HDC-based framework for on-chip unsupervised anomaly detection and diagnosis. LOCUS encodes telemetry into hypervectors, constructs a trace-specific local normal reference, and detects deviations without offline training. Detected anomalies are represented as prototypes for similarity-based diagnosis and novelty detection. On Exathlon FScustom, LOCUS achieves 0.875/0.982 AUPRC/AUROC and the best AD1–AD4 F1, with <0.1% degradation under noise and bit faults, using only a 30 KiB bitwise datapath.

ABSTRACT. The realization of Fault-Tolerant Quantum Computing (FTQC) makes highly efficient fault simulation imperative for evaluating robust Quantum Error Correction (QEC) strategies. However, large-scale fault injection inevitably exposes critical computational and memory bottlenecks. To address this, we propose Decision Diagram (DD)-based simulators tailored to various error models: temporal state caching for isolated single-gate faults, structural batching via Segment Trees and Cost-Aware Water-filling Segment Trees for spatially correlated single-qubit faults, and MST-based batch simulation scheduling for dense burst faults. These methods eliminate redundant matrix multiplications, providing an efficient approach for massive fault simulation.

ABSTRACT. As semiconductor designs become increasingly complex and technology nodes continue to shrink, layout-induced yield risks are becoming more prominent. The design layouts are subject to frequent revisions during both the development and mass production phases, thereby requiring efficient identification and assessment of changes that could potentially affect yield. This paper introduces an image-based methodology for detecting layout changes using a Siamese Neural Network. The proposed approach includes layout-to-image conversion, layer-wise preprocessing and normalization, and integration of domain-specific design knowledge to enhance analysis efficiency. Experimental results demonstrate that the technique can pinpoint sub‑nanometer variations in metal layers at a speed more than 18 times that of traditional electronic design automation (EDA) tools. In addition to the dramatically reduced analysis time, it rapidly narrows the list of failure‑analysis candidates and speeds up the identification of the underlying failure mechanisms. By combining explainable‑AI methods with layout‑domain expertise, the approach evaluates the yield impact of layout changes without requiring deep design knowledge or reliance on commercial EDA software.