Speakers: Li-C. Wang (UC Santa Barbara), Seoyeon Kim (UC Santa Barbara)

Abstract: Large language models (LLMs) and agentic AI systems are rapidly transforming how engineers interact with software, information, and complex workflows. These technologies are beginning to reshape many aspects of semiconductor engineering. This tutorial introduces the foundations of modern LLM technologies and explains how they evolve into goal-oriented AI agents capable of reasoning, tool usage, memory management, and multi-step task execution. The tutorial is designed for semiconductor engineering professionals who want to develop a deeper understanding of why modern LLMs have become so powerful, how agentic AI systems work, and how practical AI agents can now be rapidly prototyped using modern LLM tools and effective context engineering.

Topics covered include:

• Foundations of generative AI and large language models
• Principles behind modern LLM development, including scaling laws, pretraining, supervised fine-tuning (SFT), RLHF, and emergent reasoning capabilities
• In-context learning and context engineering
• Chain-of-thought reasoning and ReAct-style agents
• Tool calling, retrieval-augmented generation (RAG), and memory
• Principles behind modern agentic AI systems

The tutorial emphasizes intuition, engineering perspectives, and practical understanding rather than low-level mathematical derivations. A brief hands-on demonstration is also included to show how modern coding agents and LLM-assisted development tools can now enable rapid prototyping of end-to-end AI agents within only a few hours through effective prompting and context engineering.

Speakers' bios:

Li-C. Wang is a professor at ECE department at University of CA, Santa Barbara. He received PhD in 1996 from University of Texas, Austin, and was previously with Motorola PowerPC Design Center. Starting from 2003, his research has focused on investigating how machine learning could be utilized in design and test flows, where he had published more than 120 papers and supervised 23 PhD theses on topics in this area. Prior to that, his research spanned across multiple topics in EDA and test, including microprocessor test and verification, statistical timing analysis, defect-oriented testing, and SAT solvers. He received 12 Best Paper Awards and 2 Honorable Mentioned Paper Awards from major conferences, including recent best paper awards from ITC. He is the recipient of the 2010 Technical Excellence Award from Semiconductor Research Corporation (SRC) for his research contributions in data mining for test and validation. He is the recipient of the 2017 IEEE-TTTC Bob Madge Innovation Award. He is an IEEE fellow and serve as the General Chair of the International Test Conference (ITC) in 2017, 2018, and 2023.

Speakers: Sandeep Goel (TSMC), Yervant Zorian (Synopsys)

Abstract: Advancements in process technology have enabled the creation of chips with billions of transistors, significantly enhancing power and performance for high-performance computing (HPC) and AI applications. This complexity has spurred the development of various 3D integration and packaging techniques utilizing multi-die/chiplet-based designs. Advanced 3D integration technologies allow for the construction of multi-die systems, each offering specific advantages and trade-offs in terms of performance, application, and cost. Similar to traditional chips, all 3DICs must be rigorously tested for manufacturing defects. This includes Known-Good Die (KGD) testing before stacking, Known-Good-Stack (KGS) testing after stacking, final tests, and system-level tests. Furthermore, given the complexity of the stacking process, in-silicon monitoring solutions are necessary to continuously check silicon health during in-field operation. This tutorial offers an overview of the advanced packaging technologies and explores the associated test flow challenges. An example of how the 3Dblox open standard simplifies the description of a 3D stack, enabling interoperability between EDA tools and allowing various test optimizations, is presented. Additionally, it covers various Design-for-Test (DFT) schemes, sensors/monitors and embedded test & repair solutions to facilitate efficient testing across different packaging configurations.

Speakers' bios:

Dr. Sandeep K Goel is an academician and senior director at Taiwan Semiconductor Manufacturing Company (TSMC), USA. He previously held research and management roles at LSI, Magma Design Automation, and Philips Research. Dr. Goel earned his M.Tech. in VLSI from IIT Delhi in 1999 and his Ph.D. in Electrical and Computer Engineering from the University of Twente in 2005. He has co-authored multiple book chapters, published over 90 conference/journal papers, and holds more than 100 US patents. He received the Most Significant Paper Award at ITC in 2010 and the Distinguished Contributor Award from the IEEE Computer Society in 2022. He is the chair of IEEE Std. P3537 standard for 3Dblox: Chiplet connectivity and physical properties description language. His research focuses on design verification, testing, diagnosis, and defect modeling of 2D/3D SOCs.

Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff at AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, and Editor-in-Chief Emeritus of IEEE Design and Test of Computers. Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous awards; he is a Fellow of IEEE.

Speaker: Adit Singh (Auburn University)

Abstract: This tutorial aims at understanding the effectiveness of functional system level tests (SLTs) as an additional final defect screen before processor SOCs are shipped for assembly. It takes an in-depth look at traditional scan based Stuck-at and TDF tests to understand potential sources of test escapes, and discusses new test generation methodologies such as Cell Aware, Gate Exhaustive, Transistor Stuck-Open, and Timing Aware tests. The tutorial identifies failures that can remain undetected by scan structural tests and require the use of functional SLTs, and suggests strategies to minimize SLTs without impacting defect levels.

Speakers' bios:

Dr. Adit D. Singh is Godbold Endowed Chair Professor of Electrical and Computer Engineering at Auburn University. Before joining Auburn in 1991, he served on the faculty at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. He has held several visiting positions during sabbaticals, including at the University of Tokyo in Japan, the Universities of Freiburg and Potsdam in Germany, the Indian Institutes of Technology, and as Fulbright Awardee at the University Polytechnic of Catalonia in Barcelona, Spain. He has also conducted over 70 tutorials and short courses at conferences, universities and industry worldwide. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He has published over two hundred and fifty research papers and holds international patents that have been licensed to industry. He is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing. He has served as a consultant to many major semiconductor, test and EDA companies around the world. Professor Singh was elected Fellow of IEEE in 2002.

Speakers: Rubin Parekhji, Mudasir Kawoosa (Texas Instruments India)

Abstract: Many semiconductor chip families are characterized by very high volumes and extremely low cost, while being unrelenting on quality in the end application system. There is little headroom in chip area and test cost, which often precludes the direct adoption of well-established DFT and test methods. This tutorial provides an industry perspective on (i) design affordability and test economics, (ii) illustrations of custom methods for DFT and test required to meet challenges due to technology, architecture and end application, and (iii) current gaps in standard methods and how to fix them through customizations and emerging landscapes in EDA and agentic AI.

Speakers' bios:

Rubin Parekhji has been with Texas Instruments (India), Bangalore, since 1996, where he has mentored and led DFT teams on various design and test technology projects across multiple groups, resulting in many DFT and test innovations, and adoption of new test technologies across TI WW. He is a distinguished member of the technical staff. He has published regularly and delivered tutorials at leading conferences, has mentored and partnered on several university projects, has been a visiting faculty member for multiple academic terms, has several issued patents on ideas co-authored with team members, and has been on the editorial board of journals. He has a Ph.D. from Indian Institute of Technology, Bombay, India.

Mudasir Kawoosa is a DFT Architect at Texas Instruments (India) Pvt. Ltd. in Bangalore, with fifteen years of industry experience. As a Senior Member of Technical Staff, he leads the centralized DFT team in Connectivity Business Unit driving transformative changes through innovative test solutions, expert silicon bring-up and widely adopted methodologies. Mudasir has architected DFT and test solutions for over fifteen complex System-on-Chip (SoC) programs. He holds master’s degree in electrical engineering from the Indian Institute of Technology, Madras, has published in several peer reviewed external conferences (and is also prolific in TI internal and other conferences), and holds eleven granted US patents. Through his work, he has established several innovative solutions in DFT, test and silicon debug, for a wide variety of chip architectures across several business units in TI, and continues to influence the EDA DFT roadmap.

Speakers: Debendra Das Sharma (Intel), Yervant Zorian (Synopsys)

Abstract: High-performance and power efficiency needs of emerging workloads demand on-package integration of heterogeneous processing units, memory, and electrical and optical interconnects. Applications such as artificial intelligence/machine learning, data analytics, 5G, automotive, and high-performance computing are driving these demands to meet the needs of cloud computing, intelligent edge, enterprise, client, and hand-held computing infrastructure. On-package interconnects are a critical component to deliver the power-efficient performance with the right feature set in this evolving landscape. UCIe is an open industry standard with a fully specified stack that comprehends plug-and-play interoperability of chiplets on a package; like the seamless interoperability on board with well-established and successful off-package interconnect standards such PCI Express®, Universal Serial Bus (USB)®, and Compute Express Link (CXL)®. Recently, UCIe added significant enhancements for the test and debug infrastructure to work seamlessly across the silicon life cycle. In this tutorial, we will discuss the usages and key metrics of UCIe, both planar as well as 3D. We will delve into electrical, packaging, protocol, RAS, debug, testability, manageability, and software aspects along with the compliance and interoperability mechanisms. This will address inter die and intra die requirements. The intended audience of this tutorial are architects, SoC developers, chip designers, DFT & test engineers, researchers, and system integrators.

Speakers' bios:

Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff at AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, and Editor-in-Chief Emeritus of IEEE Design and Test of Computers. Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous awards; he is a Fellow of IEEE.

Speaker: Said Hamdioui (TU Delft)

Abstract: This tutorial discusses the Device-Aware Test (DAT) approach designed to close the gap between legacy fault models and real-world defects, demonstrated on emerging industrial memory designs. DAT incorporates the impact of physical defects into technology parameters and electrical models, performs systematic fault analysis, derives appropriate fault models, and develops test solutions. Demonstrations include STT-MRAM, RRAM, FeFET, and logic chips, showing DAT sensitizes realistic and unique defects not caught by traditional approaches.

Speakers' bios:

Said Hamdioui is Chair Professor on Dependable and Emerging Computer Technologies and Head of the Quantum and Computer Engineering department at Delft University of Technology. He is a Fellow of the Netherlands Academy of Engineering and recipient of the European Innovation Council (EIC) grant in 2025. Hamdioui received the MSEE and PhD degrees with honors from TU Delft, has authored over 350 publications, holds multiple patents, and has received numerous awards for research and technology transfer. He serves on editorial boards and has extensive industry collaborations.

Speakers: Amit Pandey (Amazon), Karthik Natarjan (Synopsys), Sankaran Menon (Ericsson)

Abstract: Infield Test and Debug provides deeper insights into the system behavior and structural quality while the system is running in mission-mode. It provides a non-intrusive method for testing and debug of complex computer systems. This is specifically useful in mission-critical applications such as space applications, ADAS (Advanced Driver Assistance Systems), for various industrial/robotic applications as well as virtually all real-time and datacenter/AI applications. In this tutorial we will establish the motivation for Infield system Test & Debug such as inadequacies of structural testing, and we will cover the various testing and debug techniques that are available today. We will then introduce the Infield system testing and debug mechanisms available for the closed-chassis systems using USB Type-C, PCIe and any other high-speed interfaces. We will cover the efficient design planning mechanism that would consume as much of the available bandwidth for designs using high-speed interfaces. We will conclude with results from an Infield system test and Debug used in real-world applications across the various industries.

Speaker: Li-C. Wang (UC Santa Barbara)

Abstract: Large language models (LLMs) are fundamentally changing how semiconductor test data analytics systems can be designed and deployed. Modern LLMs can generate code, analyze CSV tables, create plots, summarize engineering data, and perform multi-step reasoning. However, reliable semiconductor analytics requires far more than simply connecting an LLM to raw test data.

This tutorial presents a new paradigm for agentic semiconductor test-data analytics based on workflow grounding, context engineering, and analytic-ready tables (ARTs). The tutorial introduces the evolution of the Intelligent Engineering Assistant (IEA) platform toward IEA-Notebook and IEA-Sentia, a scalable agentic analytics architecture that combines workflow knowledge with LLM-based reasoning.

The tutorial discusses how modern AI agents interact with engineering environments through iterative reasoning loops involving table retrieval, code generation, tool usage, plot interpretation, contextual memory, and workflow-guided execution. A central theme of the tutorial is that the primary engineering challenge in the LLM era is no longer merely implementing analytic algorithms, but constructing grounded analytic environments that enable reliable AI reasoning over semiconductor engineering data.

Real industrial examples and deployment experiences will be discussed throughout the tutorial. The tutorial will also include demonstrations showing how modern LLM systems can now generate substantial portions of analytics workflows and software components directly from high-level engineering specifications.

The tutorial is intended for semiconductor test, product, and data engineers who want to understand how modern LLM and agentic AI technologies are reshaping the future of engineering analytics systems and semiconductor data analysis workflows.

Speakers' bios:

Li-C. Wang is a professor at ECE department at University of CA, Santa Barbara. He received PhD in 1996 from University of Texas, Austin, and was previously with Motorola PowerPC Design Center. Starting from 2003, his research has focused on investigating how machine learning could be utilized in design and test flows, where he had published more than 120 papers and supervised 23 PhD theses on topics in this area. Prior to that, his research spanned across multiple topics in EDA and test, including microprocessor test and verification, statistical timing analysis, defect-oriented testing, and SAT solvers. He received 12 Best Paper Awards and 2 Honorable Mentioned Paper Awards from major conferences, including recent best paper awards from ITC. He is the recipient of the 2010 Technical Excellence Award from Semiconductor Research Corporation (SRC) for his research contributions in data mining for test and validation. He is the recipient of the 2017 IEEE-TTTC Bob Madge Innovation Award. He is an IEEE fellow and serve as the General Chair of the International Test Conference (ITC) in 2017, 2018, and 2023.