Meeting Summary & Overview

This full-day meeting focuses on key industry test challenges, data analytics, heterogeneous integration, defect coverage, and silent data corruption in the age of AI. Attendees will hear presentations from leading industry experts and engage in collaborative panel discussions throughout the day.

Topics Covered

· Data Analytics & Adaptive Test: Shifting from traditional workflows to AI-driven systems, product chip health monitoring, and test floor analytics.

· Heterogeneous Integration & AI Processors: Testing challenges across wafer to in-field, unique DFT requirements, and HBM testing.

· Defects & Reliability: Process corners, defect coverage reporting, marginal failures, and Silent Data Corruption (SDC).

· Data Center Debug & TCO: System-level challenges, cost vs. quality balances, and actionable error-data insights.

Registration & Attendance Restrictions

· Attendees must register via the official ITC website (www.itctestweek.org) for room capacity and lunch arrangements.

· Photo and audio/video recordings are strictly prohibited during the sessions.

· Presenters are not required to distribute their presentation materials.

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Test Challenges and Direction in the Age of AI Everywhere

Speaker: Harry Chen and Anti Tseng

Company: Mediatek

This talk explores critical defect escapes in data centers and outlines an industry call to action. It examines how marginal defects drive in-field failures and highlights the vital role of System-Level Testing (SLT) alongside standard ATE and ATPG methodologies, using practical examples of shifting to adaptive AI-driven test workflows.

Monitoring in-Field Product Chip Health with In-die Quality Monitors

Speaker: Andrzej Strojwas

Company: PDF Solutions Inc

This session covers monitoring product chip degradation and aging across the entire lifecycle, with key applications in automotive and data center products. It introduces the PDF CV Core—a complex IP block embedded into product chip designs featuring multiple sensors, such as mechanical stress, process/device centering, and device reliability sensors—and discusses its implementation in commercial products like ADAS.

Don't Let AI Do All the Thinking on Your Test Floor

Speaker: John O'Donnell

Company: yieldHUB

Panel: "Test Analytics: Why Is Industry Adoption Still Lagging When Product Complexity, Quality Requirements, and Field Reliability Risks Are Increasing So Rapidly?"

Moderator Ira Leventhal who is the lead of the HIR (Roadmap) chapter on Data Analytics & Adaptive Test.

· How heterogeneous integration, chiplets, advanced packaging, and AI accelerators are fundamentally changing analytics requirements.

· Silent Data Corruption and other field reliability challenges, and the need to correlate field failures back to manufacturing and test data.

· Why data silos, traceability gaps, incompatible data formats, security concerns, and organizational barriers continue to limit adoption.

· What types of data should realistically be shared across the semiconductor value chain, and what collaboration models are needed among foundries, OSATs, device companies, and hyperscalers.

· AI hype versus practical production deployments. Where is AI delivering measurable results today, and what foundational infrastructure is still missing?

· Whether the biggest challenge is analytics itself, or the underlying infrastructure required for data collection, alignment, traceability, and secure sharing.

The Role of Agentic AI in Test Program Development

Speaker: Brian Buras

Company: Advantest

AI Processors -- Emerging changes to Test/DFT/In-field testing through Heterogeneous Integration

Speaker: Saket Goyal

Company: Broadcom

This session covers emerging changes to test and DFT methodologies driven by heterogeneous integration in 2.5D and 3D XPU architectures. Key focus areas include unique chip-to-chiplet DFT requirements, evolving test flow methods, and HBM testing requirements, alongside in-field test strategies and test optimization across all manufacturing steps.

Defect coverage will be different for ‘typical’ and each process corner – how should it be reported in a way that will correlate with DPPM?

Speaker: Stephen Sunter

Company: Siemens EDA

Published papers have invariably reported defect coverage of analog/mixed-signal tests and circuits for only ‘typical’ process, mostly because simulation times have been too long to allow exploring process corners. As digital circuits exhibit more sensitivity to process, and analog circuits are also tested structurally, it might be essential to measure defect coverage at the corners in addition to typical process, as the newly published IEEE 2427 standard recommends. This presentation will compare the possibilities: union coverage (recommended by 2427), intersection coverage (suggested by analog scan paper), coverage per corner (required by 2427), and process-weighted coverage.

Data Center: Debug & Cost Challenges

Speaker: Darshan Kobla

Company: Microsoft

Advanced packaging and chiplet-based architectures are becoming foundational to high-performance computing. This shift increases the complexity and cost of testing, debugging, and failure analysis in data centers. This presentation explores these challenges in today’s data center systems. It also examines total cost of ownership (TCO) and the balance between cost and quality. Finally, it calls for industry-wide collaboration on error-data collection, analysis, and actionable insights.

Presentation related to SDC, Marginal Failures, Reliability Direction

Speaker: David Lerner

Company: Intel

Open Panel covering topics such as

· Root Causes of Silent Data Corruption: New empirical findings, field data correlation, and mitigation strategies.

· Fault Models for Sub-2nm Nodes: Evaluating Cell-Aware ATPG vs. novel physical defect modeling approaches.

· Functional vs. Structural Testing: Accelerated stress testing, new burn-in paradigms, and defect detection efficiency.

· Test Time & Cost Reduction: Strategies for handling exploding test times in complex AI architectures.

· System-Level Testing (SLT) Integration: Determining necessity, positioning after ATE/ATPG, and coverage trade-offs.

Speaker: Adit Singh (Auburn University)

Speakers' bios:

Dr. Adit D. Singh is Godbold Endowed Chair Professor of Electrical and Computer Engineering at Auburn University. Before joining Auburn in 1991, he served on the faculty at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. He has held several visiting positions during sabbaticals, including at the University of Tokyo in Japan, the Universities of Freiburg and Potsdam in Germany, the Indian Institutes of Technology, and as Fulbright Awardee at the University Polytechnic of Catalonia in Barcelona, Spain. He has also conducted over 70 tutorials and short courses at conferences, universities and industry worldwide. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He has published over two hundred and fifty research papers and holds international patents that have been licensed to industry. He is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing. He has served as a consultant to many major semiconductor, test and EDA companies around the world. Professor Singh was elected Fellow of IEEE in 2002.

Abstract:

This tutorial is designed for professionals without a formal background in integrated circuit (IC) testing and those interested in reviewing the core ideas. The session covers fundamental test concepts in detail, including defect statistics, fault models, test generation, scan design-for-test (DFT), and built-in self-test (BIST). Additionally, the tutorial provides an overview of technological advances, such as test compression, adaptive testing, and cell-aware and timing-aware fault models. Throughout the presentation, real-world production test data is used to evaluate the practical effectiveness of these various test methods.

Speakers: Lee Harrison (Siemens EDA), Peter Orlando (Siemens EDA)

Abstract: In this tutorial, we will give an overview of how the use and development of AI is driving the evolution of advanced AI hardware. It will cover the critical and special characteristics and the architecture of the popular AI chips. Next we will summarize the features of the AI chips from design-for-test (DFT) perspective and introduce the DFT technologies that can help testing AI chips. We will also cover how additional monitoring techniques that are available today are addressing the requirements of the AI hardware, developing reliability and resilience. Finally, we will present a few case studies on how DFT is implemented in real AI chips.

Speakers' bios:

Lee Harrison is Automotive IC Test Solutions Manager with Siemens EDA. He has over 20 years of industry experience with Mentor DFT products and has been involved in specifying new test features and methodologies, focusing on Automotive requirements. Lee received his BEng in MicroElectronic Engineering from Brunel University London in 1996 and regularly presents at conferences such as DAC, ITC, VTS, ETS, and DATE.

Peter Orlando is a Technical Marketing Engineer at Siemens EDA.

Speaker: Gang Qu (University of Maryland, College Park)

Abstract: Faults are inevitable in integrated circuit (IC) fabrication due to many factors such as manufacturing process variability. By adding testability features at design time, scan-based design makes test pattern generation, application and evaluation cost-effective to screen out defective ICs. It has become a common design structure for modern chips. However, the unrestrictive and ease of access to the internal states of the circuit under test makes scan chains an exploitable side channel for attacker to steal sensitive information such as cipher key of cryptographic core through in-field testing. In this tutorial, after a brief introduction of scan-based DfT, we will focus on its security vulnerabilities, the attacks based on these vulnerabilities, and corresponding countermeasures. We will also discuss DfT-based solutions to some of the hardware security problems, including digital watermarking, fingerprinting, IC metering, physical unclonable function, and random number generation.

Speakers' bios:

Gang Qu is a professor in the Electrical and Computer Engineering department at the University of Maryland at College Park. He leads the Maryland Embedded Systems and Hardware Security lab and the Wireless Sensor Laboratory. Dr. Qu has made significant contributions to hardware security and trust, co-founded multiple workshops and symposiums in the field, developed a popular hardware security MOOC on Coursera, and is a Fellow of IEEE.

Speakers: Sai Varun Puligilla, Stephen Sunter, Jason Doege, Jonathan Gaudet, Martin Keim (Siemens EDA)

Abstract: This tutorial provides a comprehensive introduction to IEEE 1687 (IJTAG), a standard designed for scalable access to embedded instruments within complex SoCs. It explains how 1687 builds on IEEE 1149.1 boundary scan. In addition, it outlines the emerging extensions P1687 (1687 refresh), P1687.1 and P1687.2. Key concepts such as instrument networks, ICL, and the procedural description framework are highlighted. The tutorial includes the different types of PDL used to describe instrument procedures and test sequences. It emphasizes how IJTAG improves flexibility, reuse, and interoperability across modern test and debug infrastructures.

Speakers' bios:

Sai Varun Puligilla is a Technology Enablement Engineer at Siemens EDA, specializing in DFT methodologies, multi-die architectures, and advanced test automation for modern semiconductor designs. Since joining Siemens in 2023, he has developed high-impact test flows, validated tool interoperability, authored application notes, and supported customers through technical guidance, demos, and training content. He holds an M.S. in Electrical and Computer Engineering from California State University, Fresno.

Steve Sunter graduated from the University of Waterloo in 1978 with a Bachelor of Applied Science in Electrical Engineering. He worked in mixed-signal IC design from 1977 to 1990 at Bell-Northern Research and Nortel. In 1996, he became Engineering Director of mixed-signal DfT at LogicVision, later part of Mentor Graphics and Siemens. Over his career he was granted 30 U.S. patents, authored many papers and book chapters, chaired IEEE working groups and served on multiple program committees. He is a Life Senior Member of IEEE and an Associate Editor of JETTA.

Jason Doege graduated from DeVry Institute of Technology in 1992 with a Bachelor of Science in Electronics Engineering Technology. He is a Product Manager at Siemens EDA, responsible for SiliconInsight products, with 30+ years in Design For Test and Debug. He was a core contributor to IEEE P1500 and P1687 and currently holds roles in multiple IEEE working groups.

Jonathan Gaudet is a Senior Engineering Manager at Siemens EDA, leading the Tessent IJTAG development team. He has contributed to IJTAG and multi-die products since 2008 and is co-inventor of High-Bandwidth IJTAG. He has authored several ITC publications and leads development for Tessent IJTAG.

Dr. Martin Keim joined Mentor Graphics' Silicon Test Solutions group in 2001 and is currently a senior technical marketing engineer. He previously worked as a Test Engineer at Infineon and is active in IEEE P1687 working group and test/failure analysis communities.