Speaker: Adit Singh (Auburn University)

Abstract: TBD

Speakers' bios:

Dr. Adit D. Singh is Godbold Endowed Chair Professor of Electrical and Computer Engineering at Auburn University. Before joining Auburn in 1991, he served on the faculty at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. He has held several visiting positions during sabbaticals, including at the University of Tokyo in Japan, the Universities of Freiburg and Potsdam in Germany, the Indian Institutes of Technology, and as Fulbright Awardee at the University Polytechnic of Catalonia in Barcelona, Spain. He has also conducted over 70 tutorials and short courses at conferences, universities and industry worldwide. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He has published over two hundred and fifty research papers and holds international patents that have been licensed to industry. He is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing. He has served as a consultant to many major semiconductor, test and EDA companies around the world. Professor Singh was elected Fellow of IEEE in 2002.

Speakers: Lee Harrison (Siemens EDA), Peter Orlando (Siemens EDA)

Abstract: In this tutorial, we will give an overview of how the use and development of AI is driving the evolution of advanced AI hardware. It will cover the critical and special characteristics and the architecture of the popular AI chips. Next we will summarize the features of the AI chips from design-for-test (DFT) perspective and introduce the DFT technologies that can help testing AI chips. We will also cover how additional monitoring techniques that are available today are addressing the requirements of the AI hardware, developing reliability and resilience. Finally, we will present a few case studies on how DFT is implemented in real AI chips.

Speakers' bios:

Lee Harrison is Automotive IC Test Solutions Manager with Siemens EDA. He has over 20 years of industry experience with Mentor DFT products and has been involved in specifying new test features and methodologies, focusing on Automotive requirements. Lee received his BEng in MicroElectronic Engineering from Brunel University London in 1996 and regularly presents at conferences such as DAC, ITC, VTS, ETS, and DATE.

Peter Orlando is a Technical Marketing Engineer at Siemens EDA.

Speaker: Gang Qu (University of Maryland, College Park)

Abstract: Faults are inevitable in integrated circuit (IC) fabrication due to many factors such as manufacturing process variability. By adding testability features at design time, scan-based design makes test pattern generation, application and evaluation cost-effective to screen out defective ICs. It has become a common design structure for modern chips. However, the unrestrictive and ease of access to the internal states of the circuit under test makes scan chains an exploitable side channel for attacker to steal sensitive information such as cipher key of cryptographic core through in-field testing. In this tutorial, after a brief introduction of scan-based DfT, we will focus on its security vulnerabilities, the attacks based on these vulnerabilities, and corresponding countermeasures. We will also discuss DfT-based solutions to some of the hardware security problems, including digital watermarking, fingerprinting, IC metering, physical unclonable function, and random number generation.

Speakers' bios:

Gang Qu is a professor in the Electrical and Computer Engineering department at the University of Maryland at College Park. He leads the Maryland Embedded Systems and Hardware Security lab and the Wireless Sensor Laboratory. Dr. Qu has made significant contributions to hardware security and trust, co-founded multiple workshops and symposiums in the field, developed a popular hardware security MOOC on Coursera, and is a Fellow of IEEE.

Speakers: Sai Varun Puligilla, Stephen Sunter, Jason Doege, Jonathan Gaudet, Martin Keim (Siemens EDA)

Abstract: This tutorial provides a comprehensive introduction to IEEE 1687 (IJTAG), a standard designed for scalable access to embedded instruments within complex SoCs. It explains how 1687 builds on IEEE 1149.1 boundary scan. In addition, it outlines the emerging extensions P1687 (1687 refresh), P1687.1 and P1687.2. Key concepts such as instrument networks, ICL, and the procedural description framework are highlighted. The tutorial includes the different types of PDL used to describe instrument procedures and test sequences. It emphasizes how IJTAG improves flexibility, reuse, and interoperability across modern test and debug infrastructures.

Speakers' bios:

Sai Varun Puligilla is a Technology Enablement Engineer at Siemens EDA, specializing in DFT methodologies, multi-die architectures, and advanced test automation for modern semiconductor designs. Since joining Siemens in 2023, he has developed high-impact test flows, validated tool interoperability, authored application notes, and supported customers through technical guidance, demos, and training content. He holds an M.S. in Electrical and Computer Engineering from California State University, Fresno.

Steve Sunter graduated from the University of Waterloo in 1978 with a Bachelor of Applied Science in Electrical Engineering. He worked in mixed-signal IC design from 1977 to 1990 at Bell-Northern Research and Nortel. In 1996, he became Engineering Director of mixed-signal DfT at LogicVision, later part of Mentor Graphics and Siemens. Over his career he was granted 30 U.S. patents, authored many papers and book chapters, chaired IEEE working groups and served on multiple program committees. He is a Life Senior Member of IEEE and an Associate Editor of JETTA.

Jason Doege graduated from DeVry Institute of Technology in 1992 with a Bachelor of Science in Electronics Engineering Technology. He is a Product Manager at Siemens EDA, responsible for SiliconInsight products, with 30+ years in Design For Test and Debug. He was a core contributor to IEEE P1500 and P1687 and currently holds roles in multiple IEEE working groups.

Jonathan Gaudet is a Senior Engineering Manager at Siemens EDA, leading the Tessent IJTAG development team. He has contributed to IJTAG and multi-die products since 2008 and is co-inventor of High-Bandwidth IJTAG. He has authored several ITC publications and leads development for Tessent IJTAG.

Dr. Martin Keim joined Mentor Graphics' Silicon Test Solutions group in 2001 and is currently a senior technical marketing engineer. He previously worked as a Test Engineer at Infineon and is active in IEEE P1687 working group and test/failure analysis communities.