Program for Tuesday, October 13th: Talk View

PROGRAM FOR TUESDAY, OCTOBER 13TH: TALK VIEW

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View: with abstracts session overview

9:00

9:30

10:00

10:30

11:00

11:30

12:00

12:30

13:00

13:30

14:00

14:30

15:00

15:30

16:00

16:30

17:00

17:30

18:00

18:30

19:00

19:30

20:00

20:30

09:00-09:30 Opening Plenary & Ceremony

09:30-10:30 Keynote 1: TBD

10:30-11:30 Corporate Presentation by Diamond Supporter

13:30-14:00

CREW: Collapse-Resilient Generative Augmentation for Wafer Defect Classification

Md Fahim Ul Islam, Soyed Tuhin Ahmed, Krishnendu Chakrabarty

14:00-14:30

ORACLE : Orchestrated Reasoning Agents for Classification of Wafer-Map Defects with Fab-Aware Logic and

Md Fahim Ul Islam, John Carulli, Krishnendu Chakrabarty

14:30-15:00

Diffuse to Detect: Generative Diffusion Models for Unsupervised IC Anomaly Detection

Yuxuan Yin, Chen He, Todd Jacobs, Jialei He, Boxun Xu, Robert Jin, Peng Li

13:30-14:00

DICE: A Digital Twin-Driven In-Field Continuous-Test Engine for Silicon Lifecycle Management

Hsiao-Ping Ni, Krishnendu Chakrabarty

14:00-14:30

A Software-Based methodology for In-Field Power-on Self-Test of Safety-Critical Timer Modules

di Gruttola Giardino et.al

14:30-15:00

VITAL: Voltage-Frequency Driven Safety and Aging Analysis for Silicon Lifecycle Management

Eduardo Ortega, Arjun Hati, Jonti Talukdar, Krishnendu Chakrabarty

13:30-15:00 Special S1:

13:30-14:00

An Innovative Memory Vmax Defect Testing/Repair Methodology For 3nm HPC Products

Yihsin Kuo, Haiming Yu, Marvin Chen, Nate Keane, Abdul Rahman Syed

14:00-14:30

Improving Yield Through Advanced Detection of High-Speed Memory Access Failures

P. Kumar, A. Purushotham, R. Thekke Veetil, V. Reddy, A. Khan, P. Seetharaman

14:30-15:00

Characterizing Path Delay Failures from Random Process Variations to Improve Timing Tests

Mukarram Ali Faridi, Adit Singh

13:30-14:00

A Vernier-Based Design-for-Test Cell for Silicon Photonic Ring Resonators

Pratishtha Agnihotri, Sandeep Kumar Goel, Frank Lee, Krishnendu Chakrabarty

14:00-14:30

Structural Testing Framework for RRAM DNN Accelerators: From Circuit to System-Level

Serlis, Arapidis, Gebregiorgis, Aziza, Taouil, Hamdioui, Fieback

14:30-15:00

STAMP: Stress-Aware Machine Learning for Electromigration-Induced Aging Prediction in Fan-Out Wafer-Level

D. Thapar, R. Gandhi, P. Bhoumik, C. Bailey, K. Chakrabarty

16:00-16:15

Accelerating ISO 26262 Functional Verification with LLM-Based Critical Node Analysis for Early-Stage RTL

S. Fei, Z. Chao, Y. Sun, Y. Bian, Z. Bian, Y. Zhou, H. Li, Z. Wang

16:15-16:30

Si-ATLAS: Autonomous Testing via LLM-Agent Synergy for RISC-V SBST Generation

Wang, Chen, Bellarmino, Esteban Rodriguez Condia, Li, Squillero, Cantoro

16:30-16:45

AI-Driven Test Efficiency at Scale: Implementation case-studies on nanoscale Automotive SoCs

Boddikurapati et.al

16:45-17:00

Automated Issue Site Detection in Multi-Site Testing via Isolation forest

K.T. Tamakloe, G. Bonsu, S. Chaganti, D. Chen, A. Nesty

17:00-17:15

A Hierarchical Manufacturing Test Strategy for Custom AI Accelerators: From ATE to Network-Level

Shreyas Rao, James Le, Sameeksha Gupta

17:15-17:30

Speeding up DFT Recommendation Systems with limited-compute resources

Baleegh Ahmad, Prakyath Madadi, Zhiwei Liao, Theo Toulas, Peter Wohl

16:00-16:15

Uncertainty-guided Multi-objective Performance Tuning of Mixed-signal ASICs through Surrogate Model

Strobel, Shahpari, Rottacker, Bantel, Rösslhuber, Pflüger, Anders

16:15-16:30

EDGE: Entropy Driven Stimulus Optimization for Efficient GMM Based Diagnosis of Modular Analog/Mixed-Signal

Ankush Ankush, Abhijit Chatterjee

16:30-16:45

Fault diagnosis of analog circuits using Bayesian framework and structural BIST

Suhas Krishna Kashyap, Sule Ozev

16:45-17:00

Programmable Scan Shift Frequency Ramping in Logic BIST for Power Supply Noise Mitigation in Advanced-Node Automotive and Server

Singh, Richter, Meehl, Chakravadhanula, Niewenhuis, Varadarajan

17:00-17:15

Scan-Based Charge-Injection BIST for SEU-Tolerant Flip-Flops

Lowry P.-T. Wang, Hao-Chi Lin, Charles H.-P. Wen, Herming Chiueh

17:15-17:30

RC2C-PEPR: Resistance- and Capacitance-Aware Two-Cycle PEPR for Hard-to-Detect Defects

Xu He, Ruben Purdy, Subhasish Mitra, Shawn Blanton

16:00-17:30 Special S2: (Panel-2)

16:00-16:30

An FPGA-Upgradable ATE Architecture for CMOS Image Sensor Mission-Mode Testing with MIPI C-/D-PHY

Jun Yeon Won, Cheolmin Park, Minho Kang, Hyuntae Jeong, Jaehyun Baek

16:30-17:00

Industrial Experience for Achieving Advanced Test Coverage

J. Yang, H. Lim, J. Kim, J. Park, D. Song, S. Nanduru

17:00-17:30

Testing and Diagnosis of CNOD Defects in Advance Process Nodes: A Silicon Case Study

Sandeep Kumar Goel, Ankita Patidar, Frank Lee, Hubert Ke, Ken Wang

16:00-16:15

A Novel Approach Enables Synergy Between Repair Algorithm and Multi-Bit On-Die ECC in HBM

G. Yeon, H. Cho, J. Kim, A. Ilgyu, T. Kim, E. Jeon, H. Km, C. Park, B. Kim

16:15-16:30

An IEEE 1838-Compliant All-Digital On‑Chip Diagnosis Architecture for 3D‑IC Interconnects in Chiplet and Multi‑Die

Kentaroh Katoh, Toru Nakura, Haruo Kobayashi

16:30-16:45

RED-SAM: Reliability Enhancement of DNNs against Bit-Flip Errors via Sharpness-Aware Minimization Augmented with Approximate

Hossein Pourmehrani, Kossar Pourahmadi, Hamed Pirsiavash, Naghmeh Karimi

16:45-17:00

LOCUS: Learning On-Chip Using Hyperdimensional Computing for Silicon Lifecycle Management

Chengcheng Gao, Fei Su

17:00-17:15

Decision Diagram-based Fault Simulator for Quantum Circuits

Cheng-Yun Hsieh, Bo-Lin Huang, James Chien-Mo Li

17:15-17:30

Layout Change-Driven Failure Risk Prediction for Fast Failure Localization

Jihye Seo, Ghil-Geun Oh

12:00-13:30 Exhibit Hall Lunch (@Texas Ballroom DEF)

15:00-16:00 Session Break (Texas Ballroom DEF)

18:30-20:30 Grand Reception (Texas Ballroom Prefunction)