ABSTRACT. Large Language Models (LLMs) are transforming semiconductor test-data analytics by enabling AI agents to generate code, analyze tables, and perform complex reasoning. This paper presents IEA-Connect, a context-centric architecture that enables engineering knowledge to accumulate and propagate through everyday analytics work. The central idea is that every validated solution becomes reusable context for future solutions. Artifacts produced during analytics, including prompts, workflows, scripts, templates, and analytic-ready tables (ARTs), are automatically captured and organized as reusable knowledge assets. Engineers and AI agents can retrieve, adapt, and build upon these assets, creating a connected ecosystem in which one engineer's solution becomes another engineer's starting point. The paper introduces the principles underlying IEA-Connect, including ART-centered context representation, workflow-grounded knowledge capture, context inheritance, and orchestration mechanisms for collective engineering intelligence. By treating context as the primary unit of reuse, IEA-Connect transforms isolated analytics activities into a continuously evolving engineering knowledge network.

ABSTRACT. Advanced-node CPU manufacturing suffers a 1–3 month chip-probe (CP) to final-test (FT) latency, causing high-performance chip yield loss. We deploy an interpretable, production-scale machine learning framework that predicts FT binning directly from CP-stage parameters (>5,000 features reduced to 200 via two-stage selection) at HVM scale (10⁴–10⁶ chips/week). For binary classification, the model achieves F1 = 0.882 and AUC-PR = 0.938, a 60.8% AUC-PR gain over the industrial single-indicator baseline (0.583). Group-specific SHAP profiling identifies distinct physical drivers per market segment. Early CP-stage deployment shortens the yield feedback loop from months to days, saving ~$5M per CPU product generation.

ABSTRACT. We compare two approaches for generating additional Process Control Monitor (PCM) data: Monte Carlo simulation and synthetic data generation. PCMs are electrical test structures placed in wafer scribe lines to monitor manufacturing variation, assess wafer health, and inform specification limits. During process ramp-up, limited measurements necessitate additional data. Traditional Monte Carlo methods rely on random sampling, lacking spatial awareness and producing unrealistic outcomes. Using measurements from manufactured wafers, we show that synthetic data generation better represents real variation. μ±4σ limits derived from synthetic data contain 98.7% of real wafers versus 10.3% for Monte Carlo on a GlobalFoundries 12LP FinFET process.

ABSTRACT. Modern System-on-Chip (SoC) designs employ aggressive low-power techniques and multi-mode operation, increasing demands on Design-for-Testability (DFT) architectures to maintain coverage while improving configurability. This paper presents a dynamic scan architecture that unifies reset and clock-gate enable control within a single Embedded Deterministic Test (EDT) environment. A compact four-flop scan-programmable control segment enables ATPG to exercise multiple test scenarios without regenerating patterns or modifying scan infrastructure. Experimental results on representative SoC blocks show equal or improved stuck-at coverage and a 6–15% reduction in ATPG pattern count. The approach reduces test modes, simplifies verification, and incurs negligible timing and area overhead.

ABSTRACT. Test point insertion (TPI) improves testability, but post-synthesis TPI is constrained by standard-cell boundaries, incurring unnecessary area and timing overhead, while RTL-level TPI suffers from uneditable regions that limit precision. This work identifies the internal Boolean graph before technology mapping as a sweet spot for TPI. A novel in-synthesis TPI framework is proposed, where test point analysis and insertion are performed on the AIG, followed by technology mapping. Compared with state-of-the-art commercial tools for post-synthesis and RTL-level TPI, the proposed method improves testability with fewer test points. Additionally, better area and timing results are obtained over the post-synthesis approach.

ABSTRACT. Conventional gate-level test point insertion occurs after timing optimization, delivering testability feedback too late for effective Register Transfer Level (RTL) correction and inheriting independent assumptions that degrade accuracy on circuits. We present RISE, a simulation-driven framework operating directly on RTL, combining Shannon entropy and Rademacher-Walsh Transform (RWT) spectral analysis to identify controllability and observability before synthesis. Entropy metrics quantify information flow at each signal while spectral coefficients characterize toggling frequency guiding a combined iterative tournament loop. This is evaluated on the ITC-99 benchmarks, RISE achieves up to 2.73 percentage-point fault coverage improvement and 14–25% test vector count reduction

ABSTRACT. Automated Test Pattern Generation (ATPG) plays a crucial role in the post-silicon validation and manufacturing test flow. It has a decisive influence on the final test quality of integrated circuits. Traditional testability enhancement methods rely on localized circuit modifications that fail to systematically explore the global design space, often missing the optimal structure for conflict reduction. To address these challenges, this paper proposes E-ATPG, a novel framework that leverages E-graphs to perform testability-driven logic restructuring. Experimental results over a range of benchmarks demonstrate that E-ATPG significantly reshapes the circuit's search space to be "ATPG-friendly".

ABSTRACT. Modern IC complexity drives test pattern growth, with the majority of patterns targeting a small set of hard-to-detect (HTD) faults. This motivates new ATPG algorithms to improve test effectiveness specifically for HTD faults. This paper presents DEFT, a new ATPG approach that reformulates the discrete ATPG problem as a continuous optimization task. DEFT introduces a mathematically grounded reparameterization that aligns the expected continuous objective with discrete fault-detection semantics, enabling reliable gradient-based pattern generation. To ensure scalability and stability on deep circuit graphs, DEFT integrates a custom CUDA kernel for efficient forward-backward propagation and applies gradient normalization to mitigate vanishing gradients.

ABSTRACT. As modern multi core systems-on-chip grow in complexity, selecting optimal test compression configurations—such as chain count and PRPG size—is critical for minimizing test cost. This work presents an efficient approach that uses virtual compression–aware Automatic Test Pattern Generation emulation to rapidly estimate test cost for different compression architectures, eliminating the need for repeated physical compressor insertion during Design for Test exploration. Integrated with an AI guided distributed optimization framework, the solution automates and accelerates the selection and evaluation of candidate compressor configurations, enabling rapid identification of compression architectures that deliver optimal quality of results while significantly reducing turnaround time.

ABSTRACT. This work presents a novel hardware root of trust to counter hardware security threats and prevent leakage of secret information or other sensitive assets across the various stages of IC testing. It builds on and easily integrates with a Streaming Scan Network technology – a new packetized test data delivery system whose high-speed parallel bus is also deployed to drive the serial IJTAG network. The proposed root of trust comprises optimized security primitives. Their presence stems from an adopted challenge-response authentication protocol that enables multi-level access protection and thus fine-grained control over the accessibility of individual cores and test instruments.

ABSTRACT. Widely used side-channel attacks such as Correlation Power Analysis and Template Power Attacks often detect leakage without reliably achieving full key recovery. This paper proposes a Random Forest (RndF)-based power side-channel attack methodology for AES using three leakage models: Hamming Weight of the S-box output, S-box output value, and key value. The method is evaluated on three unprotected and five protected public AES datasets. Results show substantial trace reduction compared with state-of-the-art attacks, with near single-trace recovery in several scenarios and strong performance across multiple protected implementations. These findings provide an effective framework for evaluating security and guiding stronger countermeasures.

ABSTRACT. Heterogeneous integration (HI) enables composition of chiplets across technology nodes but introduces new security risks: even trusted dies can form insecure systems if interconnections are manipulated. Existing mechanisms verify chiplet identity but not system topology, leaving HI vulnerable to connectivity-based tampering. We present THETA, a topology-aware secure boot framework that reconstructs the runtime chiplet connectivity graph and authenticates it against a golden reference. THETA further enforces connectivity policies, including required and forbidden adjacencies and multi-hop constraints, to detect unauthorized links and bypass attacks. Evaluation shows THETA achieves this with low overhead, incurring less than 6% area and sub-33 µs latency.

ABSTRACT. Chiplet-based 2.5-D and 3-D multi-die packages increasingly feature tens of thousands of die-to-die micro-bump interconnects susceptible to hard opens, hard shorts, resistive weak opens, resistive weak shorts, and inter-bump coupling faults. Existing approaches of automatic test pattern generation rely on simplified electrical models with no hardware corroboration, employ NP-hard heuristics that become computationally infeasible at package scale, and do not address multi-defect scenarios, quantitative ground bounce bounds, or fine-pitch scaling behavior. This paper presents an electrically parameterized Graph Neural Network (GNN) framework for micro-bump interconnect test pattern generation, corresponding to a range of different topologies.

ABSTRACT. Heterogeneous integration enables chiplet-based system-on-chip (SoC) design but introduces yield challenges due to manufacturing defects and complex die-to-die (D2D) interconnect constraints. Lane-level defects, limited spares, and structural compatibility restrict feasible chiplet combinations. This paper proposes a defect- and interconnect-aware chiplet matching framework to maximize functional SoC yield. The approach models defect maps, spare budgets, and topology constraints, while leveraging chiplet rotation and interface permutation to expand matching options. A compatibility matrix is constructed, and the global assembly problem is formulated as an integer linear program. Experimental results demonstrate significant yield improvement over baseline matching strategies.

ABSTRACT. High Bandwidth Memory (HBM) is essential for 2.5D and 3D systems, providing the massive data throughput required for high performance computing and AI. HBM’s wide interfaces, stacked die structure, and extensive DFT needs significantly increase test time. Traditional IJTAG architectures rely on long scan chains and serialized instrument access, creating bottlenecks. This paper demonstrates how High Bandwidth IJTAG delivers a scalable, and parallel test access mechanism for 3D ICs with HBM. Its packet-based protocol and high throughput paths streamline scheduling across logic and memory dies, reducing test time and improving verification efficiency, as confirmed by experimental and simulation results.