Tentative Agenda

8:00-9:00am – Transforming Test for the AI Era: From Test Optimization to Assistance and Autonomy (The growing complexity of AI systems is driving new challenges in semiconductor testing, including increasing test cost, engineering productivity demands, and system reliability concerns. Traditional test methodologies are being stretched by larger designs, more complex integration technologies, and the need for reliable operation throughout the product lifecycle. This session presents a path for the evolution of semiconductor testing in the AI era. It begins with AI-enabled test optimization techniques that improve test quality, reduce runtime, and lower manufacturing cost. It then explores how AI technologies can assist engineers and automate key test development activities, paving the way toward autonomous test engineering.)

Talk 1: AI Enabled Scalable Test Solution for Test QoR Improvement and Cost Reduction; MediaTek and Synopsys
Talk 2: Industrial Experience for Achieving Advanced Test Coverage Leveraging AI; Samsung and Synopsys
Talk 3: AI Applications for Test: From Optimization to Assistance and Autonomy; Srikanth Venkat Raman, Synopsys

9:00-10:00am: Panel - Building AI-native engineering (DFT organizations are being asked to support more complex SoCs, more chips and chiplets, 3D-IC integration, and heterogeneous architectures. Execution speed has become a competitive differentiator, and compressed schedules leave little room for the traditional, sequential handoffs between design, DFT, verification, and silicon validation teams. On top of that, there’s a well-known, industry-wide shortage of experienced DFT talent. AI augmentation is therefore moving from optional productivity aid to operational necessity. This panel asks a practical question: as AI agents take on DFT tasks once reserved for experienced engineers, what should the DFT engineer of the future look like, and how should organizations restructure to get there?)

10:30-12:00: Applied AI in DFT: Skill developments and customer applications (Organizer: Ron Press, Siemens EDA; Abstract: Applied AI in DFT explores how semiconductor engineers can effectively adopt and customize AI-driven Design-for-Test workflows. The session covers practical interaction with agentic EDA tools, LLMs, and supporting infrastructures. The talk includes best practices for prompting, managing AI-generated data, validating results, and troubleshooting unexpected behavior. Industry speakers will share real-world experiences deploying AI in production DFT environments. They will demonstrate how company-specific design challenges, traditionally addressed through custom scripts and DRCs, can be enhanced through reusable AI skills and workflow automation. Attendees will gain practical insights into balancing user customization with vendor capabilities, understanding the effort required to develop specialized AI solutions. They will gain practical insights in applying AI responsibly to improve productivity, quality, and scalability in modern semiconductor test design.)

Talk 1: Your role in new AI in DFT
Presenter: Amer Guettaf, Principal DFT Architect, Siemens EDA
Amer will present on what to expect and how to interact with DFT tool agentic flows.
Talk 2: Bring product context into AI
Presenter: Anusha Kotha, Lead DFT Engineer, Microsoft
Anusha is part of the DFT AI development team in Microsoft and will share experience in flow development
Talk 3: Practical implementation of AI in DFT
Presenter: Sujay Pandey, EDA Tools Software Engineer, Intel
Sujay works in Intel's Central Tools, Flow, and Methodology (TFM) team and will share how AI agents and skills can help in shift-left for Design-for-Test (DFT).

1:00-2:30pm: AI in test chips in view of heterogeneous integration, from 2.5D interposers and CoWoS to hybrid bond
Talk1: Ramune Nagisetty, PDF Solutions
Talk 2: Moran Wolf and Noam Brousard, Protean Tecs
Talk 3: Priyavadan Kumar, AMD (Beyond the Copilot: Engineering Trustworthy AI Agents for Semiconductor Test: AI agents can accelerate test-program development and debug, access to engineering knowledge, and test-data analytics, but deploying them responsibly requires more than model performance. This talk presents a practical architecture combining authoritative engineering context, controlled tools, persistent workflow state, evidence-based evaluation, and risk-based approvals. It will illustrate how engineers remain accountable as workflows progress from assistance toward bounded automation, and why these controls become increasingly important as advanced packaging expands data, identity, and provenance boundaries across die, chiplet, package, and system test.)

2:45-3:55pm: Panel - How does test engineering life will be like in the near future?
(Open Discussion with All Presenters)

3:55-4:00pm: Closing remark – Look Forward To Next Year