Unified UVM Testbench: Integrating Random, Directed and Pseudo-Random Verification Capabilities

Amitav Mitra, Kilaru Vamsikrishna, Shaikh Salehabibi and Sushrut B Veerapur

A UVM Testbench for Exploring Design Margins of Analog/Mixed-Signal Circuits: A PCI-Express Receiver Detection Circuit Example

Jaeha Kim

A Graph-Based UVM Generation Framework for Complex State Machine Verification

Francois Cerisier, Philippe Ledent and Eric Hargous

How Docker containers can make chip development more productive

Philipp Wagner, Holger Horbach, Martijn Berkers, Udo Krautz and Johannes Kösters

Tackling the cyber-physical system design challenges with MBSE and SystemC

Karsten Einwich, Rolf Meyer and Petri Solanti

Property Generator: simple generation of Formal Assertion IP

Tobias Ludwig and Osama Ayoub

Out of the Box Techniques for Data Path Verification

Atharva Kakde, Ketki Gosavi, Pradeep Bagavathiappan and Anshul Singhal

Minimally Intrusive Safety and Security Verification of Rust RTIC Applications

Pawel Dzialo, Ivar Jönsson, Malte Munch, Erik Serrander, Johan Eriksson and Per Lindgren

Offloading Complex Mathematical Computations in System Verilog Testbenches - Asyncronous verification of ethernet Reed-Solomon forward error correction using third-party Python packages

Simon Coulter

Early Chip-Level Power Estimation using Digital Mixed-Signal Simulations

Ricardo Dantas, Akib Mohammad Azam Zaidi and Gabriela Alecu

DRAMPyML: A Formal Description of DRAM Protocols with Timed Petri Nets

Derek Christ, Thomas Zimmermann, Philippe Barbie, Dmitri Saberi, Yao Yin and Matthias Jung

GAP: A Generic Agent Pattern for Reusable Testbenches

Omar Younis, Peter Gad and Ahmed Adel

FPGA Firmware Verification: a common approach for simulation and hardware tests

Stefano Pavinato, Emmanuel D'Costa and Stephane Gabourin

Cadence Verisium - Optimizing Regressions and Debug with AI

Hans Zander and Moshik Rubin

Efficient SoC Modeling, Architectural Exploration, and Result Analysis using TLM2 based IPs

Rocco Jonack, Matthias Jung and Jean-Blaise Pierrès

Fast, Flexible, Timing-accurate and Open Source Performance Modeling Method for Compute Accelerators

Vishal Chovatiya, Andrew Stevens and Snehith Shenoy

Time-Travel Debugging for High-Level Synthesis

Jonathan Bonsor-Matthews, Greg Law, Chirag Goyal and Chris Croft-White

Data-Driven Approach to Accelerate Coverage Closure on Highly Configurable ASIC Designs

Tulio Pereira Bitencourt, Rasadhi Attale, Samuel Man-Shun Wong, Po-Shao Cheng and Anton Tschank

Simulation Time Federation using the Zenoh framework between SystemC's and QEMU

Mark Burton, Mahmoud Kamel and Alwalid Salama

Introduction to the Apheleia Verification Library

Andy Bond

Creating a Co-Simulation Enivronment for Questa Simulator Using QEMU

Telat Işık, Faruk Karaahmet and Melike Karabalkan