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![]() Title:Efficient SoC Modeling, Architectural Exploration, and Result Analysis using TLM2 based IPs Conference:DVCon Europe 2025 Tags:DRAM modeling, interconnect IP, performance exploration, performance visualization, TLM2 modeling and Virtual Prototypes Abstract: The advancement of semiconductor technology, characterized by shrinking feature sizes and the increasing viability of die-to-die and chip-to-chip interconnects, continues to drive the integration of complex electronic systems onto a single chip, giving rise to the paradigm of System-on-Chip (SoC) design. The ability to model the behavior of these intricate systems before committing to physical implementation is paramount. This tutorial addresses the critical need for efficient modeling, comprehensive architectural exploration, and insightful result analysis within the constraints of typical project lifecycles. The increasing availability and maturity of pre-verified Intellectual Property (IP) blocks, such as CPUs, DRAM controllers, and interconnect fabrics, present an opportunity to shift the focus from low-level component modeling to system integration. Efficient SoC Modeling, Architectural Exploration, and Result Analysis using TLM2 based IPs ![]() Efficient SoC Modeling, Architectural Exploration, and Result Analysis using TLM2 based IPs | ||||
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