The verification of complex designs which include big control and protocol state-machines has always been a challenge. Although SystemVerilog and UVM have brought to the verification community the ability to create constrained random scenarios by means of test sequences and sequence libraries, the management of complex protocols from those sequences often leads to spaghetti code, hard to maintain sequence libraries, directed tests or worse, not verifying all the targeted features. In parallel, we have seen the emergence of graph-based approaches resulting in the development of the PSS (Portable Stimulus Standard), bringing the capacity to think differently about the use case scenarios, allowing them to be combined in a much bigger picture and enabling cross platform reuse. Those techniques are really efficient at System Level and for verification of complex SoC. However, using them requires learning a new language, integrating new tools and are therefore less of an added value in complex IPs and subsystem projects already using UVM. Meanwhile, SystemVerilog provides interesting language constructs that can leverage standard UVM sequences for a more efficient constrained random generation, therefore accelerating the coverage closure of complex state machine designs. The randsequence keyword is really powerful in generating graph-based scenarios providing that we stick to a well-structured template. Using its full capabilities and adding a few tricks we can even enable fully controlled graph explorations as well as automatic coverage closure completion, whether the design is fully controlled by the testbench or the testbench reacts to the design behavior. This paper presents the overall approach, proposes an application proven template for the randsequence graph-based UVM sequence and leverages this by automating the template generation. A concrete example, based on the PCIe link training state-machine is then presented.