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![]() Title:Expediting Coverage Closure in Digital Verification with the Portable Stimulus Standard (PSS) Authors:Tulio Pereira Bitencourt, Nikolaos Ilioudis, Ahmed Abd-Allah, Daniel Waszczak, Anton Tschank and Tom Fitzpatrick Conference:DVCon Europe 2025 Tags:accelerate coverage closure, enhance bug finding, expedite digital verification, portable stimulus standard, PSS and UVM and real-world data Abstract: The semiconductor industry continually faces increasing complexity, driving the need for optimized, reliable integrated circuits (ICs). Today’s systems must perform diverse tasks and connect with many devices, making verification highly challenging. The Portable Stimulus Standard (PSS) from Accellera addresses this complexity by enabling testcases at various abstraction levels (e.g., SystemVerilog UVM, FPGA prototyping). Since its release in 2018, PSS adoption has grown, with many EDA tools supporting it. For digital ASIC verification, PSS extends UVM with dynamic, random scenario generation—allowing more efficient and comprehensive testing. PSS tasks can be mapped to UVM sequences, while PSS tools generate scenario permutations based on model rules. With just three files—a PSS model, task list, and PSS test—engineers can automate broad, randomized coverage, optimizing bug detection and accelerating closure. This tutorial introduces PSS, covers building robust PSS models, and details integrating PSS with UVM. Key topics include:
By combining PSS with UVM, engineers can enhance productivity, improve bug coverage, and reduce verification time. PSS is increasingly vital in digital verification—and its ease of use and effectiveness make it a go-to tool for companies seeking better results, faster. Expediting Coverage Closure in Digital Verification with the Portable Stimulus Standard (PSS) ![]() Expediting Coverage Closure in Digital Verification with the Portable Stimulus Standard (PSS) | ||||
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