This paper presents a UVM testbench for characterizing the design margins of analog/mixed-signal (AMS) circuits by finding the worst-case deviation of the circuit’s response across a continuous-valued parameter space. The testbench combines a reactive stimulus technique with a Bayesian optimization algorithm to efficiently and adaptively explore the parameter space. Using a PCI Express receiver detection circuit as a case study, of which analog components are modeled in SystemVerilog with XMODEL primitives, the paper demonstrates how the testbench can identify design points that maximize margin and assess their sensitivity to secondary operating conditions. This approach enables adaptive, coverage-driven AMS verification, supporting more automated and scalable margin analysis in complex mixed-signal systems.