This paper proposes an approach for implementing functional coverage within a UVM-based top-level testbench for analog intellectual property (IP) in ASICs. The methodology is compatible with both Digital Mixed Signal (DMS) and Analog Mixed Signal (AMS) simulations. Functional covergroups are defined in the testbench environment based on the IP specification. These covergroups help extract coverage metrics to ensure that critical chip-level features are exercised and captured by the verification plan. A key focus of this work is the adaptation of metric-driven verification techniques—common in digital verification—for use in analog IPs. The approach supports both real number models and analog schematics in mixed-signal simulations, helping to bridge the gap between analog and digital design and verification processes