This paper proposes a methodology for early power estimation during chip design phase using digital mixed-signal (DMS) simulations. It is not a replacement for the more accurate chip-level analog mixed-signal (AMS) simulations, which are typically considered the sign-off criterion for pre-Silicon power consumption estimation. However, AMS simulations are time-consuming and usually executed late in the development phase; if implementation or architectural issues are found, it is often too late for major design updates, thus delaying the tape-out process (i.e. pre-Silicon phase completion). The proposed method is an auxiliary technique aiming at identifying power consumption related problems early in the design phase, which can later be confirmed through AMS simulations. It relies on analog model-based digital simulations to estimate dynamic power consumption. Individual contributions of all analog IPs are consolidated according to the activation sequence of each corresponding analog model during digital simulations, thus allowing early identification of potential power violations. Although it is not intended to produce accurate power figures, especially over transient states, this method offers a preliminary check for power consumption across different operational modes and configurations.