Verification of modern System on Chip (SoC) designs involve many components.

Hardware Description Languages (VHDL, System Verilog), Unified Power Format (UPF), Software Languages (C#/C++), Interconnect standards (IP-XACT, AMBA) and speciality purpose built layers such as the Universal Verification Methodology (UVM) and System Verilog Assertions (SVA).

This tutorial explores using Arteris SOC Integration technolgies to "blend" these components together by proposing a more efficient methodology to increase productivity and help ensure first time SoC project success.