Functional Safety (FuSa) standards are mandatory in modern semiconductor chips since the industry evolves, and chips are largely used in automotive industry (Automotive FuSa standard – ISO26262). Failure analysis is required to be completed throughout the RTL design and necessary safety mechanisms needs to be added in the RTL design. Which means, FuSa begins with the design intellectual properties (IPs). FuSa related RTL must be added for legacy IPs based on the analysis and new IPs must be architected with FuSa considerations. This paper demonstrates the methodology to verify FuSa RTL design by using reusable UVC (UVM verification component) in constrained random UVM TB (Module or IP Level TB)