PROGRAM
Days: Monday, January 25th Tuesday, January 26th Wednesday, January 27th Thursday, January 28th
Monday, January 25th, 2027
View this program: with abstractssession overviewtalk overview
12:30-13:30Lunch Time
13:30-15:30 Session 1D: The Inference Engine: From Speculative Decoding to Compiler-Driven Hardware Generation
Technical Session |
Location: Conference Room 3
| 13:30 | AHEAD: A Fast and Efficient MoE Speculative Decoding System via Dynamic Draft–Verify Coordination (abstract) |
| 13:50 | Speculate, Verify, Repeat: Faster Decoding via Speculative KV Access and Verification Feedback (abstract) |
| 14:10 | TriM: Efficient MoE Inference on Edge CPU-GPU Systems via Fused Quantization and Sensitivity-Guided Scheduling (abstract) |
| 14:30 | AccTTS: Characterizing and Optimizing Workload Dynamics in Test-Time Scaling (abstract) |
| 14:50 | DFAC: Dataflow-Aided Intra-cluster Coalescer for AI Accelerators (abstract) |
| 15:10 | Compiler-driven Generation of Domain-Specific AI Hardware Accelerators for Edge Devices (abstract) |
13:30-14:30 Session 1E-1: Die-to-Die and Board-Level Routing
Location: Conference Room 4
| 13:30 | Efficient Concurrent Die-to-Die Routing with Teardrop and Offset-Via Awareness (abstract) |
| 13:50 | ARC: Any-Angle PCB Routing with Obstacle Avoidance under Complex Design Rules (abstract) |
| 14:10 | A Consensus-Optimization Framework for Progressive Clearance-Aware PCB Legalization with Irregular Components (abstract) |
14:30-15:30 Session 1E-2: Manufacturing-Aware Design and Physical Verification
Location: Conference Room 4
| 14:30 | RT-DRC: Accelerating Design Rule Checking Using GPU Ray-Tracing Cores (abstract) |
| 14:50 | An Efficient Layout Decomposition Framework via Unsatisfiable Core (abstract) |
| 15:10 | A DTCO-Oriented Early Digital Bring-Up Framework under Incomplete PDK and Standard-Cell Assets (abstract) |
15:30-15:50Coffee Break
15:50-17:50 Session 2D: On-Chip Networks and Memory Hierarchies
Technical Session
Location: Conference Room 3
| 15:50 | MinVNS: Minimal Virtual Network Separation for Deadlock Avoidance in Modular Network-on-Chip (abstract) |
| 16:10 | RESCUE: Runtime Setup Resilience for TDM-Based Circuit-Switched NoCs (abstract) |
| 16:30 | Q-COMPASS: A Circuit-Calibrated Simulation Framework for QDI NoC Architecture Exploration (abstract) |
| 16:50 | Declared Event Semantics: Cross-Layer Memory-Hierarchy Co-Design for Latency-Critical Systems (abstract) |
| 17:10 | S-cache Directory: Efficient Sharer Tracking for Entry-Constrained Coherence Directories (abstract) |
| 17:30 | UACC: A Chiplet-Based Auxiliary Cache for Cost-Effective Performance Scaling in Multicore Processors (abstract) |
15:50-17:50 Session 2E: Low-Power Design, Power Estimation, and Power-Intent Optimization
Technical Session
Location: Conference Room 4
| 15:50 | Anonymous: A CPU-GPU Heterogeneous Engine for Glitch-Aware Time-Based Gate-Level Power Analysis (abstract) |
| 16:10 | GRACE: GRAph-based power Consumption Estimator with Parallel Switching Activity Propagation (abstract) |
| 16:30 | An In-situ Self Clock-Gated 7474 Style Scan-Mux-D Low Power Flip-Flop (abstract) |
| 16:50 | FlexRF: Retention-Aware Compilation for Low-power and Area-Efficient Flexible Microprocessors using IGZO DRAM-style Register File (abstract) |
| 17:10 | PowerPilot: Preserving Verified Progress in LLM-Based Power-Intent ECO Repair (abstract) |
| 17:30 | Physics-Informed Generative Model Based Aging Library Characterization (abstract) |
Tuesday, January 26th, 2027
View this program: with abstractssession overviewtalk overview
10:30-11:00Coffee Break
11:00-12:00 Session 3B: Living on the Edge: Real-Time Intelligence Under Tight Budgets
Technical Session
Location: Conference Room 1
| 11:00 | EdgeDAE: Acceleration of Diffusion Action Experts for Real-Time Physical AI with Tiny VLAs on Edge FPGA-GPU Systems (abstract) |
| 11:20 | CRANE: Criticality-Aware Concurrent Neural Inference on Heterogeneous Edge Platforms (abstract) |
| 11:40 | Progressive Computation Scheduling for Deadline-Critical Tasks in Hierarchical Edge Networks (abstract) |
11:00-12:00 Session 3C: Neural Computation in Emerging Device Technologies
Technical Session
Location: Conference Room 2
| 11:00 | IMPACT: IoT SNN Inference with a Metadata-Guided Pulse-Width Control Architecture for Conductance-Time Weight Representation in RRAM (abstract) |
| 11:20 | OMNI-DC: One-shot Multi-input Neural-Inference-Based Data Converter for Analog Computation-in-Memory (abstract) |
| 11:40 | Observability-Aware Runtime Reliability for MZI-Based Optical Neural Networks (abstract) |
11:00-12:00 Session 3D: Beyond Conventional Synthesis: Superconducting Logic Mapping and Verified Microarchitecture Replacement
Technical Session
Location: Conference Room 3
| 11:00 | Fanout-Multiplicity-Aware Technology Mapping for Multi-Output Superconducting Logic (abstract) |
| 11:20 | Formally Verified Contract-Aware Replacement of Ready/Valid Microarchitectures (abstract) |
11:00-12:00 Session 3E: Processor Architectures, Fault Injection, and System Security
Technical Session
Location: Conference Room 4
| 11:00 | Staggered Instruction-Fetch Duplication: A Lightweight Processor-Level Countermeasure Against Fault Injection (abstract) |
| 11:20 | Reasoning and Modeling of Instruction Corruption of MCU under EMFI (abstract) |
| 11:40 | Secure Reconfiguration for Multi-Tenant FPGAs (abstract) |
11:00-12:00 Session 3F: Quantum Circuit Optimization
Technical Session
Location: Conference Room 101-102
| 11:00 | A Resource-Efficient Quantum Circuit for Fixed-Point Logarithm Operations with Analytical Error Bounds (abstract) |
| 11:20 | Scalable Quantum Circuits Partitioning via Shortest-Path Search and Circuit Transformation (abstract) |
| 11:40 | Reducing T-depth in quantum circuits through adaptive allocation of ancillae between T-par and H-gadgets (abstract) |
12:00-13:00Lunch Time
13:00-15:00 Session 4B: Teaching Silicon New Tricks: Cores, GPUs, and Arrays Reshaped for Modern Workloads
Technical Session
Location: Conference Room 1
| 13:00 | Resource-Efficient Heterogeneous CGRA for Kernels with Control Flow (abstract) |
| 13:20 | BB8: Blocking Buffer for breaking head-of-line stalling in GPGPUs via Instruction Bypassing. (abstract) PRESENTER: Munawira Kotyad |
| 13:40 | Accelerating 5G NR Channel Estimation with a Complex-Arithmetic RISC-V Vector Extension (abstract) PRESENTER: Zexu Tan |
| 14:00 | Prefix-Branch Software Co-Design for Random Forest Acceleration on Embedded Hybrid TCAMs (abstract) |
| 14:20 | RobotCFU: A Tightly Coupled Multi-Operator CFU for Embedded RISC-V Robot Control (abstract) |
| 14:40 | A Minimal MMU for Memory Virtualization on Microcontrollers for time-sensitive applications (abstract) |
13:00-15:00 Session 4C: Advanced Hyperdimensional and Neural Computing Techniques
Technical Session
Location: Conference Room 2
| 13:00 | CABLE: A Cached Bidirectional and Multi-lane Item Memory\\for Efficient Hyperdimensional Computing (abstract) |
| 13:20 | SpikeFold: An FPGA-based Neuromorphic Processor with DSP Optimization and Parallel Weight Update STDP (abstract) |
| 13:40 | Nexus: Activity-Aware Capacity-Constrained Neuron Partitioning for Multicore SNN Accelerators (abstract) |
| 14:00 | Cross-Layer Co-Designed In-Memory Hyperdimensional Computing Accelerator for Proteomics at the Edge (abstract) |
| 14:20 | Online Open-World Wafer Defect Discovery using Hyperdimensional Computing (abstract) |
| 14:40 | Hit-SME: A High-throughput Hybrid SNN-based MLP Engine for Neural Volume Rendering (abstract) |
13:00-15:00 Session 4D: Breaking the Memory Wall: Emerging Memory Architectures for LLM KV Caches and Long-Context Inference
Technical Session
Location: Conference Room 3
| 13:00 | CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV Caches (abstract) |
| 13:20 | KV3D: KV Cache-Centric Monolithic 3D-Stackable DRAM-Based Accelerator for LLM Serving (abstract) |
| 13:40 | DeferKV: Long-Context LLM Attention Acceleration with Per-Token Scale Folding and Bank-Local Softmax on PIM (abstract) |
| 14:00 | CRISP: Paged Sparse Attention on DRAM-PIM with Row-Band-Aware KV Allocation and Frame-Derived Addressing (abstract) |
| 14:20 | A Waferscale Memory Architecture for Efficient LLM Inference (abstract) |
| 14:40 | LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the Edge (abstract) |
13:00-15:00 Session 4E: Power Delivery, IR Drop, and Backside Design
Technical Session
Location: Conference Room 4
| 13:00 | CertIR: Certified Static IR-Drop Estimation with Physics-Anchored Neural Correction (abstract) |
| 13:20 | PDN-Aware Graph Transformer-based Dynamic IR Drop Prediction with Criticality-Guided Subgraph Construction (abstract) |
| 13:40 | Cross-Layer Reinforcement Learning for Power-Via Optimization in Multilayer RDL Power/Ground Plane Synthesis (abstract) |
| 14:00 | Power Network Topology Optimization for Top Dies in Backside-Powered F2F 3D ICs (abstract) |
| 14:20 | Grad-BSS: Differentiable Optimization for Full-Stack Backside Signal Routing (abstract) |
| 14:40 | Clock Distribution Network with Backside Clock Mesh in BSPDN Architecture (abstract) |
13:00-15:00 Session 4F: Bulletproof Chips: Power of Formal Verification
Technical Session
Location: Conference Room 101-102
| 13:00 | Decompose Transform Refine Verify: A new approach for scalable formal verification (abstract) |
| 13:20 | GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits (abstract) |
| 13:40 | From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5 (abstract) |
| 14:00 | SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification (abstract) |
| 14:20 | Adaptive BTOR2 Reformulation via Solver-Aware Equality Saturation (abstract) |
| 14:40 | FormalPCell: Formal DRC Verification of Parameterized Layout Cells via Symbolic Interpretation and SMT Solving (abstract) |
15:00-15:20Coffee Break
15:20-17:20 Session 5B: Memory and Compute, Converging for the LLM Era
Technical Session
Location: Conference Room 1
| 15:20 | ATLAS: A Thermal-Aware 3D-Stacked Heterogeneous Architecture For LLM Multi-Turn Dialogue Serving (abstract) |
| 15:40 | Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture (abstract) |
| 16:00 | TACO: Topology-Aware Compression via Hardware–Software Co-Design for Robust CiM-Accelerated Edge RAG Retrieval (abstract) |
| 16:20 | Multi-Agent LLM Serving with SSD-Based KV-Cache Offloading (abstract) |
| 16:40 | TreePIM: A Heterogeneous Processing-in-Memory Architecture for Tree-based Speculative Decoding (abstract) |
| 17:00 | PSD-CIM:A Computing-In-Memory Attention Accelerator with Predictor-Free Sparsity search and Distribution Shaping (abstract) |
15:20-17:20 Session 5C: AI Methods for Analog Circuit Design and Physical Implementation
Technical Session
Location: Conference Room 2
| 15:20 | CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction (abstract) |
| 15:40 | ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration (abstract) |
| 16:00 | APPlace: Co-Optimizing Device Locations and Access Points for Routing-Aware Analog Placement (abstract) |
| 16:20 | An Explainable Analog/Mixed-Signal Routing Agent using Deterministic Constraint-Conflict Diagnosis (abstract) |
| 16:40 | CktHVR: A Convergence-Aware GNN-VLM Hypothesize-Verify-Refine Framework for Analog Circuit Topology Rectification (abstract) |
| 17:00 | LMSACO: LLM-Guided Multi-Objective State-Adaptive Analog Circuit Sizing Optimization (abstract) PRESENTER: Ying Hu |
15:20-17:20 Session 5D: Silicon Meets Action: Accelerators for Embodied, Visual, and Edge Intelligence
Technical Session
Location: Conference Room 3
| 15:20 | ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision Switching (abstract) |
| 15:40 | ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action Models (abstract) |
| 16:00 | HB-VGGT: Exploiting Head-Wise Complementary Redundancy for Efficient VGGT Inference on Hybrid-Bonded Architecture (abstract) |
| 16:20 | CoD-MiCo: Co-Design of Mixed-Compression RISC-V Extensions for Neural Networks on FPGAs (abstract) |
| 16:40 | Enabling Energy-Efficient TinyML Inference via Fused Tensor Architecture (abstract) |
| 17:00 | Taming Irregular Sparsity with a Regular Systolic Array for Efficient DNN Training (abstract) |
15:20-17:20 Session 5E: 3D IC Floorplanning, Clocking, and Integration
Technical Session
Location: Conference Room 4
| 15:20 | NaCo3D: Native and Compact 3D Floorplanning via Reinforcement Learning (abstract) |
| 15:40 | A Two Stage Learning-Based Thermal-Aware Framework for 3D Fixed-Outline Soft-Module Floorplanning across Chip Sizes (abstract) |
| 16:00 | MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition Heuristic (abstract) |
| 16:20 | XCTS: Cross-Tier-Aware Differentiable Clock Tree Synthesis for 3D Integrated Circuits (abstract) |
| 16:40 | A Comprehensive Clock Tree Synthesis with Useful Skew for 3D ICs (abstract) |
| 17:00 | Operation-Aware Twisting of Folded Bit-Lines for Crosstalk Cancellation in Wafer-Bonded DRAM (abstract) |
15:20-17:20 Session 5F: Accelerated Validation: Emulation and Smart Benchmarks
Technical Session
Location: Conference Room 101-102
| 15:20 | Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware Adaptation (abstract) |
| 15:40 | Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems (abstract) |
| 16:00 | Spec2Plan: An LLM-Powered Framework for Comprehensive Verification Plan Generation (abstract) |
| 16:20 | Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification (abstract) |
| 16:40 | Functionality-Aware Is Not Synthesis-Invariant: An End-to-End Audit of Circuit-GNN Representations (abstract) |
| 17:00 | ML-AccelBench: A Benchmark for Evaluating LLM-Based ML Accelerator RTL Generation (abstract) |
17:40-19:10 Session 2S
ACM SIGDA Student Research Forum / WIP Poster Session
Location: Conference Room 201-203
Wednesday, January 27th, 2027
View this program: with abstractssession overviewtalk overview
10:00-10:20Coffee Break
10:20-12:20 Session 7B: Global and Detailed Placement Engines
Technical Session
Location: Conference Room 1
| 10:20 | Structure-Preserving Density Modeling for Electrostatics-Based Analytical Placement (abstract) |
| 10:40 | Learning-Guided Adaptive Cell-Wise Optimization for Mixed-Size Global Placement (abstract) |
| 11:00 | qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits (abstract) |
| 11:20 | ALTO: Joint Track-Height and Placement Optimization for Non-Integer Mixed-Cell-Height Designs (abstract) |
| 11:40 | Wirelength-Driven Mixed-Cell-Height Detailed Placement with Multi-Row Cell Relocation (abstract) |
| 12:00 | SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes (abstract) |
10:20-12:20 Session 7C: Advanced Approximate and Stochastic Computing Techniques
Technical Session
Location: Conference Room 2
| 10:20 | CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary Synthesis (abstract) |
| 10:40 | REASON: RNG-Aware Finite-State Machines for Hardware-Realistic Stochastic Nonlinear Approximation (abstract) |
| 11:00 | Low-Power Approximate MRAM CAM with Dynamic-Reference for HDC Associative Search (abstract) |
| 11:20 | SWAPPER: Dynamic Operand Swapping in Non-commutative Approximate Circuits for Online Error Reduction (abstract) |
| 11:40 | AX-AGENT: Contract-Driven Closed-Loop Framework for Error-Bounded PPA-Aware Approximate RTL Generation (abstract) |
| 12:00 | MATE: Model-Assisted Trade-off Exploration for Quality-Aware Approximate Matrix Computing (abstract) |
10:20-12:20 Session 7D: Memory-Centric Computing and Efficient LLM Inference
Technical Session
Location: Conference Room 3
| 10:20 | InfoCIM: An Information-Theoretic Framework for Modeling and Design of Noise-Limited Analog CIM (abstract) |
| 10:40 | Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution (abstract) |
| 11:00 | DRAC: A Static Analysis for DRAM Row Activation Count Toward Efficient Processing-in-Memory Code Generation (abstract) |
| 11:20 | Less is More: KV Cache Scheduling for Bandwidth-Efficient LLM Inference on FPGA (abstract) |
| 11:40 | RASP-LLM: Radiation-Aware Design-Space Exploration of Precision and Selective Protection for On-Orbit LLM Inference (abstract) |
| 12:00 | Reducing Cascaded Speech-to-Speech Latency via Speculative Prefilling and Incremental Cache Recovery (abstract) |
10:20-12:20 Session 7E: Thermal and Mechanical Analysis and Optimization for 3D ICs and Advanced Packaging
Technical Session
Location: Conference Room 4
| 10:20 | DiffTherm: A Differentiable Thermal Formulation for Cell-Via Co-Optimization in 3D ICs (abstract) |
| 10:40 | SPLIT-MOR: Fast and Accurate Model Order Reduction for Nonlinear Transient Thermal Simulation of 2.5D/3D ICs (abstract) |
| 11:00 | SiliDiff: Post-Silicon Thermal and Power Reconstruction from Sparse Sensing with a Cascaded Conditional Diffusion Model (abstract) |
| 11:20 | Gradient-Guided Thermal-Aware Timing Robustness Optimization Under Temperature Inversion (abstract) |
| 11:40 | STRIDE: Sparse Thermal Reconstruction-Informed Differential Encoding for Thermally Stable 3D-Integrated Analog CIM (abstract) |
| 12:00 | ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging (abstract) |
10:20-12:20 Session 7F: Hardware Trojan Localization, RTL Fuzzing, and Security Verification
Technical Session
Location: Conference Room 101-102
| 10:20 | GREG: A Graphical Static Analysis Framework for Early Hardware Security Verification (abstract) |
| 10:40 | PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security Validation (abstract) |
| 11:00 | DISSECT: Cross-Family RTL Trojan Localization by Auditing Structural–Functional Disagreement (abstract) |
| 11:20 | Cube-based Finite-State-Machine Extraction via SAT Generalizations (abstract) |
| 11:40 | Functional Retrieval for Resynthesis-Robust Hardware Trojan Detection in Gate-Level Netlists (abstract) |
| 12:00 | Between The Cracks: Uncovering Illegal-Instruction Bugs in RISC-V Processors by Exploring the Unified Encoding Space (abstract) |
12:20-13:20Lunch Time
13:20-15:20 Session 8B: Hypergraph Partitioning and Clustering
Technical Session
Location: Conference Room 1
| 13:20 | Placement Guidance Generation via Timing-Aware Hypergraph Partitioning and Multi-Criteria Cluster Selection (abstract) |
| 13:40 | FRESHPart: Feedback-Reshaped Spectral Embedding for Hypergraph Partitioning (abstract) |
| 14:00 | Learning-Augmented Multilevel Hypergraph Partitioning with Net-Level Cut Priors (abstract) |
| 14:20 | RAP: Resource‑Aware Scheduling for GPU Accelerated Hypergraph Partitioning (abstract) |
| 14:40 | CCPart: Timing-Aware Multi-Level Partitioning for Multi-FPGA Systems with Incremental Timing Analysis (abstract) |
| 15:00 | From Communities to Coordinates: Hierarchical Clustering–Guided Placement for Large-Scale FPGAs (abstract) |
13:20-15:20 Session 8C: Efficient AI Models and Inference
Technical Session
Location: Conference Room 2
| 13:20 | SHARD: Sub-Transformer Harnessing for Adaptive Resource-Aware Deployment (abstract) |
| 13:40 | MemFLoRA: Memory-Floor LoRA for CNN Adaptation at the Edge (abstract) PRESENTER: Mehmet Emre Akbulut |
| 14:00 | NgramRL: Accelerating RL Post-Training for Structured Generation via Rollout-Aware N-gram Speculative Decoding (abstract) PRESENTER: Nilesh Prasad Pandey |
| 14:20 | T3R: Training-Free Two-Stage Token Refinement Towards Efficient and Robust VLA Models (abstract) |
| 14:40 | SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference Acceleration (abstract) |
| 15:00 | MARCO: Markov Decision-based Adaptive Path Selection for Dynamic Layer Skipping (abstract) |
13:20-15:20 Session 8D: Design Space Exploration and Co-Design for Emerging Architectures
Technical Session
Location: Conference Room 3
| 13:20 | Naviq: An Open-Source System-on-Chip Simulator for Rapid Prototyping, Verification, and Design Space Exploration (abstract) |
| 13:40 | PaFeDSE: Pareto-Feedback-Guided Microarchitecture Design Space Exploration for Efficient Pareto Search (abstract) |
| 14:00 | MAP-DSE: A Fast Performance Simulator for Large-Scale Microarchitectural Design Space Exploration (abstract) |
| 14:20 | ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs (abstract) |
| 14:40 | From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs (abstract) |
| 15:00 | LU-Evolve: Agent-Based Algorithm Exploration for Sparse LU Solvers (abstract) |
13:20-15:20 Session 8E: Physical Unclonable Functions (PUFs) and Hardware Authentication
Technical Session
Location: Conference Room 4
| 13:20 | EMPUF: A Leakage-Controlled Pre-Fabrication Benchmark for PCB Spectral Fingerprints (abstract) PRESENTER: Renchao Li |
| 13:40 | A Lightweight Microring-Resonator PUF Design for Silicon Photonics Transceivers (abstract) |
| 14:00 | Lightweight Key-Based Hardware Device-ID Authentication: A Reliable, ML-Resistant Alternative to PUFs (abstract) |
| 14:20 | A Reliability-Enhanced SOT-MTJ PUF with Obfuscated Write-Back for Physical-State Exposure Mitigation (abstract) |
| 14:40 | Power and EM Side-Channel Leakage Mitigation in Oscillator-Based PUFs via Sampling Techniques (abstract) |
13:20-15:20 Session 8F: Future Computing: Architectures and Tools for DNN Accelerators, CIM, Neural-Hybrid Computing, Ising Machines, and Microfluidics
Technical Session
Location: Conference Room 101-102
| 13:20 | TADA: Technology Aware DNN Accelerator Performance and Energy Estimator (abstract) |
| 13:40 | CAS: A Ferroelectric Compute-in-Memory Annealer for Sparse Combinatorial Optimization Problems (abstract) |
| 14:00 | FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy Compression (abstract) |
| 14:20 | UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System (abstract) |
| 14:40 | AutoIsing: An Automated Compiler for Programmable Ising Machine (abstract) |
| 15:00 | 3D-VASE: Volumetric-Aware Scalable and Efficient Multi-Layer Design Synthesis for 3D-Printed Microfluidics (abstract) |
15:20-15:40Coffee Break
15:40-17:40 Session 9B: AI-Assisted Modeling, Simulation, and Co-Design of Processor and Accelerators
Technical Session
Location: Conference Room 1
| 15:40 | A System-Level Typed-Graph Environment for Traceable Cycle-Level Co-Design of Heterogeneous AI Accelerators (abstract) |
| 16:00 | CoSim: A Cross-Layer Simulation Framework for System-Hardware Co-Design of LLM Inference (abstract) |
| 16:20 | MTPMoE: Exploiting Activation Skewness in Single-GPU MoE Multi-Token Prediction via Parallel Dense-Sparse Computing (abstract) |
| 16:40 | UnifyPower: A Unified Framework of Architecture-Level Power Model for Processors (abstract) |
| 17:00 | Multi-modal LLM-Driven Generation of Processor Performance Simulators from Datasheet Specifications (abstract) |
| 17:20 | FlowMapper: Detection-Guided Topology Reconstruction of Circuit Block Diagrams (abstract) |
15:40-17:40 Session 9C: AI Accelerator Design, Mapping, and Scheduling
Technical Session
Location: Conference Room 2
| 15:40 | IMPACT: Constraint-Aware Search for Imperfectly Factorized Accelerator Mappings (abstract) |
| 16:00 | DSEAgent: Agentic AI Accelerator Design Space Exploration via Expert-level Reinforcement Learning (abstract) |
| 16:20 | SymbOperon: Composable and Cost-Efficient Symbolic Reasoning Operators for Neuro-Symbolic Edge Perception (abstract) |
| 16:40 | FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators (abstract) |
| 17:00 | Hardware-Retargetable Grammar-Based NAS from Declarative Device Specifications (abstract) |
| 17:20 | Efficient End-to-End Hyperprior-Based Learned Image Compression on Edge GPUs via Thread-Level Parallel Entropy Coding (abstract) |
15:40-17:40 Session 9D: Advanced Logic Synthesis and Optimization
Technical Session
Location: Conference Room 3
| 15:40 | Node Reduction via Targeted ODC-Based Wire Additions for AIG Optimization (abstract) |
| 16:00 | Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation (abstract) |
| 16:20 | DeepResub: Towards Learned Logic Optimization Operators (abstract) |
| 16:40 | aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis (abstract) |
| 17:00 | PP2Tree: Learning-Guided Frontier Partitioning for Scalable Parallel Logic Synthesis (abstract) |
| 17:20 | Placement-Aware Logic Resynthesis with Cooperative Multi-Agent Reinforcement Learning (abstract) |
15:40-17:40 Session 9E: Reliable Heterogeneous Integration and Resilient AI Systems
Technical Session
Location: Conference Room 4
| 15:40 | A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip Packages (abstract) |
| 16:00 | Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems (abstract) |
| 16:20 | UniCASE: A Unified 16-bit Floating Point Format with Criticality-Aware Selective ECC for Efficient DNN Protection (abstract) |
| 16:40 | BLINK: Batch NormaLization-based INtegrity ChecKpoints for In-Situ Detection and Mitigation of Diverse Weight Corruptions in DNN Accelerators (abstract) |
| 17:00 | Fine-Grained Compiler-Assisted Hardening via Tolerant-Output Analysis for SDC–Runtime Trade-offs (abstract) |
| 17:20 | QoS Analysis for UCIe-based Cross-die Communication using Network Calculus (abstract) |
15:40-17:40 Session 9F: Secure AI Acceleration, Cryptographic Hardware, Side-Channel Attacks, and Privacy
Technical Session
Location: Conference Room 101-102
| 15:40 | TraceMorph: Real-Trace-Guided Execution-Level Obfuscation for RAPL-Based DNN Architecture Protection (abstract) |
| 16:00 | DRS: Unified Fully Homomorphic Encryption Hardware Accelerator with Scheme-Switching (abstract) |
| 16:20 | Investigation of Karatsuba Algorithm for Large-Bitwidth Modular Multiplication (abstract) |
| 16:40 | Security-Aware Runtime Control for Mitigating Token-Acceptance Side Channels in PIM/3D-Memory Speculative LLM Inference Architectures (abstract) |
| 17:00 | PFHE: Partial Fully Homomorphic Encryption on CNN Inference (abstract) |
| 17:20 | Multi-Feature Demographic Decoupling via LPC Cross-Synthesis for Privacy-Preserving Audio Anonymization (abstract) |
18:30-20:30Banquet
Thursday, January 28th, 2027
View this program: with abstractssession overviewtalk overview
10:00-10:20Coffee Break
10:20-12:20 Session 10B: From Reliable Cells to Smart Memory: The Circuit-Device Frontier
Technical Session
Location: Conference Room 1
| 10:20 | A XNOR-SRAM-Based Computing-in-Memory Macro for Memory-Augmented Neural Networks (abstract) |
| 10:40 | Topology as a Design Variable: Joint Architecture-Sizing Optimization for SRAM (abstract) |
| 11:00 | From Isolate to Co-Deployment Risk: Coupling-Aware Mapping for ACIM-Digital AI Accelerator (abstract) |
| 11:20 | NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline Scheme (abstract) |
| 11:40 | Device-Circuit Co-Optimization of SOT-MRAM with Accurate PPA Evaluation for Edge AI Training (abstract) |
| 12:00 | Reducing Read Retries by Skipping Similar Adjacent Read Voltage Parameters in 3D TLC NAND Flash (abstract) |
10:20-12:20 Session 10C: Analog/RF/Photonic Design Automation and Benchmarking
Technical Session
Location: Conference Room 2
| 10:20 | A Unified Framework for Circuit-Aware Tapped-Inductor Inverse Design with Topology-Aware Sequence Representation (abstract) |
| 10:40 | CONTOUR: Continuous Topology Search for System-Level RFICs via Bi-Level Optimization and Neural-Analytical Co-Modeling (abstract) |
| 11:00 | Atomic and Hierarchy-Safe Cross-Module Undo/Redo for Analog IC Design (abstract) |
| 11:20 | SPGLA-Net: A Slotline-Aware Port-Graph Linear Attention Residual Network for Sub-THz On-Chip Passive Modeling (abstract) |
| 11:40 | CABAgent: A Cross-Stage Agentic Framework for Generating PDK-Compatible and Layout-Verified Analog Circuit Benchmarks (abstract) |
| 12:00 | OptiClear: Differentiable Curvilinear Design Rule Legalization for Inverse-Designed Photonic Device (abstract) |
10:20-12:20 Session 10D: Every Bit Counts: Quantization and Low-Precision Arithmetic for Neural Inference
Technical Session
Location: Conference Room 3
| 10:20 | DPSQ : Dynamic Partial Sum Quantization with Mixed Granularity (abstract) |
| 10:40 | AlignQuant: Alignment First Two-Stage Integer Microscaling Format for Systolic Native LLM Inference (abstract) |
| 11:00 | PDG-CORDIC: A Posit-Decode-Guided Low-Latency CORDIC for Activation Function (abstract) |
| 11:20 | APRQ: Adaptive Prediction-Driven Residual Quantization Accelerator for Diffusion Transformers (abstract) |
| 11:40 | Enabling Efficient Quantized LLM Inference on Floating-Point CGRAs via Lightweight Integer Extensions (abstract) |
| 12:00 | MX-like Tensor Core for LLM Inference with NPU Integration via Hardware-Software Co-Design Exploration (abstract) |
10:20-12:20 Session 10E: Chiplet and Advanced Packaging Co-Optimization
Technical Session
Location: Conference Room 4
| 10:20 | SpectraPlace2.5D: Thermal-aware Chiplet Placement via Topology-guided MILP and Spectral Thermal Modeling (abstract) |
| 10:40 | Thermal-Aware Chiplet Placement and Shape Co-Optimization under D2D Interconnect Constraints for 2.5D Integration (abstract) |
| 11:00 | Thermal-Aware Chiplet Placement Integrating Evolutionary Reinforcement Learning and Monte Carlo Tree Search (abstract) |
| 11:20 | A HeteroGNN-Based Hierarchical Co-Optimization Framework for Floorplanning and Routing in Advanced Packaging (abstract) |
| 11:40 | PI-Aware Co-Layer Signal Routing and Power Plane Synthesis for Chiplet Interposers (abstract) |
| 12:00 | Network Flow Guided Routing and Force Directed Offset Via Placement for Advanced Chiplet Interconnect (abstract) |
10:20-12:20 Session 10F: Virtual Silicon: Advanced Simulation and Multi-Physics
Technical Session
Location: Conference Room 101-102
| 10:20 | TensorLUT: Exact Batched RTL Simulation via ANF-Lifted Tensor-Core GEMM (abstract) |
| 10:40 | Encoding Symmetries into Operator Learning: Towards Accurate Multi-Physics Simulation in Advanced Packaging (abstract) |
| 11:00 | Memory-Aware Design-Space Exploration for Multi-Threaded HLS Accelerators (abstract) |
| 11:20 | VoxPMC: A Fast Voxel-Based Particle Monte Carlo Simulator for Feature-Scale Process Topography Simulation (abstract) |
| 11:40 | Cross-Family Graph Learning for Sparse Aging-Aware Timing Characterization of Standard-Cell Libraries (abstract) |
| 12:00 | HOIST: A High-Order Interaction Surrogate for Sample-Efficient High-Sigma Yield Estimation in High-Dimensional Circuits (abstract) |
12:20-13:20Lunch Time
13:20-15:20 Session 11B: New Shapes of Computation — Beyond the Common Matrix in PIM/CIM
Technical Session
Location: Conference Room 1
| 13:20 | GD-PIM: A Low-Cost Gustavson Dataflow-Based Processing-in-Memory Architecture for SpGEMM (abstract) |
| 13:40 | MfSpGEMM: Merger-Free Row-Wise SpGEMM with Bitmap Accumulation and HBM-Aware Mapping (abstract) |
| 14:00 | RACE-FFN: Runtime-Adaptive Co-Execution in a Heterogeneous SA-CIM Architecture for Efficient MoE-FFN Acceleration (abstract) |
| 14:20 | GenMLIR: An MLIR Compiler for Dynamic Programming Workloads on Tier-Aware 3D-DRAM PIM (abstract) |
| 14:40 | HAVEN: High-Bandwidth Flash Augmented Vector ENgine for Large-Scale Approximate Nearest-Neighbor Search Acceleration (abstract) |
| 15:00 | An Area-Efficient CIM-Based Ising Annealer with Folded Mapping and Cooling-Scheduled Parallel Swaps Strategy for Large-Scale Traveling Salesman Problem (abstract) |
13:20-15:20 Session 11C: Paint by Silicon: Hardware Acceleration for Visual and 3D Generative AI
Technical Session
Location: Conference Room 2
| 13:20 | TempoGS: Temporal Binning and Expiration-Aware Gaussian Loading for Memory-Efficient 4D Gaussian Splatting Acceleration (abstract) |
| 13:40 | SSR-VAR: Exploiting Spatial- and Scale-aware Redundancy for Lightweight Inference of Visual Autoregressive Models (abstract) |
| 14:00 | DREAM:3D-stacked Token-wise Caching Diffusion Accelerator with Resource-Aware Mapping (abstract) |
| 14:20 | 3DToMe: A Morton-Local and Interaction-Aware Token-Merging Accelerator for Efficient 3D Diffusion Policy Inference (abstract) |
| 14:40 | ScaleLUT: A Fully-Parallel Configurable LUT-Based Accelerator for Real-Time Multi-Scale Super-Resolution (abstract) |
13:20-15:20 Session 11D: Parallel, Physical, and 3D-Aware Logic Synthesis
Technical Session
Location: Conference Room 3
| 13:20 | GARDEN: GPU-Accelerated Rapid Divisor Extraction (abstract) |
| 13:40 | GA2-CT: GPU-Accelerated Genetic Algorithm for Low-Power Compression-Tree Rewiring (abstract) |
| 14:00 | Fast Delay-oriented Logic Optimization with Parallel SOP Generation (abstract) |
| 14:20 | 3D-Syn: 3D-aware Synthesis Flow for Heterogeneous LogicFolding 3D ICs (abstract) |
| 14:40 | Multi-Output-Guided Transistor Network Synthesis and Layout for Sequential Cells (abstract) |
| 15:00 | Logic Resynthesis for Cross-Die Dependencies in Hybrid Bonded 3D ICs (abstract) |
13:20-15:20 Session 11E: LLM Agents and Algorithm Evolution for Physical Design
Technical Session
Location: Conference Room 4
| 13:20 | AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization (abstract) |
| 13:40 | Opening the Black Box: A Self-Correcting LLM Agent for EDA Toolchains Based on Source-Code Analysis (abstract) |
| 14:00 | CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models (abstract) |
| 14:20 | VPR-Evolve: Multi-Agent-Driven Algorithm Evolution for FPGA Place and Route (abstract) |
| 14:40 | Phase-Aware Monte Carlo Tree Search with LLM-Guided Proposal for Multi-Objective Physical Design Tuning (abstract) |
| 15:00 | EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair (abstract) |
13:20-15:20 Session 11F: AI-Enabled Lithography Modeling and Mask Optimization
Technical Session
Location: Conference Room 101-102
| 13:20 | MaxIM: A Plug-and-Play Maxwellian Engine via Interface Modification for Thick-Mask Lithography (abstract) |
| 13:40 | ResistONet: Cascade Operator Network for Photoresist Simulation (abstract) |
| 14:00 | MAGI-OPC: Manhattan Area–Edge Learning Guided by High-Quality ILT for Optical Proximity Correction (abstract) |
| 14:20 | Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features (abstract) |
| 14:40 | Curvilinear OPC via Diffeomorphic Deformation (abstract) |
| 15:00 | EtchMO: A Differentiable Etch Model for Mask Optimization (abstract) |
15:20-15:40Coffee Break
15:40-17:40 Session 12B: Noise-Aware, Robust, and Dependable AI on Analog Compute-in-Memory
Technical Session
Location: Conference Room 1
| 15:40 | ABNAT: Attention-Based Noise-Aware Training for Robust Transformers on Analog Compute-in-Memory Systems (abstract) |
| 16:00 | NANQ: Noise-Aware Mixed-Precision Non-Uniform Quantization for Neural Networks on Analog Compute-in-Memory (abstract) |
| 16:20 | ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory Hardware (abstract) PRESENTER: Yuannuo Feng |
| 16:40 | NOVA-CIM: Noise- and Correlation-Tolerant Stochastic Interfaces for Analog Compute-in-Memory (abstract) |
| 17:00 | ACCORD-IC: Contract-Checked Relation Transactions for Low-Bit Dynamic CNN–GNN Inference (abstract) |
| 17:20 | SURE-AI: Single-pass Uncertainty Estimation for Reliable Edge AI Accelerators (abstract) |
15:40-17:40 Session 12C: Analog Sizing Optimization and Photonic Design Automation
Technical Session
Location: Conference Room 2
| 15:40 | CRAFT: Constraint-Guided Region-Adaptive Search over Broad Design Spaces for High-Dimensional Analog Circuit Sizing (abstract) |
| 16:00 | Archive-Guided MOEA/D for Constrained Many-Objective Analog Circuit Sizing (abstract) |
| 16:20 | GLARE: Generalizable Large-scale Analog Sizing via Reinforcement Learning with Covariance-Guided Exploration (abstract) |
| 16:40 | FUSE: Five-Block MVM Energy Comparison (abstract) |
| 17:00 | MIBIFI: Differentiable Electronic–Photonic–Thermal Co-Simulation for Co-Packaged Optics Designs (abstract) |
| 17:20 | A Time-Encoded Analog Photonic Interposer for Energy-Efficient Integration of Analog Vision Sensors and Analog Accelerators (abstract) |
15:40-17:40 Session 12D: LLM and Agentic Methods for RTL and HLS Generation
Technical Session
Location: Conference Room 3
| 15:40 | VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts (abstract) |
| 16:00 | SpecLens: LLM-Based Verilog Generation with Specification-Derived Constraints via Behavioral Divergence (abstract) |
| 16:20 | MAESTRO: Memo-Augmented Multi-Agent Engine for Self-Testing RTL Code Generation with Resource Orchestration (abstract) |
| 16:40 | HLSClaw: Bringing Vibe Coding to High-Level Synthesis through Skill-Based Agentic Harness (abstract) |
| 17:00 | ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents (abstract) |
| 17:20 | HINT: Toward an Executable Hardware-Intent Intermediate Representation Layer for LLM-Driven RTL Generation (abstract) |
15:40-17:40 Session 12E: Timing Analysis, Prediction, and Optimization
Technical Session
Location: Conference Room 4
| 15:40 | RAPID: An Efficient and Accurate Ratio-Based Analytical Proxy for Interconnect Delay (abstract) |
| 16:00 | PACT: A Runtime Contract for Sparse-Topology Updates in GPU-Accelerated Timing ECOs (abstract) |
| 16:20 | Anonymous: Fast Clock-Aware Timing Propagation for Complex Clock Logic and Constraints with State Flow Graph Abstraction (abstract) |
| 16:40 | AnchorGNN: Cross-PVT Corner Timing Prediction via Anchor-Guided Graph Learning and STA-Aware Propagation (abstract) |
| 17:00 | Obstacle-Aware Timing-Driven Buffer Insertion via Feasible Shallow-Light Topology Reconstruction (abstract) |
| 17:20 | HGRP: Heterogeneous Graph Neural Network for Routability Prediction (abstract) |
15:40-17:40 Session 12F: Smart Testing: AI, Faults, and Chip Reliability
Technical Session
Location: Conference Room 101-102
| 15:40 | When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification (abstract) |
| 16:00 | CHAIDO: Open-Source Simulation-Based Fault Injection for the AMD Versal AI Engine (abstract) |
| 16:20 | Weight-Stationary Fault Recovery via Neuron Tuning in RRAM-Based CIM Neuromorphic Accelerators (abstract) |
| 16:40 | TRAIT: Trajectory-based Robust Aging-aware Chip Identification for Traceability (abstract) |
| 17:00 | WaveAce: Analyzing the Root Cause of SoC Test Failures via LLMs' Direct Waveform Inspection (abstract) |
| 17:20 | SRAM Bitcell-Peripheral Co-Optimization Under Array-Level Yield Constraints (abstract) |