ABSTRACT. Electrostatics-based analytical placement constructs electrostatic potential fields from the placement density distribution to guide cell movement. Consequently, the fidelity of the resulting electrostatic potential fields—and ultimately the placement quality—fundamentally depends on the fidelity of the underlying density representation. However, conventional density smoothing improves numerical stability at the expense of structural boundaries near obstacles and sharp density transitions, degrading electrostatic potential estimation and restricting effective cell movement. To address this limitation, this paper proposes a structure-preserving density modeling framework for electrostatics-based analytical placement. Rather than treating density smoothing as merely a numerical operation, the proposed framework preserves structural density characteristics during density refinement, thereby constructing more faithful electrostatic potential fields while maintaining numerical robustness. An adaptive density update mechanism is further introduced to progressively incorporate refined density information according to local density evolution, while balancing optimization stability and convergence speed. Experimental results on standard placement benchmarks demonstrate that the proposed framework consistently outperforms state-of-the-art electrostatics-based analytical placers in terms of wirelength. Ablation studies further verify that structure-preserving density modeling and the adaptive density update mechanism provide complementary improvements in placement quality and convergence.

ABSTRACT. Global placement is a fundamental stage of VLSI physical design that determines the locations of circuit instances under competing objectives, primarily wirelength minimization and density control. State-of-the-art global placers are analytical methods that achieve strong scalability and solution quality by optimizing a multi-objective formulation balancing these factors. However, their optimization behavior is still largely driven by globally shared weighting schemes, which cannot fully capture the heterogeneous local needs of individual cells during placement. This design choice is largely motivated by the fact that explicitly incorporating richer local optimization behavior into mathematical formulations often incurs prohibitive complexity and compromises scalability. To address this limitation, we propose CLAW (Cell-wise Learning-guided Adaptive Weighting), the first learning-based adaptive weighting method for analytical placement that enables online, per-cell, context-aware optimization decisions. A key strength of CLAW is its practicality: with lightweight training requirements, it can be easily integrated into an existing analytical placement framework without redesigning the underlying optimizer. Our method is built on a hybrid per-cell representation that combines node-level geometric, connectivity, optimization-state, and short-horizon temporal features with multi-scale local spatial patches to characterize each cell's local placement context. We further develop an improvable-node selection method to identify cells most likely to benefit from adaptive weighting, and a generalizable offline learning framework, including training data generation, label construction, and supervised learning, to make the proposed method practically trainable. Experimental results show that CLAW substantially strengthens a strong analytical placer and achieves significantly better wirelength than state-of-the-art placers.

ABSTRACT. Rapid Single Flux Quantum (RSFQ) logic can operate at ultra-high clock frequencies; however, its physical design is complicated by explicit splitter trees and deep gate-level pipelines in which every logic gate is clocked. To address this challenge, we present qLevelPlace, a level-based placement framework for RSFQ circuits. We separate gate and splitter placement into two stages to better support level-guided gate-to-row assignment and use a timing-aware quadratic cost function to penalize long interconnects. Experiments on the benchmark circuits show that, on average, qLevelPlace achieves a 2.65$\times$ higher clock frequency and a 51\% reduction in layout area compared with the state-of-the-art RSFQ placer qPlace.

ABSTRACT. A circuit design mixing standard cells of two track heights, such as 8-track and 12-track cells, can provide drive strength where timing requires it while avoiding the area and power cost elsewhere. Because the two heights cannot share a common row grid, existing flows decide cell heights either before placement or after it on frozen positions, and placement itself never shapes the height decision. To address this limitation, we propose ALTO (Analytical Track-height Optimization), which forms the height partition during analytical global placement, rather than before or after it. Slack-driven seeding grows height fields at row granularity inside a GPU accelerated placement engine, legalization converts them into a manufacturable band partition, and a metered repair pass completes timing closure and re-verifies it on the final legal positions. Experimental results on an industrial 28 nm FD-SOI platform, across four designs, show that when placement ignores heights, critical cells scatter without regard to where tall rows can form. Deciding heights after placement therefore hands the shared repair engine a total negative slack pinned at the all-8T netlist deficit, up to 54.5× beyond ALTO’s hand-off, and spends up to twice the repair rows to reach the same closure. When the height budget is capped, this gap becomes a frequency deficit. At the budget where ALTO closes on every seed, the frozen regime still misses, with row promotion alone and even with drive substitution added, and it needs 1.75 to 2× that budget to close. Routed to signoff through per-band power domains, the joint layout stays clean on signal wiring and keeps a 25 percent frequency advantage over an all-8T control.

ABSTRACT. Modern standard cell libraries implement complex cells, such as multi-bit flip-flops, as multi-row cells. Because such a cell spans several rows and carries many pins, its placement largely determines the half-perimeter wirelength (HPWL) of its region. Yet conventional legalizers place multi-row cells by minimum displacement---blind to wirelength, as equal-displacement seats can differ widely in HPWL---and detailed placers keep them fixed, leaving their wirelength-optimal positions unexplored. In this paper, we propose a detailed placement methodology for finding the wirelength-optimal placement of multi-row cells. In the legalization stage, we propose HSEAT (HPWL-aware seating), which prices each candidate seat of a multi-row cell by its exact HPWL change. In the detailed-placement stage, we propose ISWL (independent-set windowed wirelength optimization), which relocates non-interacting multi-row cells to their wirelength-optimal positions in parallel by windowed moves. Experimental results on ICCAD-2017 mixed-cell-height benchmarks show that our flow reduces HPWL over the detailed placers of OpenROAD and DREAMPlace by 8.1% and 5.0% on average, respectively.

ABSTRACT. As semiconductor manufacturing advances toward sub-2nm nodes, local place-and-route (P\&R) design-rule violation (DRV) fixing is increasingly limited by complex rule interactions, dense multi-layer routing geometries, and foundry-specific constraints. While Large Language Models (LLMs) have recently demonstrated strong capabilities in EDA scripting and documentation, their application to \emph{visual} layout understanding remains largely unexplored: diagnosing DRC violations from layout imagery demands precise geometric reasoning and foundry-specific rule knowledge absent from general-purpose VLM training.

In this paper, we propose \emph{SCALE}, a framework with a self-supervised layout-generation stage for local DRV fixing at advanced nodes. Multi-layer layout geometry is serialized into structured text, and a fine-tuned language model learns to reconstruct randomly masked polygons from surrounding BEOL context alone without violation labels. At inference, natural-language rule constraints and high-temperature sampling steer generation toward diverse, violation-prone layout variants validated by an industrial signoff DRC checker, producing DRC-annotated layout--violation pairs used to fine-tune a domain-adapted DRC-VLM. This VLM provides rule-aware geometric guidance for local DRV repair, boosting state-of-the-art agents' solve rates by +12--25\% (up to 97\%) on 100 real sub-2\,nm cases spanning enclosure, spacing, width, and color-spacing violations.

ABSTRACT. Emerging edge AI workloads increasingly require arithmetic units that can trade computational accuracy for efficiency on demand. However, existing approximate arithmetic circuits are typically fixed-accuracy or rely on predefined structures for runtime configurability. This work introduces CircuitsDNA, an evolutionary framework that automatically evolves accuracy-configurable arithmetic circuits supporting multiple accuracy modes within a single circuit. It integrates three key features: 1) multi-threshold verifiability miter to enforce mode-specific accuracy requirements, 2) resource-limited verifiability-driven search to reduce verification overhead without sacrificing correctness, enabling efficient exploration of large circuit design, and 3) feedback-driven adaptive mutation to prioritize effective structural modifications and accelerate search convergence. Experimental results show that the 8-bit multiplier variants synthesized in 28-nm CMOS reduce the area–power product by up to 56% on INT8 DNN traces and 93% under exhaustive activity, compared with an exact 8-bit multiplier. Across CNNs and DeiTs, the accuracy loss relative to FP32 remains below 2% after fine-tuning under worst-case error (WCE) budgets of less than or equal to 1%. CircuitsDNA eliminates all search stalls observed in conventional methods across 8/12/16-bit multipliers, while adaptive mutation provides up to 1.33 times faster convergence than its non-adaptive counterpart.

ABSTRACT. Finite-state-machine (FSM)-based stochastic computing (SC) implements nonlinear functions using compact state-transition logic and state-indexed Bernoulli readout. Existing synthesis methods optimize the FSM parameter and conditional-probability-table (CPT) weights using an ideal steady-state Markov-chain model. However, result produced by the actual hardware can deviate from this model because the finite RNG sequences and their temporal ordering affect both the empirical state visitation frequencies and the Bernoulli readout. This paper presents \texttt{REASON}, a synthesis framework that decomposes the deviation into steady-state fitting error, finite-length state visitation error, and Bernoulli sampling error. For a prescribed FSM transition diagram and candidate RNG configurations, \texttt{REASON} profiles the finite trajectory of the FSM and the Bernoulli readout, and optimizes the transition parameter and CPT weights as per the profiling results by minimizing the errors. For bit widths ranging from 6 to 12, \texttt{REASON} reduces the average RMSE across eight nonlinear functions by 10.4--51.6\%, 53.2--72.9\%, and 79.3--84.8\% with one, two, and four input segments, respectively, compared with the state-of-the-art synthesis method, with particularly pronounced improvements at lower bit widths. At a sequence length of $L=256$, \texttt{REASON} further reduces area by 26.60\%, 21.43\%, and 15.09\% and power by 13.90\%, 11.07\%, and 7.78\% for one, two, and four input segments, respectively, compared with the state-of-the-art design.

ABSTRACT. Content-addressable memory (CAM) is widely used to accelerate associative search in hyperdimensional computing (HDC). Conventional bit-wise CAM implementations incur high search energy and substantial peripheral accumulation overhead. With compact bitcells and near-zero standby power, magnetic random access memory (MRAM) provides an attractive foundation for dense and low-power CAM. To further reduce search and accumulation energy, this paper proposes an MRAM-based approximate CAM. Each group of three query–storage bit comparisons is jointly sensed to produce a single binary result, reducing both sensing outputs and counter updates. A two-pass adaptive refinement scheme is introduced to preserve search accuracy. Simulations in a 28 nm CMOS process show that the proposed CAM design achieves 2.97 fJ/bit search energy and the sensing amplifier exhibits a worst-case error rate of 0.6%. Transistor-level pre-layout simulations indicate that the counter energy is reduced by 55.00%–64.71% compared with bit-wise accumulation, while the mean absolute accuracy difference from exact Hamming distance search is limited to 0.16 pp.

ABSTRACT. Error-tolerant applications, such as multimedia processing, machine learning, signal processing, and scientific computing can still produce satisfactory results under approximate computation. Approximate computing (AxC) is a well-established paradigm that improves efficiency by judiciously reducing computation quality, and has been widely applied to arithmetic circuits by modifying their logic behavior. However, depending on the approximation, arithmetic properties, such as commutativity, may no longer hold, causing error accumulation and making the output depend on the operand order. In this work, we show that controlling operand order in non-commutative approximate circuits can significantly reduce computational errors. We propose SWAPPER, a lightweight approach that drastically reduces approximation error by dynamically reordering input operands using only a single bit for the decision. To identify the most effective bit for swapping, we propose a framework applicable at different granularities, achieving large error reductions and significant accuracy gains. We evaluate SWAPPER at both component and application levels: at the component level, it reduces the mean absolute error by up to 50%, and at the application level it achieves up to 90% error reduction for AxBench suite and 66.7% top-1 improvement on a Vision Transformer.

ABSTRACT. Approximate circuits offer a compelling trade-off between functional accuracy and power-performance-area (PPA), which is especially attractive for edge intelligence and signal-processing workloads. However, existing AI-driven RTL generation frameworks are largely designed for exact hardware and do not explicitly support user-specified error budgets in approximate RTL design. We present \textbf{AX-AGENT}, a contract-driven multi-agent framework that translates natural-language specifications---including explicit error tolerances and PPA objectives---into high-quality approximate RTL. AX-AGENT consists of a Parser agent that formalizes user intent into a persistent error--PPA contract, a knowledge-guided Planner agent that determines block-level approximation strategies, a Generator agent that produces Verilog RTL, and a Critic agent that evaluates simulation and synthesis results and dispatches differentiated refinement actions. Through tool-in-the-loop refinement, the Critic guides targeted micro-adjustments that recover accuracy at minimal PPA cost. We further establish a three-axis evaluation protocol covering validity, quality, and robustness. We evaluate AX-AGENT on four representative circuit families: approximate adders, approximate multipliers, approximate mac units, and approximate processing elements (PEs). Experimental results show that AX-AGENT consistently improves contract satisfaction over iterative direct-generation baselines and identifies superior error--PPA trade-offs among valid designs. These results demonstrate that approximate RTL generation is better treated as a contract-driven closed-loop design automation problem rather than unconstrained code synthesis.

ABSTRACT. Matrix computing is a key computational primitive in modern digital systems, but exact arithmetic datapaths often incur substantial hardware cost. Approximate computing provides an attractive alternative by trading arithmetic accuracy for implementation efficiency; however, unit-level error metrics are insufficient to predict matrix-level quality degradation, while repeated Monte-Carlo simulation is prohibitively expensive. This paper presents MATE, a model-assisted area--quality trade-off exploration framework for approximate matrix computing. MATE first constructs a lookup-table-based arithmetic-unit library that captures statistical error characteristics and area costs of approximate adders and multipliers. It then represents matrix computations as dataflow graphs and estimates matrix-level approximate-computing quality through statistics propagation. Based on this model, MATE performs quality-constrained exploration to identify Pareto-efficient approximate datapath configurations. Experimental results on accumulator, matrix-vector multiplication, and MMSE channel-equalization workloads show that MATE provides high-fidelity quality estimation with more than 92% agreement with Monte-Carlo simulation, while achieving up to 261.76× evaluation speedup and enabling more than 20% area reduction under controllable application-level quality loss.

ABSTRACT. Complex non-idealities in analog compute-in-memory (CIM) systems make accurate noise modeling essential for predicting inference behavior and guiding hardware design. However, existing physical and statistical approaches either incur high modeling costs or rely on simplified assumptions, while lacking a unified theoretical view of how different non-idealities affect computation fidelity. To address this limitation, we propose InfoCIM, an information-theoretic framework that formulates analog CIM computation as a noisy communication channel. InfoCIM decomposes the channel into deterministic nonlinear distortion, multiplicative cell variation, additive inference noise, and quantization effects, and characterizes their information loss using the data processing inequality. We further derive an analytical mutual-information bound and use it to guide the selection of output scaling-factor granularity and ADC readout bit-width under the analog noise floor. Experiments on an eFlash CIM-SoC platform show that InfoCIM achieves high fidelity to measured on-chip outputs across representative CNN and Transformer workloads, with cosine similarity up to 0.984 and prediction agreement up to 97.62%. Further results validate the noise-source analysis and the predicted saturation trends of output scaling-factor granularity and ADC resolution.

ABSTRACT. Prior art introduced programmable DRAM-based near-bank Processing Units (PUs) whereby execution is triggered by host CPUs via dedicated memory commands. This host-driven model implies significant run-time overhead for host/PU synchronization barriers: mode transitions and ordering fences. In this work, we show that these synchronization costs dominate run-time: mode-transition barriers alone account for up to 95–99% of PU time in matrix-vector multiplication. To address this challenge, we present a Polygeist/MLIR compiler pipeline that, while automatically lowering C kernels to host and PU binaries, employs IR transformations to reduce both the frequency and the cost of synchronization barriers. Relative to unoptimized lowering in DDR4-based PUs, optimized compute-near-memory code reduces device execution time by 5.5–9.2× for kernels with data reuse and by 25–32× for kernels without data reuse. Finally, we perform a factorial sensitivity analysis to quantify the contribution and interaction of each proposed optimization.

ABSTRACT. Generating efficient code for near-bank DRAM-PIM remains challenging due to architectural constraints such as limited communication among SIMD lanes and nonuniform memory access latency. Because row activations are a major source of DRAM access latency and energy, accurately estimating their count is essential for compiler-level optimization. This paper presents DRAC, a polyhedral-model-based static analysis that exactly counts DRAM row activations for affine loop nests under a given PIM mapping. DRAC uses Presburger arithmetic over the polyhedral representation of loop nests to support various loops and array layouts, while modeling PIM-specific SIMD execution and multi-buffer allocation through source-level loop transformations. Across VADD, GEMV, and GEMM, DRAC matches cycle-accurate simulation in all evaluated cases and achieves 2~4 orders of magnitude speedup. Our experiments further show that optimizing loop orders, multi-buffer allocation, and array layouts can change row activations by up to 3.18x in GEMM, with similar latency and energy differences. DRAC therefore provides a fast first-stage cost model for PIM compiler optimization.

ABSTRACT. Autoregressive decoding in large language models (LLMs) is fundamentally memory-bandwidth bound: at every generation step the decoder must stream the complete key–value (KV) cache from high-bandwidth memory (HBM), saturating available bandwidth long before arithmetic units saturate. This bottleneck is especially severe on FPGA accelerators, whose HBM bandwidth (≤460 GB/s on Xilinx Alveo U280) is an order of magnitude lower than flagship GPU platforms, while their rich on-chip SRAM hierarchy (≈52 MB at >2.5 TB/s) remains largely underutilized for KV storage in current designs. We present LiM-KVS, a co-designed scheduling substrate and hardware architecture embodying the principle “fewer KV entries loaded is more throughput delivered.” LiM-KVS is grounded in a key empirical and theoretical observation: across diverse generation tasks, fewer than 20% of context positions carry more than 85% of cumulative attention mass—a concentration that is both measurable online via lightweight attention-weight accumulators and exploitable architecturally, since an FPGA dataflow pipeline can predicate individual HBM reads at cache-line granularity (the “decide-before-fetch” model), unlike GPU kernels that must stage full K/V tensors before any sparse masking. LiM-KVS comprises three tightly integrated components. First, the Attention-Score Importance Tracker (ASIT), a streaming on-chip accumulator that maintains per-position exponentially smoothed importance scores in 4 KB of BRAM with negligible area overhead, updated fully in parallel with each decode step’s residual computation. Second, the Selective Eviction Policy (SEP), a budget-constrained four-tier assignment—pinned (top-k by score in BRAM/URAM), hot (FP16 in HBM), cold (INT4 in HBM), and evicted—guided by a formal Pareto objective whose greedy top-k solution is provably optimal under a uniform matroid formulation. Third, the Bandwidth-Aware Block Scheduler (BABS), an HBM pseudo-channel allocator that distributes retained blocks uniformly across 32 channels (raising effective bandwidth utilization from 42% to 91% of peak), batches requests with overlapping hot sets to amortize BRAM refill cost, and pipelines cold-tier prefetch into otherwise idle pipeline bubbles between attention layers. Evaluated on the Xilinx Alveo U280 across LLaMA-2-7B/13B, OPT-6.7B, and Mistral-7B, LiM-KVS reduces effective HBM traffic by 2.9× and improves decode throughput by 2.33× over a full-KV FPGA baseline at sequence length T = 2048. Energy efficiency (tokens per joule) surpasses FP16 NVIDIA A100 near T ≈ 8K and reaches 4.1× at T = 32K. The largest gains occur when KV cache offloading to CPU memory becomes necessary on GPU systems (e.g., via vLLM), where throughput becomes PCIe-bound beyond T > 16K. Quality degradation remains minimal, with at most 0.31 perplexity increase on WikiText-2 and 0.5% accuracy drop on MMLU at compression ratio r = 0.40.

ABSTRACT. On-orbit large language model (LLM) inference is emerging as a promising capability for autonomous on-board data processing. However, deploying LLMs in space requires balancing radiation resilience against tightly constrained storage and protection resources. Uniformly retaining high precision and fully protecting all model states is therefore impractical, making selective protection necessary. The challenge is deciding which model objects should be protected and at what granularity under a fixed resource budget. A nominal bit-error rate alone is insufficient for this decision because the inference consequence of an error depends on the persistence of the corrupted state, its reuse during autoregressive inference, and the numerical and propagation scope of the data representation. Moreover, precision selection changes both the exposed fault space and the cost and effectiveness of protection. These coupled effects motivate formulating radiation-aware LLM protection as an object-level cross-layer resource-allocation problem.

We present Radiation-Aware Selective Protection for LLMs (RASP-LLM), a precision-aware design-space exploration framework for this problem. RASP-LLM first selects a mixed-precision assignment to reduce the model footprint under the on-board memory constraint. The resulting precision assignment is then carried into radiation-aware characterization because it changes the number of exposed storage bits, the numerical significance of corrupted bits, and the failure domain of shared metadata. To avoid exhaustive fault injection over all model objects and operating conditions, RASP-LLM uses hierarchical coarse-to-fine profiling to identify the global vulnerability structure and selectively refine candidate high-risk objects. The characterized object risks are combined with precision-dependent storage costs and candidate protection actions to derive non-dominated protection policies.

Across Qwen2.5-7B-Instruct and Llama-3.1-8B-Instruct, weight vulnerability consistently concentrates in the MLP projections, while RASP-LLM retains over 95% of the maximum characterized protection benefit with 64.1%-88.1% less additional ECC storage than uniform full protection. End-to-end full-MMLU validation further shows 96.5% accuracy-loss recovery in a high-impact Qwen static-fault case.

ABSTRACT. Cascaded speech-to-speech (S2S) pipelines suffer from a structural latency bottleneck because LLM inference begins only after end-of- utterance detection, leaving compute idle during user speech. We propose PICO, a runtime orchestration framework for cascaded S2S to reduce perceived latency. PICO is built upon three key mecha- nisms, Lookahead-Prefill, which builds the LLM KV cache from par- tial ASR hypotheses during user speech; Incremental Cache Recovery, which retains the longest valid cache prefix under ASR corrections; and Bounded-band Admission Control, which limits speculative de- coding and synthesis ahead of playback. On an NVIDIA Jetson Orin Nano and an RTX 4060 Ti, PICO reduces post-utterance LLM la- tency by up to 95% and 97%, respectively, and time-to-first-audio by up to 47%. Incremental recovery reduces correction-repair cost by up to 80%, while admission control reduces speculative lead by over 5× without increasing first-audio latency or introducing playback gaps.

ABSTRACT. Thermal management is a critical challenge in 3D IC design, where vertically stacked active layers significantly increase power density with prolonged heat dissipation paths. Prior thermal-aware placement redistributes heat sources but assumes fixed thermal conductance, while thermal via insertion adds heat paths yet relies on greedy or heuristic search, and both repeatedly re-solve the thermal network, incurring significant computational overhead. We propose \textbf{DiffTherm}, a differentiable thermal formulation enabling gradient-based cell-via co-optimization for 3D ICs at the standard-cell scale. The key idea is to solve the thermal network with a GPU-accelerated CG solver and derive both cell-movement and via-insertion gradients from a shared adjoint sensitivity vector \lambda. This naturally captures nonlinear via effects (per-via effectiveness, lateral blockage, inter-via interaction) through the conductance structure. Our CG solver achieves a 254x average speedup over PACT with a maximum error of 0.002 K. Across M3D and F2F benchmarks, DiffTherm reduces post-legalization peak temperature by up to 14.1K with 4.6mK/via average efficiency, while incurring only 7.1% average HPWL overhead and preserving post-route PPA. To the best of our knowledge, this is the first analytical via-insertion gradient, turning a long-standing heuristic problem into a gradient-based optimization.

ABSTRACT. Fast and accurate transient thermal simulation is essential to thermal reliability analysis and dynamic thermal management of advanced packages, and model order reduction (MOR) techniques are widely applied to overcome the efficiency bottleneck of rigorous numerical methods. However, nonlinear terms including temperature-dependent leakage power, thermal conductivity, and heat capacity prevent the application of conventional linear MOR, while hyper-reduction solutions require costly nonlinear training data. In this work, we propose SPLIT-MOR (Subdomain-wise Piecewise Linearization with Interval Tensors), a novel nonlinear MOR method that requires no additional training set. SPLIT-MOR computes reduced component tensors by subdomain clustering and temperature-interval partitioning in the offline stage, and updates the reduced coefficient matrices and load vectors efficiently in the online stage. Experimental results show that the online solving time of SPLIT-MOR achieves up to an 830x speedup over COMSOL and a 7.5x speedup over the state-of-the-art hyper-reduction method MDEIM, with a 27x total reduction in the offline time. The relative average error remains below 0.11%, and the maximum error is below 0.86 ℃, demonstrating the high accuracy of our method.

ABSTRACT. Runtime thermal management requires dense temperature and power maps to localize hotspots and identify dominant power sources, yet neither is directly observable post-silicon: sensing is sparse, and thermal diffusion suppresses the fine spatial structure of the heat-source distribution. We present SiliDiff, a cascaded conditional diffusion framework that reconstructs both full-chip maps from sparse thermal sensors, performance counters, and floorplan information. Stage 1 reconstructs the temperature map, and Stage 2 reconstructs the power map conditioned on the Stage 1 estimate. Stage-specific conditioning is applied during inference. The stages are trained independently, while noise conditioning augmentation improves robustness to reconstruction errors. With 16 sensors (1.56% tile coverage), SiliDiff achieves mean absolute error (MAE) values of 0.21 K and 0.51 W/cm² against simulation-derived ground truth. SiliDiff also provides per-tile uncertainty maps, reuses architecture-specific models across floorplan variants, and remains effective across CPU architectures. A source-aware throttling study further shows how the reconstructed temperature map localizes thermally critical regions and the reconstructed power map prioritizes dominant power sources for targeted control.

ABSTRACT. Modern advanced-node IC design exhibits highly nonlinear and non-monotonic temperature-delay behavior, especially under low supply voltage where temperature inversion becomes prominent. Such effects significantly increase timing variability across thermal conditions, making single-temperature static timing analysis and corner-doubling method used in current practice insufficient for ensuring timing closure. To address these limitations, this work proposes the first gradient-guided thermal-aware timing robustness optimization framework performed after clock tree synthesis. We explicitly minimize timing variation across multiple thermal conditions rather than assuming a known operating temperature condition for optimization. To achieve this, our key idea is to manipulate the permissible range of thermal-aware clock skew. Thermal sensitivity tuning performs differentiable, gradient-guided clock cell sizing to shift thermally-variant clock skew towards the permissible range. Skew margin adjustment further buffers data path to adjust permissible skew bounds and ensure robustness against temperature-dependent delay shifts. Experimental results on both academic and industrial benchmarks demonstrate substantial improvements in hold-time robustness, with consistent reduction in worst negative slack (WNS), total negative slack (TNS), and number of violating paths (NVP) across diverse thermal conditions, while perserving setup-time performance and cost-effective ECO efforts. These results confirm that the proposed method provides a general and efficient solution for robust timing closure under temperature inversion, without requiring thermal-map-specific optimizations.

ABSTRACT. Three-dimensional analog compute-in-memory (CIM) improves integration density by stacking an analog memory die over a logic die, but vertical thermal coupling creates spatially non-uniform temperatures across the CIM array. The resulting state- and temperature-dependent conductance drift introduces inference errors that cannot be fully mitigated by fixed encoding or chip-wide compensation. This paper proposes STRIDE, a sparse thermal reconstruction-informed differential encoding framework for thermally stable 3D eFlash CIM. STRIDE reconstructs and partitions the temperature field using sparse on-chip thermal sensors while exploiting encoding redundancy, which allows the same differential weight to be represented by multiple equivalent state pairs. By jointly considering thermal drift and magnitude-dependent cell variation, STRIDE selects suitable differential state pairs for different weights and thermal regions. The encoding is optimized offline, and reprogramming is performed only after a significant and persistent change in operating temperature. On-chip experiments on a 3D eFlash CIM SoC show that STRIDE outperforms existing compensation methods, improving vision-model accuracy by up to 1.56 percentage points and reducing LLM perplexity by up to 3.75%. Further on-chip tests in a temperature-controlled chamber show that, over the temperature range from −25°C to 85°C, STRIDE achieves up to a 5.20-percentage-point accuracy improvement and an 8.40% perplexity reduction.

ABSTRACT. Integrating heterogeneous materials in advanced integrated circuit packaging exacerbates thermal stress and warpage caused by coefficient of thermal expansion mismatches. While the finite element method (FEM) offers high accuracy, its computational cost remains prohibitively high for large-scale packaging structures with complex geometries and diverse materials.

To overcome this bottleneck, we propose ThTrace, a highly efficient global displacement-field simulator based on the finite difference method. ThTrace ensures physical conservation and scalable performance by establishing equivalent material properties for heterogeneous interfaces and employing a preconditioned iterative solver, LGMRES with aggregation AMG.

Compared to commercial FEM software, ThTrace delivers an overall speedup of over 22.46×, comprising a 344× acceleration in meshing and an 19.05×acceleration in solving, while requiring only 28.08% of the memory usage. Meanwhile, the root mean square error and mean absolute error of the displacement field remain below 1.28 𝜇m and 1.24 𝜇m, respectively, and the relative error in the peak displacement is less than 2.98%. When applied to thermal warpage analysis, the relative error remains below 2.17%.

ABSTRACT. Hardware security verification is a challenging aspect of chip development. Many of the available tools and methods require expertise to use. Furthermore, their setup involves significant manual effort, limiting their use in early verification. In this work, we propose an open-source framework that uses heuristics and graph-based static analysis to find hardware security weaknesses within a design. Our solution works out of the box without design-specific setup; it runs on just the source code with no simulation or compilation required. We analyze the efficacy of our proposed approach using 23 buggy benchmark designs (those established in prior work and more, which span across three CWEs). Our framework finds all 23 bugs. In comparison, prior work discovers fewer than half of the bugs (even under ideal settings). We also examine how generalizable our heuristic approach is across different coding styles, using 36 different open-source designs.

ABSTRACT. Transient-execution vulnerabilities represent a critical concern in processor security, as mispredicted control flow can perturb the state of the branch prediction unit (BPU) and leave observable traces. Existing pre-silicon validation tools make sub-optimal utilization of limited RTL simulation testcases, as they lack pre-simulation control-flow filtering, controlled construction of branch-predictor conflicts, and feedback mechanisms for ordered predictor-state transitions. To address these limitations, we present PARFuzzer, a path-aware RTL fuzzing framework designed for branch transient-execution validation on RISC-V processors. Prior to simulation, PARFuzzer first filters redundant control-flow patterns using normalized Control Flow Graph (CFG) signatures. It then injects 4 KB-aligned attacker/victim branch layouts to deterministically induce complex cross-PC Branch Target Buffer (BTB) aliasing. It further encodes ordered BTB/meta events as micro-execution paths and ranks input seeds based on coverage gain, micro-path novelty, and freshness. We evaluated PARFuzzer on BOOM v3 with 80,000 testcases. Experimental results indicate that PARFuzzer improves microarchitectural coverage by 33.4% and micro-execution path diversity by 11.1% over the state of the art. Crucially, it detects 2.95x more RTL trace-level trigger candidates and additionally identifies 1,890 Alias_BTB structural candidates.

ABSTRACT. Hardware Trojans inserted at the register-transfer level (RTL) threaten the integrated circuit supply chain, so practical localization methods must generalize to unseen circuit families. Most graph neural network (GNN) detectors are evaluated with same-family circuits present in the training set.Their precision collapses under leave-one-family-out (LOFO) evaluation, with false positives (FPs) on benign datapath and protocol logic. To our knowledge, we are the first to show that message passing creates Trojan-like representations for these FPs, so precision cannot be recovered from topology alone.We therefore propose DISSECT: a relational GNN over the relational data-flow graph (R-DFG) gives each node a structural prediction. A large language model (LLM) uses RTL context to assess whether each node’s behavior is explained by the design’s primary function. When the GNN and the LLM agree on a node, the node's label is decided directly. A disagreement node is labeled Trojan only when RTL and R-DFG evidence shows that the node produces a malicious effect or reaches a payload. Under the LOFO protocol on 77 designs from four families, DISSECT reaches a node-level F1 of 0.942 (precision 0.937, recall 0.963), versus an F1 of 0.240–0.370 for structural baselines.

ABSTRACT. As reliance on third-party IP cores and outsourced design flows increases, recovering finite-state machine (FSM) mod- els plays an important role in trust validation, reverse engineering, and security analysis....

ABSTRACT. Graph neural networks (GNNs) are promising for hardware Trojan detection, yet their robustness under logic-preserving resynthesis remains insufficiently characterized. We introduce LPRT-GNN, a resynthesis-aware evaluation framework for gate-level Trojan analysis. Clean ISCAS85/EPFL circuits and Trojan-injected variants are normalized, transformed with Yosys/ABC resynthesis flows, and represented as typed netlist graphs with node, edge, and global features. We jointly evaluate Trojan classification and functional similarity retrieval under benchmark-held-out, resynthesis-held-out, and custom retrieval protocols to expose synthesis-induced distribution shifts. Ten GNN backbones are compared with structural retrieval baselines. The results show that high classification accuracy alone does not guarantee function-preserving robustness, with best-case resynthesis-held-out classification accuracy of 93.02% and best learned retrieval R@1 of 0.9819.

ABSTRACT. Fuzzing has become a mainstream pre-silicon security verification technique with the emergence of open-source RISC-V processors. As the cornerstone of fuzzing, the balance of instruction generation has been a long-standing research question, in which diverse legal functionalities and the rejection of illegal instructions should be stressed. However, existing methods overlook the instruction encoding space's inherent hierarchy and spatial adjacency, resulting in inability to stress or misplaced uniformity of the illegal space.

In this paper, we argue that the bugs concentrate at the cracks where illegal encodings border legal ones. We propose an illegal instruction generation approach targeting these high-risk regions by modeling and exploring the unified binary encoding space. Our approach first systematically models the instruction space to reveal the characteristics of risk regions, establishing a foundation for tunable sampling. It then performs instruction generation based on this model, with illegal space calibration and weighted sampling. Finally, we implement the approach as a fuzzing tool portable across processors and ISA evolution. Evaluation on NeoRV32 and OpenXiangShan projects uncovers 7 new bugs, achieves 2.5× faster coverage convergence over RISCV-DV and seamlessly adapts to RVV without hand-crafting rules.

ABSTRACT. Placement guidance can help commercial placers improve timing closure, but effective guidance generation often requires manual analysis and design-specific tuning. This paper presents a training-free framework for automated timing-driven placement guidance generation. From the gate-level design after global placement and initial buffering, the framework preserves the original signal-net hypergraph and adds delay-weighted 2-pin pseudo nets to represent fine-grained timing-critical source-to-load relationships. It then estimates a design-dependent partition-count range from logical hierarchy information. Following industrial practice, five target counts are uniformly sampled from this range, and the corresponding partitioning jobs are run in parallel. For each partitioning result, candidate clusters are then filtered using timing stress, structural connectivity, and congestion estimates. Each selected cluster becomes a placement group, and the collection of placement groups forms the placement guidance. Experiments on four open-source and eleven industrial designs show average total negative slack (TNS) and worst negative slack (WNS) improvements of 22.3% and 10.5%, respectively, with negligible impact on wirelength, area, and power.

ABSTRACT. With scalable Laplacian solvers now available, the next frontier is to exploit them more effectively for high-quality hypergraph partitioning. In this work, we revisit spectral hypergraph partitioning from the perspective of spectral embedding geometry. Through a systematic analysis of spectral embeddings for both circuit hypergraphs and controlled synthetic (hyper)graphs, we identify a ray-like geometric structure that explains the effectiveness of projection-based partitioning. We further show that the geometry of spectral embeddings can be systematically influenced through Laplacian design and hyperedge reweighting. Guided by these insights, we propose FRESHPart, a feedback-reshaped spectral partitioning framework that refines the spectral embedding through Geometry Feedback and Search Feedback, producing embeddings that are better aligned with projection-based partitioning. On the Titan23 benchmark, FRESHPart achieves average cut reductions over hMETIS of 13.09% at 𝜖=2% and 25.21% at 𝜖=20%, surpassing the strongest previously reported results (12.16% and 22.53%, respectively), while completing every benchmark in under 120 s on a single GPU.

ABSTRACT. Hypergraph partitioning is fundamental to electronic design automation (EDA), where classical multilevel partitioners are limited by local heuristics. Two observations motivate this work: cut-overlay suggests that frequently cut nets provide structural priors for targeted improvement, and imbalance ratios expose different search flexibility for knowledge transfer across balance settings. We propose HyperCutNet, a learning-augmented framework that predicts balance-conditioned net-level cut probabilities instead of vertex assignments and uses them to guide TritonPart coarsening. To exploit partitioner diversity, we train models from KaHyPar, hMETIS, and TritonPart solution pools and fuse guided solutions through multi-model Cut-Overlay. Evaluated on ISPD98 and Titan23 test benchmarks under multiple balance constraints, HyperCutNet achieves the best average cutsize among KaHyPar, hMETIS, SpecPart, and TritonPart, improving over KaHyPar/hMETIS by 9.15%/3.96% on ISPD98 and 12.23%/7.85% on Titan23. Further analyses confirm cross-suite transferability, identify coarsening guidance and multi-model fusion as key contributors, and show a 28.4% runtime overhead over TritonPart.

ABSTRACT. Hypergraph partitioning sits on the critical path of VLSI design, and GPUs have finally made it fast: the state-of-the-art GPU partitioner, gHyPart, outruns multi-threaded CPU tools by an order of magnitude. We argue the next leap is hiding in an assumption every GPU partitioner inherited from its CPU ancestors--that one hyperedge or vertex per task. Real netlists span five orders of magnitude in hyperedge size, so under this schedule, one giant net dictates the critical path, thousands of threads collide on the same atomic counters, and most warp lanes simply wait.

RAP removes the assumption instead of fighting its symptoms. It dissolves the hypergraph into a single global stream of (hyperedge, vertex) pins and rebuilds the dominant subroutines---coarse-hypergraph construction GSC and FM gain evaluation SGE---as short pipelines of stable sort, prefix-sum, and run-length encoding over that stream. Skew vanishes by construction: a giant hyperedge is just more parallel entries. Atomics vanish by construction: every output address is computed before any store. Determinism comes for free: stable primitives on fixed keys make the result independent of thread timing, and RAP's partitions are bit-identical to gHyPart's, verified by cut and partition-hash equality. On 20 Titan23 and SAT14 designs, RAP runs 1.6 times faster end to end on average (up to 3.0 times) with stages accelerated by up to 21 times, and its advantage widens to 8 times on 20M-scale synthetic netlists---the larger the design, the more the schedule matters. Code and scripts are available at https://anonymous.4open.science/r/RAP-76AD.

ABSTRACT. Multi-FPGA prototyping is widely used to validate large-scale designs that exceed the capacity of a single FPGA. In this setting, conventional partitioners mainly optimize cutsize, but the achievable prototyping frequency is often limited by t he delay of timing-critical paths. This paper presents CCPart, a timing-aware multilevel partitioning framework with incremental timing analysis. During refinement, CCPart incrementally updates timing information under node moves and uses it to guide partition decisions. On top of this framework, we develop two refinement strategies: a max-hop-driven method that minimizes the maximum number of inter-FPGA crossings on timing paths, and a slack-based method for settings where inter-FPGA delays vary significantly across FPGA pairs under TDM assignment. Experiments on four real-world industrial designs show that the max-hop-driven method consistently achieves the lowest max-hop, while the slack-based method yields the best slack after TDM assignment on all heterogeneous-delay cases, with only 9%--21% cutsize overhead over a min-cut partitioner.

ABSTRACT. Analytical FPGA placers often begin without explicitly exploitingthe modular structure of the netlist, forcing early optimization torecover large-scale spatial organization. We propose a topology-guided placement framework whose core mechanism physicallyinstantiates a two-level netlist hierarchy as continuous initial coor-dinates. The hierarchy is placed as utilization-aware virtual clusterson a fixed-terminal-aware coarse hypergraph and reconstructed asnative primitive coordinates through controlled truncated-Rayleighscattering. No hard cluster region persists: original cells, resourcetypes, connectivity, and architectural constraints are restored beforecell-level optimization. An optional finite-horizon net-weightingmechanism preserves the structural prior during early placementand anneals back to the original objective. On ISPD 2016 benchmarks, the method reduces detailed-placement HPWL and routedwirelength by 3.63% and 3.46% relative to the matched DREAMPlaceFPGA+OpenPARF flow, while reducing end-to-end runtime by 15.9% and cell-level global-placement iterations by 55.95%. A six-seed full-flow study, rerunning the complete pipeline for each seed,yields suite-level mean gaps of −2.95%/−2.35% for HPWL/routedwirelength, with across-design standard deviations of 2.06%/1.80%.With a commercial placer on five proprietary designs, the same coordinate path reduces HPWL, end-to-end runtime, and global-placement iterations by 6.65%, 9.93%, and 44.71%, demonstrating cross-engine portability with all front-end overhead included.

ABSTRACT. Edge AI systems must deliver on-device inference under strict latency, energy, and memory constraints while adapting to dynamically varying resource budgets at runtime. Vision Transformers (ViTs) achieve state-of-the-art accuracy, but their fixed compute and memory demands hinder edge deployment. We propose SHARD, a sub-transformer harnessing framework that converts a \emph{pretrained} ViT into a hierarchy of nested sub-transformers for resource-aware adaptive inference. SHARD introduces \emph{Head-Aware Sharding}, which preserves all attention heads while proportionally scaling their embedding subspaces, maximizing parameter sharing without the accuracy degradation. A complementary \emph{Delta Runtime Manager} (DRM) enables low-overhead transitions between configurations via incremental parameter loading. On NVIDIA Jetson Orin, SHARD achieves up to \textbf{2$\times$ faster} inference and \textbf{65\% lower} energy per inference than existing approaches, while achieving a more favorable accuracy-FLOPs Pareto frontier. The source code will be made publicly available upon acceptance.

ABSTRACT. On-device learning is necessary when the model encounters user-, sensor-, or environment-specific shifts after deployment. Although parameter-efficient fine-tuning (PEFT) methods, particularly Low-Rank Adaptation (LoRA) variants, enable efficient adaptation at the edge, the limiting resource for Convolutional Neural Network (CNN) adaptation is often not the number of trainable parameters but the activation state that must be retained until the backward pass. This paper introduces Memory-Floor LoRA (MemFLoRA), a low-rank CNN adapter built around a memory-first design principle rather than a direct application of transformer-oriented LoRA. Instead of merely reducing trainable weights, we define an activation-memory-floor criterion: trainable backward computations must not depend on full-width layer inputs. The resulting adapter freezes the down-projection, trains a scale-matched up-projection, and combines eval-mode backbone normalization with activation-minimal backward rules, reducing saved state to the low-rank branch. Evaluated on three Human Activity Recognition (HAR) datasets and two CNN backbones under subject, body-location, and sensor-placement shifts, MemFLoRA reduces saved-activation memory by 98.5-98.7% and peak training-state memory by 94.9-97.3% relative to full fine-tuning, while matching or exceeding CNN PEFT baselines.

ABSTRACT. Reinforcement learning (RL) post-training improves the reasoning capabilities of large language models, but its cost is dominated by autoregressive rollout generation, which can exceed 70% of training time. Existing speculative-decoding methods are poorly suited to this setting: model-based drafters consume scarce GPU memory and may become misaligned as the policy evolves, while existing model-free methods do not explicitly exploit repetition across training epochs. We observe that recent rollouts of the same prompt provide a high-quality, self-updating draft source. Based on this insight, we propose NgramRL, a per-prompt n-gram drafter constructed from bounded recent rollout history. NgramRL requires no auxiliary model, drafter training, or persistent GPU-resident drafter state, while target-model verification preserves the rollout distribution. To hide CPU cache lookup and scheduling, we further introduce an adaptive fan-out prefetcher that predicts likely verification outcomes (j, b), consisting of the accepted draft length $j$ and target-emitted continuation token b. A causal budget allocator concentrates prefetches on high-probability outcomes, while uncovered outcomes fall back to sequential lookup without changing committed tokens. Across two model families and three reasoning and structured-generation workloads, NgramRL commits 3.60-7.77 tokens per target-model forward in the warm-cache regime, up to 1.99x more than SuffixDecoding and 7.0x more than prompt-lookup decoding. On Spider, the prefetcher covers 96.6% of Qwen3-8B outcomes at a candidate budget of 16 and improves measured rollout throughput by 1.38x over synchronous NgramRL, approaching its 1.40x overlap ceiling.

ABSTRACT. Vision-Language-Action (VLA) models enable end-to-end robot control, but inference is increasingly expensive: each decision processes hundreds of visual tokens, often across multiple cameras, leading to substantial computation while allowing irrelevant background content to distract action prediction under distribution shift. We argue that these issues stem from two complementary forms of redundancy: many visual tokens are spatially irrelevant, while attention over the remaining tokens is often misallocated. Based on this observation, we propose T3R, a Training-free Two-stage Token Refinement framework. In the first stage, segmentation-guided token pruning removes irrelevant visual patches to reduce computation and eliminate distracting context. In the second stage, saliency-guided attention biasing reallocates attention toward action-critical visual regions and language instructions within the retained tokens. Together, pruning produces a cleaner candidate set, while attention biasing further emphasizes the most decision-relevant evidence, yielding a better accuracy-efficiency frontier than either stage alone. On LIBERO, T3R removes 85% of visual tokens while matching the unpruned success rate, representing a 2.5x more aggressive reduction than prior training-free pruning methods, and further improves success by up to 7 percentage points under out-of-distribution object-placement perturbations. As input resolution increases, the computational benefits become increasingly pronounced: despite introducing only 7.8 ms of resolution-independent overhead, T3R achieves up to a 3.3x measured speedup in the LLM forward pass at 768px resolution while maintaining comparable task performance. The pruning strategy also generalizes beyond OpenVLA-OFT: on the three-camera RoboTwin benchmark with a π0.5 backbone, T3R is the only training-free method that consistently preserves the unpruned success rate under substantial token reduction. These results demonstrate that training-free token refinement is a practical, backbone-agnostic approach for improving both the efficiency and robustness of VLA inference.

ABSTRACT. Mixture-of-Experts (MoE) models are increasingly used in LLMs because sparse activation decouples model capacity from compute cost. However, the large expert parameter footprint often exceeds GPU memory capacity, making inference latency dominated by the host-to-device PCIe transfers for expert loading. To address these challenges, this paper presents SPICE, a speculative prefetching framework for MoE offloading that combines lightweight expert prediction with confidence-aware CPU-GPU orchestration. On one hand, SPICE builds a lightweight draft model aligned with the target MoE architecture, using a confidence-aware adaptive lookahead algorithm to prefetch high-confidence experts. On the other hand, when speculative predictions miss, SPICE switches to a cost-aware CPU-GPU heterogeneous orchestration: low-confidence misses are approximated by the resident shared expert with low-rank expert (LoRE) surrogates, while exact residual work is offloaded to the CPU and executed asynchronously in parallel with ongoing GPU computation. Evaluated on DeepSeek-V2-Lite and Qwen2-57B-A14B across diverse GPU platforms, SPICE achieves up to 3.12 times speedup in Time Per Output Token (TPOT) with minimal quality loss, showing that effective MoE offloading requires not only predicting future experts, but also deciding which misses deserve approximation, which require exact recovery, and where exact residual work should execute. Our code is available at https://anonymous.4open.science/r/SPICE.

ABSTRACT. Large language models (LLMs) have achieved remarkable performance across a wide range of NLP tasks. However, their substantial inference cost poses a major barrier to real-world deployment, especially in latency-sensitive scenarios. To address this challenge, we propose \textbf{MARCO}, a Markov decision-based adaptive path selection framework that dynamically determines computation routes conditioned on input characteristics. We model layer skipping as a Markov Decision Process (MDP), enabling fine-grained token-level decisions guided by intermediate representations. To mitigate potential performance degradation caused by skipping, we introduce a lightweight compensation mechanism that injects differential rewards into the decision policy. Furthermore, we design an asynchronous execution strategy that overlaps layer computation with policy evaluation, minimizing runtime overhead. Experiments on multiple LLM architectures and NLP benchmarks show that our method achieves significant inference acceleration while maintaining competitive task performance, outperforming existing methods.

ABSTRACT. Modern FPGA SoCs are no longer simply collections of accelerators on top of a programmable fabric. They combine programmable logic with hardened processors, networks-on-chip (NoCs), memory, and components that can dominate end-to-end performance. Evaluating individual components is insufficient; system performance depends on the complex interplay of components spread across the SoC. However, FPGA SoC simulation flows provide limited support for this style of evaluation. Vendor simulations capture these interactions but are prohibitively slow for iterative design-space exploration, while faster software models often abstract the hardware components that determine real behavior.

We present Naviq, an open-source, cycle-level software simulator for FPGA SoCs, tuned to AMD Versal-class architectures. Naviq bridges high-fidelity but slow vendor simulation and fast but overly abstract software modeling: it captures key behaviors of modern commercial FPGA SoC infrastructure while remaining fast enough for debugging and design-space exploration. Naviq models hardened SoC infrastructure in C++ and integrates user accelerators through Verilator, allowing designers to evaluate custom RTL in a full-system environment. At the center of Naviq is an AXI4-compliant NoC model that captures transaction ordering, packetization, routing, backpressure, and DDR/HBM interactions. Naviq provides CPU and memory integration, protocol checking, checkpointing, tracing, and performance-analysis tools for debugging and design-space exploration. Experimental results show that Naviq reproduces key bandwidth and latency behaviors of real Versal-class platforms while achieving orders of magnitude speedups over vendor RTL-based simulation. By combining calibrated platform fidelity, RTL integration, and open-source accessibility, Naviq enables practical full-system evaluation of modern FPGA SoC designs.

ABSTRACT. Efficient microarchitecture design space exploration (DSE) is critical for optimizing performance, power, and area trade-offs in modern out-of-order processors. While machine-learning-based DSE significantly reduces the cost of exhaustively evaluating large design spaces, existing methods still waste expensive simulations on Pareto-miss candidates that do not improve the Pareto frontier and repeatedly process redundant candidates during iterative exploration. In this paper, we propose PaFeDSE, a Pareto-feedback-guided microarchitecture DSE framework for efficient Pareto search. PaFeDSE leverages Pareto-hit feedback to prioritize candidates likely to improve the frontier and Pareto-miss feedback to suppress exploration of unpromising local regions, while filtering redundant candidates that remain low priority across iterations. Evaluated on SPEC CPU 2017 workloads, PaFeDSE requires up to 49.0% fewer simulations than the strongest prior baseline to reach target hypervolume levels, while achieving a 7.1x reduction in exploration overhead through adaptive candidate filtering.

ABSTRACT. To identify optimal solutions for application-specific processors, designers rely on tools to conduct early simulation-based design space exploration (DSE). While performance simulators can accurately predict a processor's performance by combining abstract functional descriptions with non-functional timing models, their comparatively slow runtimes make it infeasible to explore large-scale design spaces. This article presents the MAP-DSE simulator, especially designed to accelerate performance simulations for large-scale microarchitectural DSE. It contains a performance backend capable of evaluating thousands of microarchitecture variants during a single simulation while reducing unnecessary simulation overheads. In addition, it considers performance over blocks of consecutive instructions rather than per instruction, further increasing simulation speeds. Results for the state-of-the-art CV32E40P and CVA6 RISC-V processors show average simulation speeds of 580 and 66 million instructions per second (MIPS), respectively, corresponding to speed-ups of 40x and 7x over an established performance simulator, while producing identical performance predictions.

ABSTRACT. Modern GPU workloads, especially sequences of heterogeneous op- erator kernels, exhibit rare but severe slow phases caused by rapidly shifting resource contention. These microarchitectural tail phases, visible as the high-percentile region (e.g., P99) of the interval-level CPI distribution, are masked by mean-based modeling yet expose contention-driven performance cliffs that govern worst-case in- terval behavior and predictability. Because mean-centric design space exploration (DSE) optimizes only aggregate throughput, it can converge on configurations that look efficient on average but exhibit poor timing stability under transient contention. We propose ChronosDSE, a tail-phase-aware DSE framework for improving interval-level performance stability. Its key insight is that temporal stall-reason migration exposes tail susceptibility: stable bottlenecks indicate robustness, while frequent or severe shifts reveal tail risk. ChronosDSE captures this signal with Chronos- Signature, preserves transient CPI P99 through adaptive window sampling, and optimizes a stability-aware objective beyond mean CPI. On Vortex, ChronosDSE reduces interval-level CPI P99 by up to 24.1% and 10% on average, keeps mean CPI within roughly 2% of a mean-based baseline, and lowers exploration effort by about 58% versus exhaustive profiling. Its stall-centric design is largely ISA- independent, requiring only a consistent stall-taxonomy mapping.

ABSTRACT. Coarse-grained reconfigurable architectures (CGRAs) combine the performance and energy efficiency of domain-specific accelerators with the flexibility provided by instruction-level reconfiguration. However, current CGRA compilers have a narrow view of run-time performance, solely focusing on instruction-level metrics, and end-to-end latency also depends on architecture and technology considerations that are invisible at higher abstraction levels. Thus, we propose TAC-Co: a technology-architecture-compiler co-design flow with pipeline-aware compilation that delivers performance improvements by effectively utilizing hardware resources. At the technology level, TAC-Co explores frequency, leakage, and area trade-offs across ALU pipeline depths and standard-cell sets of different threshold voltages. At the architectural level, it parametrizes the pipeline depth of ALU operations on the critical path to optimize the maximum frequency. At the compiler level, it uses an end-to-end compilation flow for efficient mapping across pipeline depths by hiding multi-cycle operation latencies. Our results with compute-intensive kernels in the high-performance computing domain (FFT, convolution, and general matrix multiplication) in TSMC 16 nm show up to 3.56 GFLOP/s for a 4×4 CGRA running at 1.79 GHz. We obtain a 1.60× run-time improvement over pipeline-agnostic compiler-only exploration at a 3.0% area cost. Co-optimizing technology, architecture, and compiler exposes new and better Pareto cost/performance frontiers informing CGRA design choices.

ABSTRACT. Circuit simulation often produces extremely sparse and structurally near-symmetric matrices with many low-degree local connections and a few high-degree nodes. These structural characteristics strongly influence ordering, pivoting, and fill-in, making sparse LU factorization highly matrix-dependent in both performance and numerical robustness. Existing sparse LU solvers offer configurable strategies such as ordering, pivoting, and scaling, but their optimization remains confined to predefined algorithmic choices, making matrix-specific specialization difficult without expert effort. To address this challenge, we propose LU-Evolve, an agent-driven self-evolving framework that automatically specializes sparse LU solvers for a given matrix or matrix family. LU-Evolve treats sparse LU optimization not as fixed-parameter tuning, but as a validated algorithm-code evolution process. Rather than relying on autonomous LLM discovery, the framework injects matrix-specific insights and structured sparse-LU knowledge that map structural, numerical, and graph-topological characteristics to suitable algorithmic strategies and implementation priorities. This knowledge provides the agent with a reliable basis for targeted exploration. Guided by these insights, LU-Evolve adapts reordering, block decomposition, pivoting, scaling, and factorization strategies, and further evolves the corresponding implementation through an iterative compilation-and-validation loop. This system-level workflow explores beyond predefined solver parameters while filtering out incorrect or performance-regressive candidates. Experimental results on 12 representative sparse matrices show that LU-Evolve generates correct specialized solvers with lower fill-in and factorization cost than general-purpose baselines. For example, on one representative matrix, the evolved solver achieves consistent improvements over both KLU and SuperLU, reducing fill factor and factorization flops by 7.6% and 24.5% compared with KLU, and by 54.8% and 79.2% compared with SuperLU, respectively. On another matrix, it also improves over UMFPACK, reducing fill factor by 17.2% and factorization flops by 39.5%. These results demonstrate that verified agent evolution can effectively explore the algorithm-code space of sparse LU factorization and produce matrix-specific solver optimizations.

ABSTRACT. Printed circuit board (PCB) supply-chain authentication needs inexpensive physical fingerprints that can be inspected before a design is fabricated at scale. Electromagnetic (EM)-domain physical unclonable functions (PUFs) and radio-frequency (RF) fingerprints can derive entropy from microstrip geometry and fabrication variation, but their reported modeling resistance is easy to confound with encoding and train/test protocol choices. This paper presents EMPUF, an automated Ansys High Frequency Structure Simulator (HFSS) benchmark for side-coupled microstrip resonator PCB spectral fingerprints. EMPUF synthesizes tolerance-aware simulated populations with HFSS Optimetrics, extracts S11 spectral features, locks median thresholds on enrollment devices, and evaluates bit-index, design-only, metrology-assisted, learned-spectral, and white-box attackers under device-level splits. Across 100-instance HFSS populations with N=4,8,12, and 16, exploratory results show that attack conclusions depend strongly on access to device-specific information. In a predeclared N=8 split, bit-index/design-only, realized-geometry, and learned spectral attacks achieve 49.91%, 56.61%, and 75.71% accuracy, respectively. These results characterize simulated populations rather than deployment reliability.

ABSTRACT. Silicon-photonic transceivers are integrated as optical-I/O dies and chiplets, while photonic-die identity verification is increasingly important across fabrication, packaging, deployment, and field replacement. However, unauthorized replacement dies and malicious optical paths may lead to potential leakage of transmitted data; hence, photonic-die authentication before normal communication is highly demanded. This paper proposes an intrinsic microring PUF that reuses the microring resonator (MRR) array, per-ring photocurrent monitoring, and heater-control paths of a wavelength-division-multiplexed (WDM) transceiver. The fabrication-dependent untuned photocurrent of each MRR is normalized using a same-ring reference obtained through the existing heater-control loop, followed by fixed pairwise comparisons to generate the PUF response. The generated response can be used for boot-time photonic-die authentication, after which the same MRRs are aligned for normal WDM operation. This temporal reuse avoids the need for a dedicated photonic PUF array and an additional optical monitor or drop port. Lumerical-based Monte Carlo simulations show a mean Inter-HD of 49.96%, a reliability of 99.03% under a temperature shift from 27°C to 67°C, and a uniformity of 50.47%.

ABSTRACT. We propose a lightweight, key-based challenge response primitive for hardware device identity authentication, intended as a more reliable alternative to Physical Unclonable Functions (PUFs) for resource-constrained Internet-of-Things (IoT) and sensor devices. Instead of deriving a fingerprint from physical variation, the pro- posed scheme combines a fixed 256-bit internal identifier with a challenge response construction based on a signed accumulation and a shifted XOR function, which is then combined by multiplica- tion before being truncated to the sixth and seventh bits, so that any two parties sharing the identifier always agree on the response to a given challenge. This removes the need to store per device challenge response pairs (CRPs): the verifier holds only the identifier. As the response is fully deterministic, the scheme is free of the tempera- ture, voltage, and ageing induced unreliability that limits PUFs, and it can be replicated for redundancy in safety critical deployments. We evaluate its security conservatively: the construction resists first order statistical, single bit, various machine learning, and local search recovery attacks. The multiplication step raises the algebraic degree of the response map from one to two, and a bit exact SMT analysis bounds its confidentiality accordingly: the affine variant of the same datapath is recovered in seconds, whereas the deployed degree-2 map is recovered only at small key sizes and leaves the deployment size (𝑁 = 32) beyond a single solver budget in our experiments. The design occupies as few as 76 LUTs, 47 flip-flops, and 23 slices on an Xilinx Artix-7 FPGA which is lighter than the lightest CSPRNG evaluated and comparable to an equivalent CRO PUF making it attractive where reliability and footprint dominate.

ABSTRACT. Physical unclonable functions (PUFs) are increasingly used as lightweight hardware security primitives for edge-device authentication and key generation. For resource-constrained systems, magnetic tunnel junction (MTJ)-based PUFs are attractive because they provide compact entropy sources, low standby power, and nonvolatile state retention. In write-back-assisted MTJ PUFs, storing responses in complementary MTJ states improves readout reliability, but direct write-back may also establish a fixed correspondence between the written physical state and the enrolled response. Once the nonvolatile state is physically read out or replicated, this correspondence may expose response-related information. To mitigate this risk, this paper presents a reliability-enhanced SOT-MTJ PUF with obfuscated write-back. The proposed architecture uses in-cell cross-coupled positive feedback to pre-amplify MTJ resistance mismatch, an obfuscation-enabled precharge sense amplifier (OPCSA) to perform obfuscated full-swing readout, and the reused lateral SOT write path to write back encoded complementary states instead of raw responses. Circuit-level simulations show near-ideal uniqueness and uniformity, an average intra-HD of $0.630\%$, and no observed authentication errors after obfuscated write-back. These results indicate that the proposed design enhances reliable response reproduction while mitigating physical-state exposure in nonvolatile MTJ-based PUFs.

ABSTRACT. Oscillator-based Physically Unclonable Functions (PUFs), and particularly Ring-Oscillator PUFs, have proven to be vulnerable to side-channel analysis (SCA) due to spectral leakage associated with frequency measurement, necessary to construct the PUF response. In this work, three sampling strategies, including direct observation, pseudo-random gating, and deterministic flip-flop-based sampling, are proposed and implemented with the goal of mitigating power and electromagnetic leakage. Experimental results show a significant reduction in exploitable information in the frequency domain, as well as a decrease in the effectiveness of correlation-based attacks. Compared with a conventional RO-PUF implementation, the proposed techniques clearly attenuate the spectral components associated with oscillator activity and counter operations. In particular, the flip-flop-based sampling combined with pseudo-random digital nonlinear oscillators achieves the best overall performance, providing the highest reduction in both power and EM leakage while maintaining reliable and unique PUF responses.

ABSTRACT. Deep neural network (DNN) accelerators for edge inference must meet tight energy, latency, and area (EDP) budgets, and their best configuration is found through design space exploration (DSE) over the compute architecture and dataflow mapping. However, on-chip memory technology—including cell type, bank organization, and process node—is rarely treated as a first-class design variable during DSE, even though it strongly affects chip energy, performance, and area. For example, a larger-capacity memory can reduce accesses through higher data reuse but comes at the cost of greater area and access energy, limiting the budget for compute units. Therefore, memory technology can shift the optimal accelerator architecture for a given area and EDP budget.

Incorporating technology into existing ML-based DSE methods requires repeating simulation, data generation, and model training from scratch for each memory type. We present TADA, a memory technology-aware DNN accelerator performance and energy estimator that predicts system latency and energy for a given workload, hardware configuration, and memory technology. TADA is trained on a synthetic technology dataset to make it generalizable across memory technologies. The dataset represents nearly exhaustive current and diverse future technology trends while following physics-based guardrails that preserve realistic area–energy trade-offs. During training, we represent each memory technology using a technology signature—a vector of read energy, write energy, and storage capacity characterized across a range of areas—which is provided as input alongside the workload and hardware configuration.

On 21 unseen technology curves spanning SRAM, STT-RAM, ReRAM, PCM, FeFET, eDRAM, and CTT, TADA predicts system energy and latency within 1.5–4.4% and 0.7–1.2% MAPE, respectively. Across three pairwise case studies, it matches the simulator’s memory choice for 98.7–100% of area budgets, with a mean EDP loss of at most 0.21%, while providing a measured ~10⁴ speedup over analytical simulation.

ABSTRACT. Combinatorial optimization problems (COPs) are fundamental to many applications but remain computationally challenging. Existing solvers convert a COP into a quadratic unconstrained binary optimization (QUBO) form and map the QUBO matrix onto crossbar-based compute-in-memory (CiM) architectures to accelerate vector–matrix–vector (VMV) multiplication, followed by iterative algorithms such as simulated annealing (SA) for problem solving. However, these solvers ignore COP sparsity: only a small fraction (e.g., <5%) of elements in the 𝑛 × 𝑛 QUBO matrix are nonzero, yet a large crossbar array with an 𝑂(𝑛2) area complexity is required. This leads to 𝑂(𝑛2) computational complexity for VMV multiplication, with increased energy and time cost of the analog-to-digital (ADC) overhead, which fundamentally limits hardware scalability and problems solving efficiency. To address these challenges, we propose CAS, a ferroelectric based CiM annealer framework for solving sparse COPs. The framework includes: (i) a sparsity-aware vectorized formulation that computes local energy differences using only nonzero elements, reducing computational complexity from 𝑂(𝑛2) to 𝑂(𝑛𝑛𝑧/𝑛) and memory usage from 𝑂(𝑛2) to 𝑂(𝑛𝑛𝑧);(ii) a hybrid FeFET-based CiM architecture combining crossbar arrays for parallel vector–matrix operations with content addressable memory (CAM) arrays for efficient sparse index management and solution update; and (iii) an adaptive parallel simulated annealing (APSA) algorithm that dynamically adjusts candidate solution generation and parallel evaluation according to annealing temperature, effectively balancing exploration and exploitation. Evaluation on Max-Cut instances with 800–3000 nodes shows that CAS substantially reduces hardware overhead compared to two state-of-the-art annealers, achieving a maximum hardware area saving of 95.47%, with energy consumption and time cost reduced to as low as 2.71% and 14.41%, respectively. CAS also exhibits high solution efficiency, achieving a 97.60% success rate versus 27.73% on average for other annealers under identical iteration counts.

ABSTRACT. Scientific simulation leveraging high-performance computing (HPC) systems is crucial for modeling complex systems and phenomena in fields such as astrophysics, climate science, and fluid dynamics, generating massive datasets that often reach petabyte to exabyte scales. However, managing these vast data volumes introduces significant I/O and network bottlenecks, limiting practical performance and scalability. While cutting-edge lossy compression frameworks powered by deep neural networks (DNNs) have demonstrated superior compression ratios by capturing complex data correlations, their integration into HPC workflows poses substantial challenges due to the hybrid non-neural and neural computation patterns, causing excessive memory access overhead, large sequential stalls, and limited adaptability to varying data sizes and workloads in existing hardware platforms. To overcome these challenges and push the limit of high-performance scientific computing, we for the first time propose FLARE, a dataflow-aware and scalable hardware architecture for neural-hybrid scientific lossy compression. FLARE minimizes off-chip data access, reduces bubble overhead through efficient dataflow, and adopts a modular design that provides both scalability and flexibility, significantly enhancing throughput and energy efficiency on modern HPC systems. Particularly, the proposed FLARE achieves runtime speedups ranging from 3.50× to 96.07×, and energy efficiency improvements ranging from 24.51× to 520.68×, across various datasets and hardware platforms.

ABSTRACT. Neuro-symbolic artificial intelligence (NeSy AI) combines neural perception with symbolic reasoning, enabling logical reasoning. Hyperdimensional computing (HDC) is promising for NeSy AI, owing to its high parallelism and strong robustness to noise. However, the dense neural operations and memory-intensive symbolic inference in NeSy impose a severe "memory wall" bottleneck. Existing NeSy accelerators either focus solely on symbolic kernels or rely on conventional digital architectures, lacking a unified and energy-efficient hardware substrate. Moreover, exploring optimal hardware design configurations often requires costly trial-and-error. In this work, we propose UnO-NeSy, a unified CiM framework for optimizing NeSy computing. UnO-NeSy consists of UnO-CiM, an ultra-low-power NeSy architecture based on a homogeneous 2FeFET--2R compute-in-memory (CiM) array that supports both neural computation and HDC reasoning, and UnO-Sim, a cross-workload, end-to-end CiM simulator that models device non-idealities, neural quantization effects, and HDC execution behavior for accurate system-level evaluation. Built on UnO-Sim, we further develop an automated optimizer to identify workload-specific operating points under coupled energy, accuracy, and hardware constraints. By optimizing the operating configuration of the baseline 2FeFET-2R design, UnO-NeSy achieves 61.8% higher energy efficiency and 38.2% lower full-system inference energy, while consuming only 37.9% of the inference energy of the RRAM-based design. Across seven RAVEN configurations, UnO-NeSy achieves 96.2% average reasoning accuracy under hardware non-idealities, demonstrating a practical and scalable path toward ultra-low-power NeSy hardware.

ABSTRACT. Ising machines (IMs) are emerging as promising hardware accelerators for combinatorial optimization, but existing IM macros are still crafted largely by hand, hindering rapid design, retargeting, and scaling across problem sizes and technology nodes. We present AutoIsing, the first automated compiler for programmable IMs that generates optimized IM macros directly from user specifications. AutoIsing adopts a template-based hardware generation flow built on a fully customized cell library and a routing-free layout structure, enabling minute-level compilation. A flexible spin-mapping scheme supports arbitrary all-to-all connectivity and configurable weight precision under diverse hardware constraints. Implemented in TSMC 28nm, AutoIsing generates IM macros up to 400 spins with nanosecond-scale time-to-solution (<30 ns) and sub-nanojoule energy (0.453 nJ), while compiling a 400-spin macro in about 13 minutes. With a proposed coupling-ratio-controlled annealing scheme, the IMs can readily obtain solution accuracies above 95%. Compared to a state-of-the-art latch-based continuous-time IM, AutoIsing achieves comparable solution time and a 1.2× reduction in normalized energy. Overall, this work significantly accelerates the design and architectural exploration of the IMs hardware, providing a key enabling tool for the broad adoption of Ising computing in practical problems.

ABSTRACT. Additive manufacturing (3D printing) enables complex multi-layer microfluidic devices, but the physical synthesis of passive-flow designs remains a key bottleneck. In such systems, designers must encode timing synchronization and target dosing directly into channel geometry, even though the available routing space across multiple 3D layers is often highly congested, which makes scaling to complex designs difficult. Existing approaches formulate placement, routing, and fluidic constraints as a single monolithic optimization, leading to combinatorial explosion and poor performance on complex designs. This paper presents a volumetric-aware two-stage synthesis framework that decouples global structure from routing detail. A Mixed-Integer Programming (MIP) model first computes a compact multi-layer placement, followed by a dynamic 3D routing engine that enforces timing and volumetric constraints during path construction. To further improve routability in dense layouts, we introduce a hierarchical conflict resolution strategy combining local rip-up-and-reroute with controlled global expansion. Experimental results show that, under timing and volumetric constraints, 3D-VASE consistently improves synthesis speed and, in most test cases, also improves layout quality. Notably, for difficult large-scale cases where prior methods often failed to return any solution within the time limit, 3D-VASE produces feasible high-quality layouts within practical runtimes. These advances enable fast, iterative design-space exploration for complex 3D-printed microfluidic systems.

ABSTRACT. Designing heterogeneous AI accelerators requires more than just estimating peak compute throughput. As architectures combine specialized compute units, memory hierarchies, and hybrid electrical-photonic interconnects, system performance is often limited by data movement rather than computation alone. However, existing simulation frameworks typically model these domains separately, making it difficult to relate an observed bottleneck to the architectural decisions that caused it. To bridge this gap, we present STAGE (System-level Typed Accelerator Graph Environment), a unified system-level framework that compiles a typed hardware graph into a deterministic cycle-level model while preserving architectural and traffic provenance. STAGE traces stalls and energy costs back to the hardware behaviors that produced them. The model captures contention across routers, memories, and specialized units. We also introduce an optoelectronic extension that models route-dependent optical loss, wavelength-aware routing and contention, and tuning and conversion overheads. We evaluate STAGE using independent analytical checks, matched electrical-photonic case studies, and a 4×4 mesh comparison with BookSim2. STAGE reproduces analytical routing and optical link-budget calculations, matches BookSim2 in identifying the same severe mesh hotspot, and reveals how wavelength contention and conversion overheads shape system-level latency–energy trade-offs. These results demonstrate a reproducible and causally traceable methodology for heterogeneous accelerator co-design.

ABSTRACT. LLM inference cost makes hardware-software co-design critical, yet tools to guide such exploration remain fragmented. Hardware simulators estimate latency and area at fine granularity but ignore dynamic serving; system simulators capture batching and scheduling but rely on latency models without microarchitectural fidelity. Neither supports joint exploration of accelerator design and serving policy.

We present CoSim, a cross-layer co-simulation framework for LLM serving DSE. CoSim couples tile-granularity hardware modeling with event-driven serving simulation, and embeds prior-informed Bayesian optimization (PiBO) plus multi-objective search over throughput and latency, with effective area reported for design selection.

On real vLLM traces, CoSim matches end-to-end latency within 5.2-10.1% without per-GPU profiling. PiBO finds strong designs with far fewer evaluations than enumeration or generic surrogates, and joint search reveals hardware-scheduling trade-offs invisible to single-layer tools.

ABSTRACT. Mixture-of-Experts (MoE) models improve model capacity and inference efficiency. Single-GPU MoE inference is typically memory-bound because limited input parallelism prevents full compute utilization. Verified Multi-Token Prediction (MTP) generates several tokens per pass, reducing memory costs per token and increasing compute utilization. Integrating MTP with MoE, however, leads to inefficient expert execution. Serial execution underutilizes hardware because each expert processes few tokens, whereas parallel execution pads imbalanced expert workloads and wastes memory bandwidth. Consequently, existing execution mechanisms incur up to 64% higher latency.

We present MTPMoE, a framework for verified MTP in single-GPU MoE inference that preserves lossless accuracy without fine-tuning. Our key insight is that draft tokens generated by draft models are semantically similar and therefore activate highly similar experts. Motivated by this insight, MTPMoE packs frequently activated experts for dense computation and processes the rest with sparse computation. Implementing this strategy efficiently faces three challenges: (1) irregular activations make sparse computation inefficient, (2) input-dependent activation distributions make fixed expert packing suboptimal, and (3) low sparsity can make dense-sparse execution slower than conventional expert execution. To tackle these challenges, MTPMoE executes regular dense computation on high-throughput matrix units and irregular sparse computation on flexible general-purpose units in parallel, and further introduces three techniques: (1) Parallelism-driven Sparse Regularization pads irregular sparse activations into hardware-coalesced blocks; (2) Input-Adaptive Dense-Sparse Partitioning adjusts the partition threshold per input to balance the workloads; and (3) Sparsity-Aware Execution-Path Selection reverts to conventional expert execution when sparsity is below an offline-profiled threshold. On Qwen3-30B-A3B running on a single NVIDIA A800-SXM4-80GB GPU, MTPMoE achieves 6.69× and 4.49× end-to-end speedups over EAGLE3 directly integrated into HuggingFace and HuggingFace autoregressive inference, respectively.

ABSTRACT. Power efficiency is a critical design objective for embedded microprocessors, requiring accurate yet fast power modeling techniques. Architecture-level power model meets the requirement by estimating the processor power at the early stage. However, although many existing works have claimed high accuracy, the poor interpretability leads to unreliability of these models, preventing the industry from adopting them. To address the problem, in this paper, we propose UnifyPower, the first unified framework for architecture-level power models, unifying all existing types of power models in the same formulation. We perform in-depth quantitative analysis for representative models by inspecting intermediate results with intermediate labels, which uncover the root cause of the unreliability of these models. Driven by the analyzed root cause of the unreliability, we further introduce UnifyPower's model with improvements for each step upon the state-of-the-art model. UnifyPower's model can achieve an extremely high accuracy with a low MAPE of 3.15% and a high correlation R of 0.99. Importantly, it achieves a low maximum error of 5.93%, which is 17.26% lower than existing models, indicating its reliability.

ABSTRACT. With highly modular instruction set architectures (ISAs) such as RISC-V, rapid software profiling and fast evaluation of architectural variants enable workload-specific selection and customization. Yet, register transfer level (RTL) simulation is often too slow and FPGA prototyping requires great efforts for large-scale architectural exploration. As an alternative, performance simulators offer cycle-approximate profiling, but a major bottleneck is their creation effort: ML-based methods need training to build statistical models from instruction trace to cycle counts, while simulators based on architecture description languages (ADLs) require re-engineering the processor's architecture to capture the pipeline structure with its dependencies and buffers.

To address this challenge, this paper presents a multi-modal LLM-driven approach for generating accurate ADL models of processors from their datasheets. The proposed multi-stage method combines structured extraction of features from the text and images within the datasheet specification, constrained ADL code generation, and verification-driven refinement to improve code generation reliability. We tested the approach with CorePerfDSL as target ADL, which was designed for performance simulation, and evaluated it with two state-of-the-art, open-source RISC-V processors: CV32E40P and CVA6. Across a large set of benchmarks, the generated performance models achieve average relative CPI errors of 0.0015% and 1.79%, respectively, and can be constructed in less than 15 minutes in both cases. Compared with previously published, manually-constructed ADL models of these processors, the LLM-generated models achieve competitive or superior accuracy with greatly reduced development effort.

ABSTRACT. Circuit block diagrams encode functional modules and directed signal flow, yet rasterized design documents do not expose these relations to electronic design automation (EDA) tools. Recovering a machine-readable graph requires accurate semantic grounding, wire-level connectivity recovery, and direction assignment; end-to-end vision-language models (VLMs) often generate inconsistent object locations and connections in dense diagrams. This paper presents FlowMapper, a detection-guided and topology-first image-to-graph framework that decouples semantic anchoring, skeleton-based wire tracing, pass-over crossing discrimination, and arrow-grounded edge orientation. We also introduce SRCBD, a 1,403-image benchmark with object, output-port, and directed-connection annotations. On its 200-image test set, FlowMapper achieves F1 scores of 99.0% for object localization, 78.1% for output-port counts, and 75.3% for directed connections, with a latency of 0.117s per image on an RTX 3090. The resulting directed graph is serialized under a fixed JSON schema and can be exported to connectivity tables and standard DOT/GraphML formats. Under the same structured output schema, detector-provided visual anchors substantially improve VLM localization. Dataset and code are available at GitHub.

ABSTRACT. The efficiency of Deep Neural Network (DNN) accelerators depends on how each tensor operation is mapped onto the hardware. A mapping specifies how the computation is tiled across the memory hierarchy, ordered, and parallelized across the processing elements. These choices form a combinatorially large search space, where efficient mappings are hard to find. Most violate hardware constraints, and most remaining mappings underutilize the hardware. Existing mappers either search only part of this space to keep the search tractable, excluding the most efficient mappings, or sample the full space randomly, so most mappings they evaluate are infeasible. We present IMPACT, a mapper that searches the full space. IMPACT pairs a genetic algorithm with a constraint-aware repair operator that converts each infeasible mapping into a feasible one instead of discarding it. On a flexible accelerator, IMPACT outperforms state-of-the-art mappers in EDP, latency, and energy on \textit{every} DeepBench workload. On a compute-in-memory (CIM) accelerator, whose constraints leave few mappings feasible, it reduces EDP by 66\%, latency by 47\%, and energy by 18\% over the strongest prior mapper across five networks, and rivals hand-crafted expert mappings. Across flexible and highly constrained accelerators, IMPACT finds efficient mappings automatically. IMPACT will be released as open source.

ABSTRACT. Design space exploration for AI accelerators is frequently constrained by prohibitive simulation costs and labor-intensive manual tuning. We propose DSEAgent, an autonomous framework that pioneers an agent-in-the-loop paradigm by embedding a multimodal large language model directly into the optimization flow. This architecture enables active realtime interventions, including the preemptive pruning of unpromising configurations and the automated correction of architectural bottlenecks. The framework is supported by a domain-specific knowledge graph for expert reasoning and a sub-second learning-based estimator for rapid performance evaluation. Optimized via reinforcement learning, DSEAgent effectively navigates complex design spaces. Extensive evaluations demonstrate that DSEAgent reduces overall optimization time by 64.67% compared to human-guided workflows. Furthermore, it achieves comparable or superior design quality relative to state-of-the-art baselines while delivering up to a 10.31× speedup.

ABSTRACT. This paper presents SymbOperon, a design automation framework for neuro-symbolic edge perception. Instead of treating symbolic reasoning modules as fixed algorithmic choices, SymbOperon decomposes them into typed, hardware-characterized operators, generates new operators from a shared template, and explores valid compositions under edge hardware constraints. Across safety-critical perception workloads, the framework shows that generated operators can fill gaps that existing symbolic operators leave open, that the best reasoning design depends on task and platform budget, and that memory footprint, memory access pattern, and operation count must be considered jointly. SymbOperon reframes symbolic reasoning as a hardware-aware design space, enabling systematic operator generation and cost-quality optimization for edge perception. Generated operators match a tuned baseline at up to 17x fewer operations.

ABSTRACT. Efficiently deploying Deep Neural Networks (DNNs)—particularly Large Language Models (LLMs)—on tensor accelerators is essential for achieving high throughput and energy efficiency at the edge. However, the combinatorial explosion of the joint design space spanning intra-layer mapping and inter-layer fusion renders existing approaches inadequate. In this work, we present FADiff, a gradient-based optimization framework that automatically discovers optimal mapping and fusion strategies to accelerate DNN inference. We first formulate a unified, differentiable analytical cost model that accurately estimates the energy and latency of individual layer mappings as well as diverse fusion configurations. We then combine CP-SAT-based pre-enumeration of feasible discrete candidates with augmented-Lagrangian penalties over continuous relaxations, enabling a constrained gradient-based search that efficiently navigates the vast design space to identify optimal joint strategies. Experimental results show that FADiff consistently outperforms prior methods, delivering superior optimization quality with significantly faster convergence in both energy and latency.

ABSTRACT. Hardware-aware neural architecture search (HWNAS) typically relies on hand-crafted search spaces tailored to a specific task and target device. Retargeting to platforms with different operator sets, parameter domains, and structural requirements can therefore require redesigning the search space. Existing grammar-based NAS approaches preserve structural validity, such as tensor-shape compatibility at addition operations, but typically enforce resource constraints by rejecting completed models post hoc. We instead pair a shared graph grammar with a declarative device description that specifies supported operators, target-specific operator sequences, legal parameter domains, shape constraints, weight and activation memory budgets, and allowable weight and activation bit widths. Static grammar specialization removes unsupported choices, while constraint-aware constructive derivation propagates tensor shapes and resource costs. Lower and upper estimates of the resources required to complete a partial architecture guide pruning during sampling. A completed architecture is returned only if it satisfies the declared device constraints; compiler acceptance, placement, and on-device execution are evaluated separately. Retargeting the search space therefore changes the device description without redesigning the shared structural grammar. Using one base grammar, we target the MAX78000 fixed-function accelerator, the STM32F429 microcontroller, and an NVIDIA Jetson AGX Xavier GPU. Evolutionary NAS over the resulting search spaces finds models achieving CIFAR-10 test accuracies of 86.33\%, 88.63\%, and 93.83\% on the MAX78000, STM32F429, and Jetson, respectively.

ABSTRACT. Learned Image Compression (LIC) has emerged as a promising solution for satellite image transmission due to its superior rate-distortion performance. However, its significant computational complexity and the inherently serial nature of entropy coding severely constrain high-throughput deployment on edge devices. Although existing general-purpose GPU entropy coding libraries, such as NVIDIA nvCOMP and Meta DietGPU, offer high throughput, they lack support for the symbol-level dynamic probability estimation essential for LIC, resulting in a severe penalty in compression efficiency. To address these challenges, this paper presents an end-to-end high-throughput inference system for hyperprior-based LIC on edge GPUs. First, we design a thread-level parallel rANS entropy codec (TLP-rANS) that drives parallel encoding and decoding directly from the distribution parameters generated by the hyperprior network, moving the previously serial entropy coding out of the inference bottleneck. Second, we build a fully GPU-resident inference pipeline with a batch-level parallelism strategy that eliminates frequent CPU-GPU data transfer. Experiments on the Jetson AGX Orin platform demonstrate that our system achieves near-lossless compression on the Kodak dataset, with a BD-rate loss of only 0.59\% relative to the native PyTorch implementation, and outperforms advanced coding standards such as JPEG 2000, HEVC intra, and AV1 intra. At low bitrates, the encoding and decoding speeds of our system reach 296.4 and 208.4 FPS respectively, about 19 times faster than the native implementation. This performance significantly surpasses existing edge GPU acceleration schemes, providing an efficient solution for real-time LIC deployment in satellite image transmission.

ABSTRACT. High-effort logic optimization methods such as (GPU-)transduction and rewiring are based on redundancy addition and removal (RAR) to achieve high-quality optimization results for AIGs. Despite their strong optimization capability, these methods follow a speculative process in which legal wire additions are applied before their reduction effects are known. Many wire additions fail to expose profitable reductions, yet still incur temporary updates to the AIG and trigger recomputation of frequently used data such as observability don't-cares (ODCs) and truth tables. Moreover, because these wire additions are guided mainly by legality rather than explicit reduction targets, the resulting restructuring becomes increasingly ineffective as AIG size grows. This paper extracts the effective action embedded in successful RAR trials and reorganizes it into a targeted workflow. Our method selects an explicit reduction target before ODC analysis and wire search, and jointly determines the wire additions and target removal before updating the AIG. Experimental results on the IWLS 2022, 2023, and 2024 benchmark suites show that our method achieves 45.2%-49.1% converged size reduction, compared with 43.3%-48.3% for GPU-transduction and 33.0%-40.1% for rewiring, while achieving the best depth results and converging in 3.0s-4.3s versus over 2800s for GPU-transduction and 11.8s-16.3s for rewiring.

ABSTRACT. And-Inverter Graph (AIG)-based logic synthesis overlooks complemented-edge (inverter) distribution during technology-independent optimization, yet inverters become a critical cost factor during technology mapping. We propose a pre-mapping inverter redistribution method that identifies self-dual and self-anti-dual subfunctions via cut enumeration and relocates complemented edges in an equivalence-preserving manner. To maximize delay improvement, the method incorporates two complementary strategies. First, it selects an optimal local subset of inversion candidates for each node. Second, it applies a library-aware tie-break rule that explicitly leverages the delay asymmetry between XOR and XNOR gates. On the Nangate45 library, the method achieves zero delay-regressions across the EPFL combinational benchmark suite, with a geometric-mean delay reduction of 0.48% and up to 4.34% on the sqrt benchmark. A cross-library study across three technology nodes (130nm, 45nm, 7nm) demonstrates that the library-aware tie-break achieves zero regressions on three of eight library corners.

ABSTRACT. Resubstitution re-expresses a node of an And-Inverter Graph over existing signals, yet it remains insert-bounded, as exact enumeration stops at two or three inserted gates and SAT-based resynthesis buys a handful more at disproportionately larger budgets. The deep-insert region below each node’s maximum fanout-free cone (MFFC) therefore stays out of reach. We argue for a third insertion point for learning in logic synthesis, beyond flow selection and standalone generation: a learned operator, a generative proposer inside a sound classical wrapper, evaluated against the identical harness. DeepResub instantiates this class. Its model proposes each next gate as a truth table and snaps it to a realizable AND over the window’s divisors and previously generated gates, while a sound feasibility mask keeps generation constructive. Exhaustive care re-simulation, a strict gain gate, disjoint commits, and a global combinational equivalence check verify every replacement, with no exact-insertion fallback, so the operator reaches up to |MFFC|−1 inserted gates under satisfiability and observability don’t-cares. On all 20 EPFL circuits, DeepResub improves geometric-mean area and level over matched-window ABC resub -K 8 -N 3 by 3.50% and 3.02%, and against the stronger -K 16 -N 3 it trades 1.00% standalone area for a 2.29% level lead and the best area-depth product. Beyond the suite, it removes 2,426 further ANDs from identical time-bounded DeepSyn outputs and improves 63 published minima across 500 official IWLS’23–’26 circuits, removing 763 ANDs to K16/N3’s 108 and time-matched DeepSyn’s 115, with every output CEC-clean.

ABSTRACT. The rapid advancement of Machine Learning (ML) has demonstrated immense potential for logic synthesis, design-space exploration, and circuit optimization. In practice, however, researchers who want to combine these areas repeatedly face the same infrastructure problem: the surrounding ML and data-science ecosystem is centered on Python, whereas the core data structures and algorithms of logic synthesis are the product of decades of highly optimized C/C++ engineering. As a result, individual projects are often forced either to rebuild logic synthesis functionality from scratch in Python or to assemble brittle wrappers and file-based conversion pipelines around external tools. To address this recurring gap, this paper introduces aigverse, a unified open-source infrastructure project that brings mature logic synthesis capabilities into Python-first workflows without reimplementing them there. To this end, aigverse wraps high-performance C/C++ synthesis backends within an idiomatic Python interface and provides reusable support for circuit construction and manipulation, dataset generation, optimization and equivalence-checking flows, and export into graph and tensor representations for downstream data science and ML pipelines. In a case study comparing a pure-Python tensorization pipeline from the literature against aigverse, the latter achieves up to 17.2× faster end-to-end tensorization while reducing isolated framework hand-off overhead by three to four orders of magnitude depending on circuit size. In this way, aigverse is intended to provide for logic synthesis the kind of reusable, domain-aware software bridge that has already helped ML become effective in scientific fields such as medicine and chemistry without requiring those researchers to become application-domain experts.

ABSTRACT. Modern Register-Transfer-Level (RTL) designs translate to netlists with billions of gates, exceeding the memory and runtime capacity of logic synthesis tools. On our largest designs, flat synthesis does not complete at all. Partitioning a design into independently synthesizable tasks is the natural remedy, but it is fundamentally a two-objective problem: a partitioner must minimize the scheduled parallel makespan while keeping the impact on post-synthesis quality (PPA) negligible. Minimizing makespan alone is easy but destructive, as splitting until the load balances severs logic across module boundaries and degrades PPA. Few partitioners target this objective directly, and the problem has gone largely unstudied because no open design was large enough to require partitioning. We present PP2Tree, a learning-guided framework that partitions the RTL instance tree by jointly optimizing the scheduled makespan and an edge-cut penalty that protects PPA. A lightweight circuit learner predicts per-instance synthesis workload and inter-module cut cost from AST-derived features, and a linear-time frontier-pushing algorithm (TTP) drives the partition boundary into bottleneck sub-trees. We evaluate in two regimes. On an open, reproducible suite of real and synthetic circuits where monolithic synthesis is feasible, PP2Tree reduces synthesis runtime by up to 16.2× and peak memory by up to 4.9× while holding post-synthesis area within 5% and logic depth within 11% of the no-partition ceiling. On large industrial designs where flat synthesis is infeasible, PP2Tree reduces parallel synthesis time by 51.4% over a tuned METIS baseline and by 13.3% over METIS given our workload predictions, holding post-synthesis area within 1% of METIS. We release the benchmark suite and its generators to enable further research

ABSTRACT. Logic synthesis is an early stage of the RTL-to-GDS flow, yet conventional synthesis cannot reliably improve post-layout power, performance, and area (PPA) because physical effects introduced during place-and-route (P&R) substantially alter circuit timing and power. In this paper, we propose a physical-aware logic resynthesis framework that combines placement-predicted wire capacitance with cooperative multi-agent reinforcement learning (MARL) for post-placement timing closure. The synthesized netlist is decomposed into primitive gates (AND2, OR2, NOT), represented as a directed acyclic graph (DAG), and partitioned into timing-critical clusters. Within each cluster, an agent traverses the selected critical region in reverse topological order and performs localized cell remapping and logic restructuring. Each action is evaluated using a placement-aware timing model that estimates its physical impact relative to the original netlist. Centralized training with decentralized execution (CTDE), supported by a centralized critic and shared team reward, coordinates local agents toward global timing improvement. Experimental results demonstrate that the proposed framework reduces the post-placement total negative slack (TNS) and worst negative slack (WNS) magnitude by 33.2% and 29.6%, respectively.

ABSTRACT. In modern chip design, optimizing the power delivery network (PDN) during the Engineering Change Order stage remains a major challenge. When the die design is fixed, package optimization becomes the primary approach to reducing dynamic IR drop, i.e., the dynamic voltage loss across the package-level PDN between solder balls and die bumps. This motivates the need for efficient assessment of the package's contribution to dynamic IR drop. However, traditional simulation-based approaches are prohibitively time-consuming, and existing machine learning (ML) methods lack a dedicated framework for package-level dynamic IR-drop prediction. This paper proposes a dual-branch ML model to predict the dynamic IR drop of bumps across diverse package configurations. The model combines a Graph Attention Network branch, which aggregates inductive coupling and time-varying current effects from neighboring bumps based on mutual inductance, with a parallel Multi-Layer Perceptron branch that captures the intrinsic features of the target bump. Experimental results show that, with limited target-package training data, the proposed model achieves an average RMSE below 3 mV and an MAE below 2.3 mV while providing a considerable reduction in analysis time compared with commercial tools.

ABSTRACT. As heterogeneous chiplet systems scale, defects detected late in assembly can destroy substantial accumulated value. Prior work has optimized chiplet test plans while largely assuming a fixed assembly sequence. We show that assembly order should instead be optimized jointly with pre-bond qualification, accounting for component cost, conditional quality, test coverage, and chiplet qualified test variants. We develop an open-source tool that selects both the assembly sequence and the cost–coverage option for each chiplet. Across synthetic and product-inspired systems, our provably optimal dynamic programming-based approach delivers multi-magnitude runtime gain over enumeration and an average 44% cost reduction over heuristics. We also demonstrate that changes in component prices can alter the preferred assembly sequence, motivating periodic re-optimization as supply conditions evolve.

ABSTRACT. Soft errors are an increasing reliability concern for Deep Neural Network (DNN) execution because they can corrupt parameters, leading to accuracy degradation. While conventional ECC offers strong fault protection, it incurs additional parity storage and computational overhead. Embedded-parity formats reduce storage cost by reusing the least-significant bits, but they do not optimize protection while reducing computational overhead. We propose UniCASE, a unified 16-bit floating-point (FP) format that jointly optimizes data representation and error protection for reliable DNN execution. UniCASE identifies stable blocks across FP64, FP32, FP16, and BFloat16 that can be mapped into a unified representation. Based on bit-level criticality analysis, UniCASE uses selective ECC that assigns distinct levels of protection to different data bits according to their resilience against soft errors. Experimental results show that UniCASE reduces encoder/decoder cost by up to 30%, preserves model accuracy within 1% of the FP32 baseline, and provides significantly stronger soft error resilience than existing embedded-parity methods.

ABSTRACT. In safety-critical deployments such as autonomous vehicles and medical robotics, AI hardware must remain reliable against a broad spectrum of threats such as radiation-induced upsets, aging, hard faults, and adversarial attacks (e.g., progressive bit-flip attack (PBFA)). All of these corrupt stored weights while the chip keeps producing confident (but inaccurate) predictions. Detecting (and mitigating) such weight perturbations before they cause failure is of utmost importance for safety-critical platforms. We propose BLINK, an on-chip batch normalization (BN)-based on-the-fly detection and mitigation approach, which is based on continual sensing of the shift in the activation statistics, targeting a wide variety of weight corruptions (random and localized faults as well as adversarial bit flips). BLINK operates in two phases: (1) offline pre-characterization of the relationship of the activation shifts with inference accuracy degradation, and calibration of per-layer thresholds; and (2) on-chip runtime detection and mitigation of weight corruptions. Our technique is designed so that benign perturbations stay silent, while faults costing as little as 10% top-1 accuracy are flagged. Upon detection, the flagged layer is re-centered to bring it closer to its stored clean reference within the same forward pass, with no weight rewriting, no communication with a system host, and no labels. Alternatively, depending on the accuracy needs and hardware resources, on-chip BN fine-tuning can be utilized for mitigation upon error detection. If the residual shift after mitigation indicates that accuracy has fallen below a user-set floor (e.g., 50%), a held-out watcher aborts the inference. Evaluated on ResNet-20/50 and MobileNetV2 over CIFAR-10/100, BLINK flags harmful perturbations (i.e., those causing over a 10% accuracy drop) with 90-99% precision across all fault types. Furthermore, it recovers accuracy from 10% to 85.88% under 0.5% random bit flips (ResNet-50/CIFAR-10), up to 84% for localized faults (MobileNetV2/CIFAR-10), and from random-guess accuracy to 80-83% under PBFA (ResNet-20/CIFAR-10). All detection and mitigation run entirely on chip, within a single inference pass, at <2% latency cost and 0.14% computation overhead.

ABSTRACT. Transient hardware faults can corrupt processor state and cause silent data corruption (SDC) in embedded systems. Software-implemented hardware fault tolerance (SIHFT) mitigates this risk through redundant execution and checking, but incurs runtime overhead from additional shadow work and the register pressure caused by reserved shadow GPRs. Existing selective-hardening approaches determine which computations to duplicate, but do not manage redundant state or fixed shadow-register capacity after target lowering and register allocation. This work presents output-confinement-guided hardening in the RISC-V COMPAS backend. Applications designate selected output objects as tolerant, while all other state retains an exactness requirement. The compiler propagates output-confinement information from LLVM IR to physical-GPR live intervals and applies two complementary mechanisms: protocol-aware interval pruning removes eligible shadow work, while protection-aware shadow-capacity reuse forms additional protected pairs from released shadow GPRs, with optional donor-guided allocation. We evaluate five RV32IMAC programs using cycle-accurate simulation and processor-wide RTL fault injection. The proposed configurations eliminate 13.3--60.2\% of the additional cycle cost of full COMPAS hardening while retaining 56.7--89.4\% of its observed overall-SDC reduction relative to unprotected execution. Interval pruning reduces cycle overhead in every program, whereas the benefit of shadow-capacity reuse depends on whether the revised layout changes register allocation. Across all 15 main operating points, the observed non-tolerant SDC rate is lower than that of the corresponding unprotected binary.

ABSTRACT. Universal Chiplet Interconnect Express (UCIe) enables standardized die-to-die communication in chiplet systems. However, existing network-on-chip (NoC) timing analyses do not model the packetizer, scheduling, and reinjection effects introduced at UCIe boundaries, making end-to-end quality-of-service (QoS) analysis for UCIe-based communication unexplored. This paper first introduces a UCIe-based cross-die communica- tion model. Based on this model, we develop a network-calculus- based QoS analysis method that represents the UCIe boundary as a composable class-aware service stage. Specifically, we derive a class-aware UCIe boundary service curve and integrate it with source-side and destination-side NoC services to obtain end-to- end delay bounds for individual flows. The model captures the key characteristics of the modeled UCIe-compatible interface, includ- ing packetizer timeout, priority-aware scheduling, PHY bandwidth, and receiver-side processing. Experiments confirm that the derived bounds safely upper-bound all observed delays and achieve up to 89.7% tightness. Results further show that the introduced UCIe in- terface can significantly increase the observed end-to-end delay by 3.24× relative to a comparable monolithic mesh, highlighting the importance of explicit UCIe-boundary modeling in end-to-end QoS analysis.

ABSTRACT. Recent side channel attacks show that software visible RAPL traces can reveal DNN architectures and layer wise hyperparameters on CPUs. Existing obfuscation methods mainly target GPU oriented architecture stealing or timing leakage, and do not directly optimize against real RAPL trace patterns. This paper presents TraceMorph, a framework guided by real traces for execution level obfuscation to protect DNN architectures under RAPL based attacks. TraceMorph applies semantics preserving layer branching, layer deepening, and layer skipping to transform a vanilla DNN into a functionally equivalent but trace diverse executable model. A genetic algorithm searches for effective transformation configurations by executing candidate models on the target CPU, collecting RAPL traces, and evaluating architecture recoverability with an evaluator guided by DeepTheft. The fitness function jointly reduces the accuracy of the structure recovery and penalizes excessive expansion of the trace length. Experiments on 512 VGG and ResNet architectures show that, under a 20% trace length expansion budget, TraceMorph reduces SA from 99.82% to 85.70% and LDA from 98.05% to 72.26%. It also decreases the average F1 score for hyperparameter inference from 99.44% to 64.71%. These results indicate that structural obfuscation guided by real traces can weaken the architecture dependent evidence exploited by recovery attacks based on RAPL.

ABSTRACT. Fully Homomorphic Encryption (FHE) presents a paradigm-shifting framework for performing computations on encrypted data, unlocking the transformative potential for privacy-preserving technologies. Dual-scheme FHE execution is increasingly preferred for privacy-preserving machine learning, as it avoids the accuracy degradation observed with single-scheme FHE. However, mixed-scheme execution is constrained by the availability of scheme-switching primitives and the costly CKKS and FHEW scheme-switching interface, including repeated decomposition and reduction, key movement, staging overhead, and dataflow traffic across the switching path. This paper introduces DRS, an accelerator architecture that enables more efficient mixed-scheme execution on an FPGA. DRS unifies CKKS kernels, FHEW kernels, and bidirectional RLWE-to-LWE and LWE-to-RLWE switching on a single U280 FPGA. DRS mitigates scheme-switching interface overhead through a shared digit-wise fused MAC-and-reduction datapath, explicitly banked on-chip staging, and HBM-backed key streaming. DRS shows improved practicality for the mixed-scheme ResNet-20 workload, achieving up to 1.52× end-to-end speedup.

ABSTRACT. As a fundamental primitive operation in contemporary cryptographic protocols, such as zero-knowledge proofs, elliptic curve cryptography, and Rivest–Shamir–Adleman, it is desirable to develop an efficient design for large-bitwidth modular multiplication. We present an efficient design, in which the pipelined data flow shortens the critical path, and the k-term Karatsuba algorithm reduces cycles from k^2 to T^(k), which is close to k^(log2(3)).

Represented by a matrix pair (E^(k), I^(k)), the Karatsuba algorithm also brings unexpected overhead from the extra evaluation and interpolation phases. We first propose efficient k-term Karatsuba algorithms when k is a power-of-two. The uniform sign of all columns of E^(k) and I^(k) removes most of the negation logic. Later, an efficient row-based mechanism is proposed to process all rows of I^(k) in a multiple cycle manner. The redundant computations for constant 0 are eliminated. The bitwidth of intermediate results roughly reduces by a factor of k. Rigorous proof allows us to accumulate intermediate results through compression, rather than the more complex addition. As such, experimental results demonstrate 24.12% and 38.99% savings in area/throughput, when compared with the state-of-art 1024-bit and 2048-bit designs.

ABSTRACT. Speculative decoding (SD) has become a key technique for accelerating LLM inference by generating and verifying candidate tokens in parallel. PIM and 3D-memory architectures further amplify this speedup, but acceptance-aware execution introduces a fundamental side-channel vulnerability. This vulnerability arises from the three stages of SD—drafting, verification, and commit—whose timing and traffic patterns can expose private user requests to co-located adversaries.

We propose AOEL, an Acceptance-Obfuscating Execution Logic that protect against these channels by reducing the dependence between private token-acceptance states and observable hardware activity. AOEL enforces security-aware runtime control in each PIM or 3D-memory stack through three mechanisms targeting the three vulnerable stages. First, Public Speculation Envelope (PSE) maps private acceptance history and public envelope history to coarse-grained, public footprint-shaping classes. Second, Balanced Resource Scheduling (BRS) fills rejection-induced idle slots with protocol-compatible next-window candidate precomputation and committed-prefix KV prefetching. Third, Private Batched Commit (PBC) keeps acceptance metadata private and regulates visible KV-state updates through fixed-size public commit batches. Across 11 state-of-the-art SD architectures, AOEL reduces the mean source-wise normalized leakage from 74.4% to 19.8%. Across four representative accelerators, AOEL achieves an average 3.83× decoding-slice speedup over non-speculative decoding while retaining 92.8% of the original speculative-decoding speedup.

ABSTRACT. Fully Homomorphic Encryption (FHE) enables secure computation on encrypted data, but its high computational overhead poses significant challenges for practical deep learning inference. For instance, in many application scenarios, high-resolution images may only contain a small portion of sensitive information, but very limited previous works have considered this. With this background, in this paper, we propose a novel FHE computing framework that accelerates encrypted Convolutional Neural Network (CNN) inference by only encrypting the privacy-sensitive regions of the input while processing the remaining parts in plaintext. Our method, named as Partial Fully Homomorphic Encryption (PFHE), significantly reduces computational cost without compromising data confidentiality. Overall, three layers of innovative contributions have been made in this work. First of all, we construct an inference framework that is suitable for partial encryption on CNN. Second, we propose a novel PFHE convolution method that scales down the required number of homomorphic operations with the size of the encrypted region. Thirdly, we leveraged the scheme switch functionality (between CKKS and FHEW) to achieve a fast and accurate ReLU evaluation in the PFHE scenario. We have also evaluated our framework on the ImageNet dataset for the first six convolutional layers. Comparing to conventional Channel-wise convolution method, our method achieves at least 4.12× speedup in latency and 28.72× less memory. We also proposed hybrid method in case study, combining our PFHE method with Channel-wise convolution, showing that the proposed method obtains at least 10.30× latency reduction and 33.30× less memory consumption than the baseline method, and much less latency than the other works in the literature. We hope the outcomes of this work will impact the further application of FHE in large-scale machine learning systems.

ABSTRACT. Speech signals inherently encode a broad range of information beyond their linguistic content, including speaker attributes such as gender, age, and ethnicity. Although recent advances in machine learning have significantly improved the utility of speech-based applications, the associated privacy risks remain relatively underexplored. Achieving an optimal privacy–utility tradeoff is essential for developing speech systems that are both effective and privacy-preserving. In this work, we propose a new audio anonymization technique, Multi-feature Demographic Decoupling via Linear Predictive Coding (MDD-LPC), which requires no network training or attacker knowledge to address anonymization in more complex privacy-utility pairs, such as healthcare applications and demographic information, unlike existing approaches where privacy and utility (speech content and demographic information) pairs are less interconnected. The proposed method was evaluated on two emotional-speech corpora (CREMA-D, RAVDESS) and a clinical pain-speech corpus (TAME Pain) using three independent machine learning classifier families. Experimental results show that MDD-LPC achieves an improved privacy–utility tradeoff by reducing gender information leakage by 56.4% and 46.3% on the CREMA and TAME Pain datasets, respectively, while maintaining competitive downstream task performance. In the Raspberry Pi 4 hardware deployment, MDD-LPC anonymizes audio 31.1× faster and with 20.24% lower power consumption than a representative learning-based baseline, highlighting its suitability for real-time, resource-constrained clinical health-monitoring hardware.