Program for Wednesday, January 27th, 2027: Talk View

PROGRAM FOR WEDNESDAY, JANUARY 27TH, 2027: TALK VIEW

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9:00

9:30

10:00

10:30

11:00

11:30

12:00

12:30

13:00

13:30

14:00

14:30

15:00

15:30

16:00

16:30

17:00

17:30

18:00

18:30

19:00

19:30

20:00

20:30

09:00-09:50 Session 2K

10:20-12:20 Session 4A

10:20-10:40

Structure-Preserving Density Modeling for Electrostatics-Based Analytical Placement

Jai Ming Lin, Ching-Hung Wang, Liang Ting Fan, Yi Chou

10:40-11:00

Learning-Guided Adaptive Cell-Wise Optimization for Mixed-Size Global Placement

Cheng-Yu Chiang, Wei-Hsiang Tseng, Yao-Wen Chang, Hung-Ming Chen

11:00-11:20

qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits

Z. Liu, J. Hong, R. Aviles, S. Razmkhah, P. Beerel, M. Pedram

11:20-11:40

ALTO: Joint Track-Height and Placement Optimization for Non-Integer Mixed-Cell-Height Designs

Luis Humberto Pena Trevino, Lirida Naviner, Fady Abouzeid

11:40-12:00

Wirelength-Driven Mixed-Cell-Height Detailed Placement with Multi-Row Cell Relocation

Sunghyun Song, Heechun Park

12:00-12:20

SCALE: Self-Supervised Constraint-Aware Layout Generation for Local P&R DRV Fixing at Advanced Nodes

Ho, Yang, Zhou, Nishi, Li, Turner, Yu, Chen, Khailany

10:20-10:40

CircuitsDNA: Discovering Unconventional Multi-Accuracy Arithmetic Circuits via Evolutionary

Qi, Luo, Jiang, Cheng, Kielian, Laurie, Sylvester, Saligane

10:40-11:00

REASON: RNG-Aware Finite-State Machines for Hardware-Realistic Stochastic Nonlinear Approximation

Zhaojun Ni, Yutong Wang, Jie Han, Siting Liu

11:00-11:20

Low-Power Approximate MRAM CAM with Dynamic-Reference for HDC Associative Search

Qifeng Kong, Songlin Zhu, Zhongkun Shen, Erya Deng, Weiqiang Liu

11:20-11:40

SWAPPER: Dynamic Operand Swapping in Non-commutative Approximate Circuits for Online Error Reduction

M. Traiola, N. Misyats, S.-I. Filip, R. Garcia, A. Kritikakou

11:40-12:00

AX-AGENT: Contract-Driven Closed-Loop Framework for Error-Bounded PPA-Aware Approximate RTL

C. Dai, T. Zhou, M. Xiang, Y. Liu, H. Waris, L. Li, Y. Fu

12:00-12:20

MATE: Model-Assisted Trade-off Exploration for Quality-Aware Approximate Matrix Computing

Liping Wang, Yu Gong, Yi Yang, Yike Wang, Dongzhu Gao, Ke Chen, Weiqiang Liu

10:20-10:40

InfoCIM: An Information-Theoretic Framework for Modeling and Design of Noise-Limited Analog CIM

Y. Chen, W. Zhou, S. Wang, Y. Feng, W. Yao, Y. Xie, W. Kang

10:40-11:00

Compiler-driven Optimizations for Efficient Host and Near-DRAM Co-Execution

Kukić, Ivantsiv, Gaydadjiev, Galuzzi, Klein, Biswas, Ansaloni, Atienza

11:00-11:20

DRAC: A Static Analysis for DRAM Row Activation Count Toward Efficient Processing-in-Memory Code

Chenghao Quan, Yeongbae Shin, Jaewoo Park, Jongeun Lee

11:20-11:40

Less is More: KV Cache Scheduling for Bandwidth-Efficient LLM Inference on FPGA

Dong Liu, Yanxuan Yu, Chang Liu

11:40-12:00

RASP-LLM: Radiation-Aware Design-Space Exploration of Precision and Selective Protection for On-Orbit LLM

Yuechen Xi, Yueyao Zhu, Huize Chao, Ziyu Wang, Zhenhua Zhu, Yu Wang

12:00-12:20

Reducing Cascaded Speech-to-Speech Latency via Speculative Prefilling and Incremental Cache Recovery

Hojeong Kim, Junyoung Lee, Shinhyoung Jang, Hyunsei Lee, Yeseong Kim

10:20-10:40

DiffTherm: A Differentiable Thermal Formulation for Cell-Via Co-Optimization in 3D ICs

Ikkyum Kim, Heechun Park

10:40-11:00

SPLIT-MOR: Fast and Accurate Model Order Reduction for Nonlinear Transient Thermal Simulation of 2.5D/3D

Zebin Shi, Tianxiang Zhu, Yibo Lin, Runsheng Wang

11:00-11:20

SiliDiff: Post-Silicon Thermal and Power Reconstruction from Sparse Sensing with a Cascaded Conditional Diffusion

C. Shen, Y. Lu, N.K. Cherukuri, V. Honkote, S.S. Sapatnekar, Y. Cao

11:20-11:40

Gradient-Guided Thermal-Aware Timing Robustness Optimization Under Temperature Inversion

Yi-Xin Lan, Chun-Yao Chiang, Shao-Chen Wang, Ming-Chao Lee, Iris Hui-Ru Jiang

11:40-12:00

STRIDE: Sparse Thermal Reconstruction-Informed Differential Encoding for Thermally Stable 3D-Integrated Analog

Y. Chen, S. Wang, Y. Yao, W. Yao, Y. Lu, W. Zhou, W. Kang

12:00-12:20

ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging

Yong-Han Lin, Jen-Yi Wang, Pei-Yu Huang, Yu-Min Lee

10:20-10:40

GREG: A Graphical Static Analysis Framework for Early Hardware Security Verification

Bryan Kwan, Benjamin Tan

10:40-11:00

PARFuzzer: Path-Aware RTL Fuzzing with Controlled BTB Conflict Injection for Branch-Predictor Security

M. Dong, J. Cai, J. Zhai, F. Zhao, J. He, K. Zhao, Y. Lyu

11:00-11:20

DISSECT: Cross-Family RTL Trojan Localization by Auditing Structural–Functional Disagreement

Jia Rao, Jiansheng Chen, Yushuo Zhao, Qizhi Zhang, Jiaji He

11:20-11:40

Cube-based Finite-State-Machine Extraction via SAT Generalizations

Rajesh Kumar Datta, Kaveh Shamsi

11:40-12:00

Functional Retrieval for Resynthesis-Robust Hardware Trojan Detection in Gate-Level Netlists

Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu

12:00-12:20

Between The Cracks: Uncovering Illegal-Instruction Bugs in RISC-V Processors by Exploring the Unified Encoding

Yicheng Zhong, Jingzheng Wu, Xiang Ling, Tianyue Luo, Chen Zhao

13:20-15:20 Session 5A

13:20-13:40

Placement Guidance Generation via Timing-Aware Hypergraph Partitioning and Multi-Criteria Cluster

S.-Y. Huang, Y.-T. Kuo, T.-Y. Kuan, T.-C. Chen, W.-K. Mak, T.-C. Wang

13:40-14:00

FRESHPart: Feedback-Reshaped Spectral Embedding for Hypergraph Partitioning

Rongjian Liang, Zhuo Feng, Brucek Khailany

14:00-14:20

Learning-Augmented Multilevel Hypergraph Partitioning with Net-Level Cut Priors

Pengju Zhang, Ziyi Wang, Bei Yu, Zhiang Wang

14:20-14:40

RAP: Resource‑Aware Scheduling for GPU Accelerated Hypergraph Partitioning

Shang Liu, Qijun Zhang, Yugao Zhu, Mengming Li, Wenkai Li, Zhiyao Xie

14:40-15:00

CCPart: Timing-Aware Multi-Level Partitioning for Multi-FPGA Systems with Incremental Timing

Y. Dai, S. Tong, Y. Chen, C. Pei, Z. Wang, H. Weng, Y. Liu, R. Wang, W. Yu

15:00-15:20

From Communities to Coordinates: Hierarchical Clustering–Guided Placement for Large-Scale FPGAs

Ke Li, Pengju Zhang, Zhiyu Zheng, Yuhao Ren, Keren Zhu, Zhiang Wang, Xuan Zeng

13:20-13:40

SHARD: Sub-Transformer Harnessing for Adaptive Resource-Aware Deployment

Sudaksh Kalra, Rob Bieman, Dolly Sapra

13:40-14:00

MemFLoRA: Memory-Floor LoRA for CNN Adaptation at the Edge

Mehmet Emre Akbulut, Johannes Geier, Ulf Schlichtmann

14:00-14:20

NgramRL: Accelerating RL Post-Training for Structured Generation via Rollout-Aware N-gram Speculative

Nilesh Prasad Pandey, Jangseon Park, Jason Kong, Onat Gungor, Tajana Rosing

14:20-14:40

T3R: Training-Free Two-Stage Token Refinement Towards Efficient and Robust VLA Models

M. Hassan, Z. Chen, Z. Wang, Z. Zhu, T. Chen, Y. Lin, C. Li

14:40-15:00

SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference

Yongxiang Lyu, Ning Li, Bonian Jia

15:00-15:20

MARCO: Markov Decision-based Adaptive Path Selection for Dynamic Layer Skipping

Ning Yang, Fangxin Liu, Junjie Wang, Li Jiang, Haibing Guan

13:20-13:40

Naviq: An Open-Source System-on-Chip Simulator for Rapid Prototyping, Verification, and Design Space

Scott Smith, Lukas Zscherpel, Alyssa Huang, Marissa Lanz, Deming Chen

13:40-14:00

PaFeDSE: Pareto-Feedback-Guided Microarchitecture Design Space Exploration for Efficient Pareto

Joonyong Park, Hyojeong Lee, Sejeong Yang, Joo-Young Kim

14:00-14:20

MAP-DSE: A Fast Performance Simulator for Large-Scale Microarchitectural Design Space Exploration

Conrad Foik, Daniel Mueller-Gritschneder, Ulf Schlichtmann

14:20-14:40

ChronosDSE: Stability-Aware Design Space Exploration for GPGPUs

Zhenwei Duan, Dingyi Zhao, Zibo Gao, Jing Wang, Xinyu Ye, Biwei Xie, Yungang Bao

14:40-15:00

From Compiler to Silicon: A Co-Design Approach to High-Performance CGRAs

Rodríguez Álvarez, Wang, Constantinescu, Ansaloni, Peón-Quirós, Atienza

15:00-15:20

LU-Evolve: Agent-Based Algorithm Exploration for Sparse LU Solvers

Yixin Liu, David Wei Zhang, Fan Yang

13:20-13:40

EMPUF: A Leakage-Controlled Pre-Fabrication Benchmark for PCB Spectral Fingerprints

Renchao Li, Hao Lu, Xiangyu Wang

13:40-14:00

A Lightweight Microring-Resonator PUF Design for Silicon Photonics Transceivers

Xinyuan Zhao, Chenghua Wang, Yun Wu, Chongyan Gu, Yijun Cui, Weiqiang Liu

14:00-14:20

Lightweight Key-Based Hardware Device-ID Authentication: A Reliable, ML-Resistant Alternative to

James Moore, Chongyan Gu, Jack Miskelly, Maire O'Neill

14:20-14:40

A Reliability-Enhanced SOT-MTJ PUF with Obfuscated Write-Back for Physical-State Exposure Mitigation

Guocheng Jing, Zhongkun Shen, Yawei Tang, Erya Deng

14:40-15:00

Power and EM Side-Channel Leakage Mitigation in Oscillator-Based PUFs via Sampling Techniques

R. Aparicio-Téllez, J. Moore, C. Gu, M. O'Neill, M. Garcia-Bosque, S. Celma

13:20-13:40

TADA: Technology Aware DNN Accelerator Performance and Energy Estimator

Tanvi Sharma, Surya Selvam, Anand Raghunathan, Kaushik Roy

13:40-14:00

CAS: A Ferroelectric Compute-in-Memory Annealer for Sparse Combinatorial Optimization Problems

Xianmin Huang, Yucheng Cui, Yu Qian, Yuxiao Yang, Qi Sun, Xunzhao Yin

14:00-14:20

FLARE: A Dataflow-Aware and Scalable Hardware Architecture for Neural-Hybrid Scientific Lossy

Jia, Hu, Sun, Huang, Tian, Zhang, Wang, Jin, Guo, Di, Ji, Yin

14:20-14:40

UnO-NeSy: Optimizing Neuro-Symbolic Computing with Unified FeFET Based In-Memory System

Zhou, Zhu, Jiang, Mao, Zhang, Yang, Shi, Yan, Zhuo, Yin

14:40-15:00

AutoIsing: An Automated Compiler for Programmable Ising Machine

Yi Deng, Zihao Xuan, Ning Lin, Kwunhang Wong, Han Wang, Zhongrui Wang

15:00-15:20

3D-VASE: Volumetric-Aware Scalable and Efficient Multi-Layer Design Synthesis for 3D-Printed

Yushen Zhang, Jiashuo Chen, Tsun-Ming Tseng, Ulf Schlichtmann

15:40-17:40 Session 6A

15:40-16:00

A System-Level Typed-Graph Environment for Traceable Cycle-Level Co-Design of Heterogeneous AI

Zhen Wu, Yue Jiet Chong, Xuanyao Fong

16:00-16:20

CoSim: A Cross-Layer Simulation Framework for System-Hardware Co-Design of LLM Inference

Ying Gao, Jingyuan Li, Lingli Wang

16:20-16:40

MTPMoE: Exploiting Activation Skewness in Single-GPU MoE Multi-Token Prediction via Parallel Dense-Sparse

Yongkang Zhou, Jiaming Xu, Jiayi Pan, Hanzhen Wang, Tianlang Zhao, Guohao Dai

16:40-17:00

UnifyPower: A Unified Framework of Architecture-Level Power Model for Processors

Q. Zhang, Y. Lu, Y. Li, M. Li, W. Li, S. Liu, A. Mondelli, Z. Xie

17:00-17:20

Multi-modal LLM-Driven Generation of Processor Performance Simulators from Datasheet Specifications

Yang Liu, Daniel Mueller-Gritschneder

17:20-17:40

FlowMapper: Detection-Guided Topology Reconstruction of Circuit Block Diagrams

Wenbo Yan, Rongfang Wang, Changzhe Jiao

15:40-16:00

IMPACT: Constraint-Aware Search for Imperfectly Factorized Accelerator Mappings

Stavrakakis, Er, Spyrou, Stavrakakis, Wong, Gaydadjiev, Hamdioui

16:00-16:20

DSEAgent: Agentic AI Accelerator Design Space Exploration via Expert-level Reinforcement Learning

Zhuoheng Wan, Zihang Ma, Haodong Lu, Kun Wang

16:20-16:40

SymbOperon: Composable and Cost-Efficient Symbolic Reasoning Operators for Neuro-Symbolic Edge

Nimrah Saleem, Wantong Li

16:40-17:00

FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators

Shuao Jia, Zichao Ling, Chen Bai, Bei Yu, Kang Zhao, Jianwang Zhai

17:00-17:20

Hardware-Retargetable Grammar-Based NAS from Declarative Device Specifications

Moritz Reiber, Oliver Bringmann

17:20-17:40

Efficient End-to-End Hyperprior-Based Learned Image Compression on Edge GPUs via Thread-Level Parallel Entropy

Jiacheng Cao, Jiaqi Guo, Jian Wang, Huanlin Luo, Jinmei Lai

15:40-16:00

Node Reduction via Targeted ODC-Based Wire Additions for AIG Optimization

Zhuofan Lin, Shiju Lin

16:00-16:20

Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation

Jingren Wang, Guangyu Hu, Chen Chen, Heinz Riener, Shiju Lin, Hongce Zhang

16:20-16:40

DeepResub: Towards Learned Logic Optimization Operators

Dimitrios Tsaras, Yiwen Wang, Lei Chen, Zhiyao Xie, Mingxuan Yuan

16:40-17:00

aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis

Marcel Walter, Isabella Venancia Gardner, Robert Wille

17:00-17:20

PP2Tree: Learning-Guided Frontier Partitioning for Scalable Parallel Logic Synthesis

D. Tsaras, X. Li, Y. Wang, L. Chen, C. Liu, Z. Xie, M. Yuan

17:20-17:40

Placement-Aware Logic Resynthesis with Cooperative Multi-Agent Reinforcement Learning

Donghyuk Lee, Heechun Park

15:40-16:00

A Dual-Branch GAT-MLP Framework for Efficient Bump-Level Dynamic IR Drop Prediction in Flip-Chip

Wu, Chang, Pao, Chen, Peng, Hung, Li, Chang, Wang

16:00-16:20

Chiplet Assembly and Pre-Bond Qualification Planning for Heterogeneous Integrated Systems

E. Wang, A. Graening, E. Ortega, J. Talukdar, K. Chakrabarty, P. Gupta

16:20-16:40

UniCASE: A Unified 16-bit Floating Point Format with Criticality-Aware Selective ECC for Efficient DNN

Amna Hassan, Semeen Rehman

16:40-17:00

BLINK: Batch NormaLization-based INtegrity ChecKpoints for In-Situ Detection and Mitigation of Diverse Weight Corruptions in DNN

Marzia Khan, Akul Malhotra, Sumeet Kumar Gupta

17:00-17:20

Fine-Grained Compiler-Assisted Hardening via Tolerant-Output Analysis for SDC–Runtime Trade-offs

Mingtao Zhang, Tomonari Tanaka, Masanori Hashimoto

17:20-17:40

QoS Analysis for UCIe-based Cross-die Communication using Network Calculus

Chen Yang, Yuming Jiang, Zhonghai Lu

15:40-16:00

TraceMorph: Real-Trace-Guided Execution-Level Obfuscation for RAPL-Based DNN Architecture Protection

Xudong Luo, Yiwen Gao, Yuejun Liu, Yongbin Zhou, Jian Weng

16:00-16:20

DRS: Unified Fully Homomorphic Encryption Hardware Accelerator with Scheme-Switching

Kaiyuan Zhang, Antian Wang, Keshab Parhi, Yingjie Lao

16:20-16:40

Investigation of Karatsuba Algorithm for Large-Bitwidth Modular Multiplication

Bo Zhang, Xiaoyi Ye, Mingyu Gao, Mingzhe Zhang, Shoumeng Yan

16:40-17:00

Security-Aware Runtime Control for Mitigating Token-Acceptance Side Channels in PIM/3D-Memory Speculative LLM Inference

Jianfeng Wang, Tao Lei, Huazhong Yang, Xueqing Li

17:00-17:20

PFHE: Partial Fully Homomorphic Encryption on CNN Inference

Bill Dai, Jiafeng Xie, Deming Chen

17:20-17:40

Multi-Feature Demographic Decoupling via LPC Cross-Synthesis for Privacy-Preserving Audio

Nishanth Chennagouni, Alexander Santora, Qiaoyan Yu

10:00-10:20 Coffee Break

12:20-13:20 Lunch Time

15:20-15:40 Coffee Break

18:30-20:30 Banquet