Program for Tuesday, January 26th, 2027: Talk View

PROGRAM FOR TUESDAY, JANUARY 26TH, 2027: TALK VIEW

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View: with abstracts session overview

9:00

9:30

10:00

10:30

11:00

11:30

12:00

12:30

13:00

13:30

14:00

14:30

15:00

15:30

16:00

16:30

17:00

17:30

18:00

18:30

19:00

09:00-10:30 Session 1K

11:00-12:00 Session 1A

11:00-11:20

EdgeDAE: Acceleration of Diffusion Action Experts for Real-Time Physical AI with Tiny VLAs on Edge FPGA-GPU

Zhiheng Chen, Ye Qiao, Mohammad Al Faruque, Sitao Huang

11:20-11:40

CRANE: Criticality-Aware Concurrent Neural Inference on Heterogeneous Edge Platforms

Sai Teja Dasari, Gayathri Ananthanarayanan

11:40-12:00

Progressive Computation Scheduling for Deadline-Critical Tasks in Hierarchical Edge Networks

Xiaopeng Teng, Ke Jiang, Petru Eles, Zebo Peng

11:00-11:20

IMPACT: IoT SNN Inference with a Metadata-Guided Pulse-Width Control Architecture for Conductance-Time Weight Representation in

Jason Jaesung Lee, Jia Park, Seunggu Jeon, Ilhuan Choi, Woo-Seok Choi

11:20-11:40

OMNI-DC: One-shot Multi-input Neural-Inference-Based Data Converter for Analog Computation-in-Memory

Y. Zhang, Y. Biyani, S. Hemaram, A. Mahmoud, R. Bishnoi, S. Hamdioui

11:40-12:00

Observability-Aware Runtime Reliability for MZI-Based Optical Neural Networks

Michihiro Koibuchi, Shoichi Hirasawa, Hiroki Matsutani, Guangwei Cong

11:00-11:20

Fanout-Multiplicity-Aware Technology Mapping for Multi-Output Superconducting Logic

Jingkai Hong, Arda Caliskan, Ziyu Liu, Sasan Razmkhah, Massoud Pedram

11:20-11:40

Formally Verified Contract-Aware Replacement of Ready/Valid Microarchitectures

Sijing Yang, Zhengyi Zhang, Lingli Wang

11:00-11:20

Staggered Instruction-Fetch Duplication: A Lightweight Processor-Level Countermeasure Against Fault

Shoei Nashimoto

11:20-11:40

Reasoning and Modeling of Instruction Corruption of MCU under EMFI

Xunqi Ma, Ran Dong, Zhengyan Liu, Qiang Liu

11:40-12:00

Secure Reconfiguration for Multi-Tenant FPGAs

Nikhilesh Singh, Huimin Li, Mohamadreza Rostami, Lichao Wu, Ahmad-Reza Sadeghi

11:00-11:20

A Resource-Efficient Quantum Circuit for Fixed-Point Logarithm Operations with Analytical Error

Lei-Han Yao, Yu-Chung Chen, Yean-Ru Chen, Shang-Wei Lin

11:20-11:40

Scalable Quantum Circuits Partitioning via Shortest-Path Search and Circuit Transformation

Shokei Ishiura, Jion Tamamoto, Zanhe Qi, Atsushi Matsuo, Shigeru Yamashita

11:40-12:00

Reducing T-depth in quantum circuits through adaptive allocation of ancillae between T-par and

Menghan Shi, Zanhe Qi, Atsushi Matsuo, Shigeru Yamashita

12:00-13:00 Session 1S

13:00-15:00 Session 2A

13:00-13:20

Resource-Efficient Heterogeneous CGRA for Kernels with Control Flow

Hisako Ito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura

13:20-13:40

BB8: Blocking Buffer for breaking head-of-line stalling in GPGPUs via Instruction Bypassing.

Munawira Kotyad, Ganesh Sai Shanmukhi, Yashvardhan Rathore, Virendra Singh

13:40-14:00

Accelerating 5G NR Channel Estimation with a Complex-Arithmetic RISC-V Vector Extension

Zexu Tan, Emil Matus, Dmitry Utyanskiy, Pieter van der Wolf, Gerhard Fettweis

14:00-14:20

Prefix-Branch Software Co-Design for Random Forest Acceleration on Embedded Hybrid TCAMs

Yi-An Hsu, Chen-Jui Tu, Shuo-Han Chen

14:20-14:40

RobotCFU: A Tightly Coupled Multi-Operator CFU for Embedded RISC-V Robot Control

Meng Liu, Yihao Wang, Zhenkai Wang, Xiaofei Li, Guanda Zhu

14:40-15:00

A Minimal MMU for Memory Virtualization on Microcontrollers for time-sensitive applications

Leonardo Fazzini, Giacomo Valente, Luigi Pomante

13:00-13:20

CABLE: A Cached Bidirectional and Multi-lane Item Memory\\for Efficient Hyperdimensional Computing

Maxime Van Durme, Ryan Antonio, Marian Verhelst

13:20-13:40

SpikeFold: An FPGA-based Neuromorphic Processor with DSP Optimization and Parallel Weight Update

Xunqin Lai, Shanshi Huang

13:40-14:00

Nexus: Activity-Aware Capacity-Constrained Neuron Partitioning for Multicore SNN Accelerators

Yixun Liang, Yusa Wang, Zhiyi Yu, Shanlin Xiao

14:00-14:20

Cross-Layer Co-Designed In-Memory Hyperdimensional Computing Accelerator for Proteomics at the Edge

M.M.R. Nayan, Z. Li, F. Ponzina, S. Pinge, T. Rosing, A. Naeemi

14:20-14:40

Online Open-World Wafer Defect Discovery using Hyperdimensional Computing

Q. Zhao, A. Emami, T. Ide, R. Josh, S. Holmes, M. Passow, T. Rosing

14:40-15:00

Hit-SME: A High-throughput Hybrid SNN-based MLP Engine for Neural Volume Rendering

Jiayi Li, Lihua An, Ranxi Lin, Zhechen Yuan, Xin Lou, Pingqiang Zhou

13:00-13:20

CCD-KV: Exploiting High-Density 3D Charge-Coupled Device Memory for Efficient On-Device LLM KV

Palacios Almendros, Wang, Garcia Redondo, Ansaloni, Atienza, Klein, Biswas

13:20-13:40

KV3D: KV Cache-Centric Monolithic 3D-Stackable DRAM-Based Accelerator for LLM Serving

Yue Pan, Junda Chen, Zihan Xia, Mingu Kang, Tajana Rosing

13:40-14:00

DeferKV: Long-Context LLM Attention Acceleration with Per-Token Scale Folding and Bank-Local Softmax on

Rui Wan, Tianlang Zhao, Shulin Zeng, Yu Wang, Guohao Dai

14:00-14:20

CRISP: Paged Sparse Attention on DRAM-PIM with Row-Band-Aware KV Allocation and Frame-Derived

Rui Wan, Tianlang Zhao, Shulin Zeng, Yu Wang, Guohao Dai

14:20-14:40

A Waferscale Memory Architecture for Efficient LLM Inference

Shuangliang Chen, Pavan Kumar Hanumolu, Saptadeep Pal, Rakesh Kumar

14:40-15:00

LUMEN: A Compressed-LUT-based Processing-Near-Memory Architecture for Efficient LLM Inference at the

Zhu, Wu, Qin, Pan, Shi, Zhang, Yu, Yao, Tang, Gao, Qian, Wu

13:00-13:20

CertIR: Certified Static IR-Drop Estimation with Physics-Anchored Neural Correction

Chang Liu, Jiaming Chang, Min Wei, Peng Zou, Jianli Chen, Kun Wang

13:20-13:40

PDN-Aware Graph Transformer-based Dynamic IR Drop Prediction with Criticality-Guided Subgraph

Qianlin Lu, Shuoqiu Wang, Bowen Zhang, Pengcheng Fan, Qiao Hua, Peng Cao

13:40-14:00

Cross-Layer Reinforcement Learning for Power-Via Optimization in Multilayer RDL Power/Ground Plane

Shang-Che Lee, Mark Po-Hung Lin

14:00-14:20

Power Network Topology Optimization for Top Dies in Backside-Powered F2F 3D ICs

Gyumin Kim, Heechun Park

14:20-14:40

Grad-BSS: Differentiable Optimization for Full-Stack Backside Signal Routing

Amaan Rahman, Min Gyu Park, Sandra Shaji, Sung Kyu Lim

14:40-15:00

Clock Distribution Network with Backside Clock Mesh in BSPDN Architecture

Seohyun Kim, Youngjin Chae, Shilong Zhang, Youngsoo Shin

13:00-13:20

Decompose Transform Refine Verify: A new approach for scalable formal verification

Saumya Jaipuria, Ansuman Banerjee, Raj Kumar Gajavelly

13:20-13:40

GAS: GPU Accelerated Schema Aware Exact Subcircuit Matching for Large-Scale Circuits

J. Tu, B. Qi, Y. Li, B. Xie, P. Li, T. Wu, Z. Di, T. Chen

13:40-14:00

From DRAM Architecture to Protocol State: A Resource-Grounded Executable Semantics for LPDDR5

Jie Tang, Yanfeng Li, Wang Zhan, Dandan Shi, Qin Chen, Hao Wang, Sihai Zhang

14:00-14:20

SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow

Liangtao Dai, Yimin Gao, Melika Morsali, Mircea Stan

14:20-14:40

Adaptive BTOR2 Reformulation via Solver-Aware Equality Saturation

Jiaying Zhu, Zhengyuan Shi, Min Li, Qiang Xu

14:40-15:00

FormalPCell: Formal DRC Verification of Parameterized Layout Cells via Symbolic Interpretation and SMT

Yuhan Qin, Yuan Pu, Zhuolun He, Bei Yu

15:20-17:20 Session 3A

15:20-15:40

ATLAS: A Thermal-Aware 3D-Stacked Heterogeneous Architecture For LLM Multi-Turn Dialogue Serving

Yifan Ding, Qianxu Wang, Keyi Ji, Dunshan Yu, Tianyu Jia

15:40-16:00

Cross-Bank ECC Strategy for LLM-Oriented Hybrid-Bonded 3D DRAM Architecture

X. Yu, T. Xie, Y. Zhu, Y. Xi, G. Dai, H. Yang, Y. Xie, Z. Zhu, Y. Wang

16:00-16:20

TACO: Topology-Aware Compression via Hardware–Software Co-Design for Robust CiM-Accelerated Edge RAG

Yuanjie Zhang, Kachun Wong, Zheyu Yan

16:20-16:40

Multi-Agent LLM Serving with SSD-Based KV-Cache Offloading

Yu-Chen Lee, Chih Yen Chen, Ming-Yi Kuo, Yun-Chih Chen

16:40-17:00

TreePIM: A Heterogeneous Processing-in-Memory Architecture for Tree-based Speculative Decoding

Jiamu Fu, Guanghong Wu, Zhiheng Yue, Ruiqi Guo, Yang Wang, Yang Hu, Shouyi Yin

17:00-17:20

PSD-CIM:A Computing-In-Memory Attention Accelerator with Predictor-Free Sparsity search and Distribution

Tong Li, Zhiwei Zhou, Jiancong Li, Jia Chen, Yi Li, Xiangshui Miao

15:20-15:40

CalNet: Temperature-Robust ADC Calibration via Learned BGR Behavior and LUT Correction

Woo, Kim, Lee, Oh, Kim, Jeon, Hwang, Seo, Lee, Kang

15:40-16:00

ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided

Osei W Brempong Jnr, Mohammed Ayman Habib, Vivan Poddar, Morteza Fayazi

16:00-16:20

APPlace: Co-Optimizing Device Locations and Access Points for Routing-Aware Analog Placement

Bingyang Liu, Xiaohan Gao, Souradip Poddar, David Z. Pan

16:20-16:40

An Explainable Analog/Mixed-Signal Routing Agent using Deterministic Constraint-Conflict Diagnosis

Hyungjoo Park, Donghyun Lee, Jaeduk Han

16:40-17:00

CktHVR: A Convergence-Aware GNN-VLM Hypothesize-Verify-Refine Framework for Analog Circuit Topology

Huiyao Xu, Chengjie Liu, Weiyu Chen, Bo Li, Zhijun Li, Jun Yang

17:00-17:20

LMSACO: LLM-Guided Multi-Objective State-Adaptive Analog Circuit Sizing Optimization

Ying Hu, Guojing Ge, Xian Rong Qin, Yong Zhang, Ning Xu, Bo Wen Jia

15:20-15:40

ACED: An Algorithm–Hardware Co-Designed VLA Accelerator Exploiting Dynamic Weight-Precision

Wu, Zhu, Pan, Qin, Shi, Zhang, Yu, Yao, Tang, Gao, Qian, Wu

15:40-16:00

ActRAM: A Hybrid Analog/Digital Action-Expert Accelerator Architecture for Vision-Language-Action

Pan, Shi, Zhu, Qin, Wu, Li, Zhang, Yao, Tang, Gao, Qian, Wu

16:00-16:20

HB-VGGT: Exploiting Head-Wise Complementary Redundancy for Efficient VGGT Inference on Hybrid-Bonded

N. Shang, G. Li, J. Yao, H. Yang, X. Guo, Y. Ma, L. Ye

16:20-16:40

CoD-MiCo: Co-Design of Mixed-Compression RISC-V Extensions for Neural Networks on FPGAs

Batuhan Sesli, Muhammed Sabih, Frank Hannig, Jürgen Teich

16:40-17:00

Enabling Energy-Efficient TinyML Inference via Fused Tensor Architecture

Dongliang Xiong, Zaihe Zhang, Huibo Gao, Jinnuo Yu, Zimo Wang, Kai Huang

17:00-17:20

Taming Irregular Sparsity with a Regular Systolic Array for Efficient DNN Training

Jiangwen Chen, Jingbo Jiang, Xiaomeng Wang, Xizi Chen, Chi-Ying Tsui

15:20-15:40

NaCo3D: Native and Compact 3D Floorplanning via Reinforcement Learning

Kaixuan Sun, Biao Liu, Bo Yuan

15:40-16:00

A Two Stage Learning-Based Thermal-Aware Framework for 3D Fixed-Outline Soft-Module Floorplanning across Chip

Jiayi Li, Yikai Liu, Jindong Zhou, Lihua An, Pingqiang Zhou

16:00-16:20

MoL-PAM: Joint P/G TSV Planning and Macro Refinement for Memory-on-Logic 3D ICs via a Benders-Type Decomposition

Jiang, Zhao, Zhuang, Liu, Lu, Ji, Shi, Chen, Ho, Lin, Yu

16:20-16:40

XCTS: Cross-Tier-Aware Differentiable Clock Tree Synthesis for 3D Integrated Circuits

Han Zhang, Xilin Qian, Junming Jiao, Peng Cao

16:40-17:00

A Comprehensive Clock Tree Synthesis with Useful Skew for 3D ICs

Geonhyeong Park, Ikkyum Kim, Heechun Park

17:00-17:20

Operation-Aware Twisting of Folded Bit-Lines for Crosstalk Cancellation in Wafer-Bonded DRAM

Myungjun Kook, Seokhyeong Kang

15:20-15:40

Sample-Efficient Neural Compact Modeling for Design-Technology Co-Optimization Based on Process-Aware

L. Lyu, G. Fan, J. Shen, L. Li, Y. Yi, X. Zhu, Z. Wang, L. Shao

15:40-16:00

Timing-Aware Routing and Heterogeneous TDM Assignment for Multi-Level FPGA-Based Emulation Systems

Y. Chen, C. Pei, J. Zhai, S. Song, H. Weng, J. Shen, K. Zhao, W. Yu

16:00-16:20

Spec2Plan: An LLM-Powered Framework for Comprehensive Verification Plan Generation

Tseng, Chen, Yen, Chen, Pan, Hsieh, Huang

16:20-16:40

Towards Leveraging the Software Ecosystem to Facilitate Hardware Verification

Liu, Yao, Xie, Wang, Chen, Song, Yang, Shi, Wang, Bao

16:40-17:00

Functionality-Aware Is Not Synthesis-Invariant: An End-to-End Audit of Circuit-GNN Representations

Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu

17:00-17:20

ML-AccelBench: A Benchmark for Evaluating LLM-Based ML Accelerator RTL Generation

Jayanth Thangellamudi, Raghul Saravanan, Sai Manoj Pudukotai Dinakarrao

17:40-19:10 Session 2S

10:30-11:00 Coffee Break

12:00-13:00 Lunch Time

15:00-15:20 Coffee Break