ABSTRACT. Physical AI models such as Vision-Language-Action (VLA) archi- tectures enable generalist robotic policies through large-scale trans- former backbones and diffusion-based action decoders. While edge GPU platforms excel at parallelizing the compute-intensive vision- transformer workloads, they exhibit fundamental limitations for the Diffusion Action Expert (DAE) module: the iterative denoising process requires repeated parameter loading from DRAM across multiple steps, resulting in memory-bound performance where the GPU’s massive computational throughput remains underutilized. This mismatch between DAE’s I/O-intensive characteristics and GPU’s compute-centric architecture motivates a heterogeneous acceleration approach. This paper presents EdgeDAE, a heteroge- neous FPGA-GPU system that strategically partitions workloads based on computational characteristics. We offload the perception- heavy vision-transformer to GPU while accelerating DAE infer- ence on FPGA through complete on-chip parameter storage in BRAM/URAM. This architecture eliminates the memory bottleneck by co-designing quantization strategies, fixed-point arithmetic, and hardware-efficient random number generation for the FPGA fabric. Compared to an edge GPU baseline, EdgeDAE reduces end-to-end inference latency by 52.5% for Octo-Small and 38.7% for Octo-Base, with up to 2.10×higher throughput; compared to a consumer GPU (RTX 4090), it achieves ∼17×higher energy efficiency

ABSTRACT. Edge AI platforms for autonomous vehicles, drones, and surveillance systems run multiple deep neural network (DNN) inference services concurrently on heterogeneous hardware combining CPUs, an integrated GPU, and VPU accelerators with isolated memory pools. Efficiently sharing these resources across workloads of differing urgency (eg. collision avoidance, lane detection, background telemetry) remains an open challenge. Existing inference serving systems ignore criticality semantics, treat all inference tasks equally, concentrate the load on accelerators, leave the CPU cores idle, and ignore the impact of unified DRAM bandwidth shared by CPU and GPU. We present \textbf{CRANE}, an adaptive scheduling framework that combines mixed-criticality scheduling principles with multi-objective device scoring across latency, power, accuracy, and temperature to distribute inference workloads across all available accelerators while protecting high-priority tasks through cooperative preemption and overrun migration. We implement and evaluate the proposed framework on an Intel UP Squared Pro platform (consisting CPU, GPU and dual VPU) using six CNN models on CIFAR-100 dataset under Poisson and bursty arrival modes. Under a $1.5\times$ stress load, CRANE completes $2.1$--$3.1\times$ more jobs than a GPU-first baseline while achieving a \emph{lower} HIGH-criticality miss rate, 35.2\% vs.\ 42.2\% , and is $2.5$--$3.7\times$ more energy-efficient per job. An ablation study shows that device scoring and preemption alone are insufficient (84.8\% miss rate) and that adding mode switching with INT8 overrun migration is the critical enabling mechanism, dropping the miss rate to 17.3\%.

ABSTRACT. We study online scheduling for deadline-critical tasks in hierarchical edge networks. In many applications, a task is uploaded along a predetermined route, where each node computes part of its remaining workload. As computation progresses, the transmitted payload becomes smaller, reducing the upstream communication load. However, performing more computation at nodes with limited computation resources may also introduce extra delay. Balancing computation and communication load is therefore a key challenge. To address this challenge, we propose a distributed online scheduler, Queue-Guided Distributed Progressive Scheduling (QDPS). At each node, QDPS locally determines the computation workload using the local queue state and estimations of the upstream queue states. Experimental results show that QDPS achieves a high deadline satisfaction ratio with synthetic tasks and networks as well as with realistic applications and devices.

ABSTRACT. The ubiquity of Internet of Things (IoT) devices demands energy-efficient on-device inference for tasks such as image classification and keyword spotting. Spiking neural networks (SNNs) computed in analog Resistive RAM (RRAM) crossbars promise excellent energy efficiency, but representing multi-bit weights with conductance alone requires many tightly spaced conductance states, which are difficult to program reliably under cell-to-cell variation. This paper presents IMPACT, an IoT SNN inference architecture with metadata-guided pulse-width control for conductance-time weight representation in RRAM. IMPACT factorizes each synaptic weight into a three-level RRAM conductance factor and a reference-derived pulse-width-modulation (PWM) duration factor, so that the effective weight magnitude is the conductance-time product. A per-cell 2-bit metadata code, stored in a small SRAM and expanded locally into slot-wise column masks, enables weight-dependent, column-wise PWM-duration selection. A hardware-aware, layer-wise quantization and mapping flow adapts software-trained models to the supported weight set. Across CIFAR-10, MNIST, and GSCDv2, the mapped models remain within 2.15 percentage points of the ANN software baselines. With all metadata and control support included in the energy model, IMPACT reaches peak efficiencies of 240.1, 113.2, and 206.4 TOPS/W, improving energy efficiency by up to 6.08× on CIFAR-10 and 9.14× on GSCDv2 over prior RRAM-CIM baselines.

ABSTRACT. Compute-in-memory (CIM) paradigm offers a promising solution to the memory-wall bottleneck in conventional processor-centric architectures. However, the performance of the CIM architecture is currently limited by peripheral circuit design, particularly the analog-to-digital converters (ADCs), which account for the majority of the total area and energy consumption of a CIM macro. In this paper, we propose a novel neural-network-based peripheral design for CIM architectures to mitigate ADC overhead. We reformulate the ADC computation process as a neural network (NN) learning problem and introduce Natural Palindromic Coding (NPC) to help improve the learning efficiency and reduce the training loss during learning. Further, our proposed design supports multi-column inputs and directly generates the final digital output, significantly reducing the need for extra multiplexing and shift-add circuitry, thereby improving the overall throughput and energy efficiency of the system. Our proposed design achieves substantial improvements in both energy and latency, providing up to 17.6× reduction in energy consumption per conversion step and up to 13× reduction in multiplexing latency overhead. Furthermore, system-level evaluation shows that, with 4-bit weights and activations, the proposed design achieves near baseline accuracy of 98.72% on MNIST and 88.20% on CIFAR-10 benchmarks, respectively

ABSTRACT. Mach-Zehnder interferometer (MZI)-based optical neural networks are promising for efficient inference, but runtime reliability is challenged by heterogeneous errors. Sparse output corruptions, persistent MZI drift, and temporary coherent MZI-level errors have different observability properties. This paper proposes a runtime error-management framework that combines two-column algorithm-based fault tolerance (ABFT) for sparse output correction, periodic Freivalds-style random projection checks for persistent drift monitoring, and event-triggered retry with xPU fallback for temporary coherent errors. The framework separates lightweight online correction, independent matrix-level monitoring, and verified recovery, providing a layered runtime reliability stack for MZI-based ONNs. Across four workloads, the framework restores accuracy to within 0.15 percentage points of clean execution, with (0.45)-(1.52%) retry and at most (0.21%) xPU fallback under the evaluated fault stream.

ABSTRACT. In emerging technologies, such as superconducting logic circuits, where signal duplication requires explicit splitter cells, fanout is an area and delay cost that technology mapping must account for. Some emerging multi-output cells expose multiple physical output pins, each configurable to a function drawn from a small pool. A pin not needed for a distinct function can instead carry a duplicate copy of a function the cell already produces, supplying one fanout at no splitter cost. This makes output multiplicity a resource that trades against the splitter network. We model configurable output pins as a native fanout resource that absorbs part of the fanout before any splitter is charged. We integrate this cost into multi-output technology mapping so that the Boolean cover and the output-pin configuration are selected together. We also support a delay-first objective that builds the splitter forests explicitly during timing evaluation. On the EPFL combinational benchmarks mapped to superconducting pulse-conserving logic, our mapper reduces area by 9.70\% and critical-path delay by 12.30\% in geometric mean over a multi-output mapping baseline.

ABSTRACT. Conventional logic synthesis preserves cycle behavior even when a ready/valid connection requires only an ordered token stream. We present HandshakeSuper, a template-based post-RTL replacement flow for single-channel transport blocks. It filters elastic pipelines, fall-through buffers, skid buffers, and register FIFOs using explicit capacity, no-stall latency, throughput, ready-path, and service-window contracts, then proves token safety and bounded recovery after arbitrary stall histories. A rendezvous miter permits reference and candidate to accept and produce the same logical tokens in different cycles; IC3/PDR discharges every accepted replacement unboundedly. Composition is valid for well-formed, stall-insensitive endpoints whose external structural contract is sound, a boundary we state explicitly. Across 56 scenarios from 4 pinned open-source projects, area, delay, and vectorless cell power improve in 39/56, 18/56, and 32/56 cases, with the original RTL retained on no win. All 448 properties for 224 candidates are proved. In a stateful packet-pipeline integration, whole-system proof confirms a cycle-different AXIS transport replacement and mapped area, delay, and power fall by 44.1%, 5.4%, and 41.3%. The artifact includes stage-level runtime and complete reproduction scripts.

ABSTRACT. Fault attacks exploit transient hardware faults to bypass software-level security checks in embedded processors. Processor-level redundancy can detect such faults, but duplicating the whole processor is costly for resource-constrained devices. This paper proposes Staggered Instruction-Fetch Duplication (SIFD), a lightweight processor-level countermeasure based on instruction-fetch redundancy. SIFD fetches each instruction twice in consecutive cycles, while fetching two different instructions in every fetch cycle. This staggered schedule detects inconsistent fetch results without full processor duplication, compiler support, or cryptographic hardware. We implement SIFD on a custom RV32I processor and evaluate it on an Artix-7 FPGA using clock fault injection (CFI) and electromagnetic fault injection (EMFI). SIFD increases slice utilization by 15.0\% and execution time by 16.3\%. It reduces the attack success rate from 0.86\% to below 0.01\% under CFI and from 0.32\% to 0.13\% under EMFI. It also detects 73.18\% of CFI attempts and 11.44\% of EMFI attempts. These results indicate that SIFD can convert many fault effects into explicit detections and reduce successful fault-injection outcomes, especially under CFI.

ABSTRACT. Electromagnetic fault injection (EMFI) is an effective technique for inducing transient faults in microcontrollers. Existing studies mostly describe instruction-level fault effects such as skip, replay, and corruption at the behavioral level, but how such faults are generated and the underlying mechanism remains poorly understood. In this work, we investigate ARMv7‑M microcontrollers and systematically reveal how EMFI‑induced bit flips in instruction codes can give rise to various instruction corruptions. We design an automatic reconstruction framework that analyzes the collected fault data, reconstructs the candidate instructions that may be executed after the fault, and verifies their execution. Based on the reconstruction result, we build a bit‑level fault model that unifies conventional behavioral fault phenomena, including instruction skip, replay, and register corruption. Moreover, the periodic temporal distribution of the faults and a Flash‑versus‑SRAM execution control experiment provide strong evidence that the physical origin of these faults lies in the 128‑bit instruction‑line buffer fetch path of the Flash/ART accelerator. We also demonstrate that the corrupted instructions can lead to real security vulnerabilities. The proposed fault model established in this work can serve as a foundation for designing countermeasures of MCUs against EMFI.

ABSTRACT. FPGA-as-a-Service platforms virtualize FPGA fabrics for efficiency, but their security contracts are weak. Cloud providers must ensure that uploaded bitstreams are safe, while clients demand confidentiality for their proprietary designs. Existing solutions privilege one side only, rely on ad hoc mechanisms, and lack portability. We propose SENTRY, a framework that treats partial reconfiguration as a policy-enforced control plane within a trusted execution environment (TEE). SENTRY confines bitstreams to TEE-protected memory, inaccessible to providers and co-tenants, while a TEE-resident validator authenticates clients and enforces bitstream safety on-the-fly, balancing the needs of both parties. SENTRY scales across virtual machines (VMs) on a hypervisor, requires no vendor-specific register transfer level (RTL) changes, and is realized end-to-end on the AMD ZCU102 with open portable TEE (OP-TEE). Our evaluation shows that SENTRY thwarts six potent adversarial threat classes at the configuration boundary, spanning representative MITRE CAPEC attack patterns and CWE weakness families, including unauthorized access, replay, and integrity violations. It limits the added configuration latency to 15.3% and adds no runtime overhead.

ABSTRACT. Quantum circuits for logarithm operations are essential building blocks for scientific computing and quantum algorithms. To achieve O(2^-F) bounded error, where F is the decimal point precision in bits, existing quantum circuit designs require complexity of O(F^2 lg(F)) in width and complexity of O(F^3 lg(F)) in depth. There does exist a lower-complexity design with complexity O(F^2) in width and O(F^3) in depth, but it lacks an error bound analysis. This paper proposes a resource-efficient quantum circuit construction for logarithm operations of positive fixed-point inputs. Using a leading-zero counter and a shifter, the proposed circuit construction extracts the integer characteristic and normalizes the remaining computation to approximate the fraction. The circuit construction for the fractional part consists of: (1) M rounds of range reduction based on square root, and (2) an Taylor expansion of N terms in Horner-form. This design enables a tunable trade-off to avoid unnecessary circuit overhead. We further analyze how the values of M and N affect the constructed quantum circuit in terms of resources needed and errors. For F fractional output bits, choosing M=N=Theta(F^0.5), the proposed circuit construction achieves O(2^-F) bounded error with complexity O(F^1.5) in width and O(F^2.5) in depth. Experimental results also validate our theoretical claims.

ABSTRACT. Executing large-scale quantum circuits on NISQ devices requires quantum circuit partitioning. However, as the number of gate cuts and wire cuts grows, the sampling overhead required to reconstruct the original circuit’s result increases exponentially. Existing SMT-based methods can search for the optimal partition that minimizes sampling overhead, but on large and dense circuits the explosion of the search space inflates their runtime, making them difficult to apply. In this work, we formulate quantum circuit partitioning as a shortest-path problem and use Dijkstra’s algorithm to search for high-quality partitions scalably. Our method represents wire cuts and gate cuts as edges of a graph and treats the sampling overhead of each cut as an edge cost, so that the minimum-overhead partition is obtained as a shortest path. Furthermore, in addition to optimizing qubit placement as existing SMT-based methods do, we introduce time-division, which splits the circuit along the time axis and allows different placements in different segments, together with circuit transformation via reordering of commutable gates, thereby enabling partition optimization that accounts for the circuit structure that prior methods held fixed. In an evaluation on 60 QAOA MaxCut circuits, our method obtained solutions quickly for all circuits, including 20-qubit fully-connected circuits on which SMT timed out.

ABSTRACT. T-par is an effective optimization technique for reducing T-depth in fault-tolerant quantum circuits (FTQCs). However, since Hadamard (H) gates change the computational basis, phase polynomial optimization cannot be applied across H gates, forcing a circuit to be divided into multiple independent optimization regions. Consequently, T-par optimizes each region independently, leaving potential cross-region optimization opportunities unexplored. We observe that, even after T-par optimization, each region often retains residual parallelism, where additional T gates can be scheduled without increasing the local T-depth. This observation indicates that further T-depth reduction can be achieved by migrating T gates from later regions into the residual capacity of preceding regions when their dependencies allow. In this work, we propose a unified optimization framework that integrates T-par with H-gadgets to enable T-gate migration across H gates. By replacing selected H gates with H-gadgets, the proposed method removes basis-change barriers and exploits the residual parallelism of preceding regions to reduce the T-depth of later regions without increasing the T-depth of preceding regions. Since H-gadgets require additional ancillae and practical FTQCs have limited ancilla resources, we formulate an ancilla-constrained optimization problem that jointly determines H-gadget insertion, ancilla allocation, and T-gate migration to minimize the overall T-depth. Experimental results demonstrate that, compared with T-par alone, the proposed method achieves an average T-depth reduction of 23.0% and a maximum reduction of 42.9%.

ABSTRACT. Coarse-grained reconfigurable architectures (CGRAs) have attracted attention as accelerator platforms that balance flexibility, energy efficiency, and computational performance through word-level reconfiguration. Recent studies have demonstrated the effectiveness of executing entire kernels, including control flow, on PE arrays for practical applications containing branches and loops. Although this approach enables large program regions to be offloaded, it uniformly maps basic blocks with different execution frequencies and degrees of parallelism onto spatial resources, leaving room for improvement in PE utilization.This work proposes a heterogeneous CGRA incorporating PEs capable of time-multiplexed execution for kernels whose control structures can be statically analyzed. Rather than spatially mapping every region of a kernel onto dedicated PEs, the proposed architecture executes selected regions in a time-multiplexed manner to utilize computational resources more effectively. We also propose a compilation method that facilitates mapping while accounting for time-multiplexed execution, as well as a design-space exploration method that determines an appropriate PE configuration for a given set of target applications. Evaluation results demonstrate that the heterogeneous CGRA designed using the proposed methods improves both performance and area efficiency while reducing computational resources compared with conventional spatially mapped CGRAs.

ABSTRACT. Graphics Processing Units (GPUs) are widely used to accelerate scientific and general-purpose applications due to their high throughput. However, many workloads exhibit limited parallelism and frequent long-latency operations, resulting in issue stalls and underutilization of available execution resources. Strict in-order issue within a warp means that a single stalled instruction at the head of an issue buffer blocks all subsequent, potentially ready, instructions in that warp from issuing. This head-of-line (HOL) blocking leaves substantial instruction-level parallelism (ILP) unexploited and degrades issue-stage utilization. We propose the Blocking Buffer, a lightweight, non-speculative microarchitectural extension to the warp scheduler that temporarily removes stalled head instructions from the issue buffer, allowing the scheduler to bypass them and issue younger ready instructions. Our approach increases instruction-level parallelism, reduces pipeline idle time, and improves overall execution efficiency without requiring the complexity of conventional out-of-order processors. Evaluated using Accel-Sim across a diverse set of benchmarks, our implementation with an eight-entry Blocking Buffer (BB8) achieves a geometric mean IPC speedup of 20.66% over an Nvidia A100 baseline, with up to 69.10% maximum speedup and an overall stall reduction of 17.5%. The proposed design achieves these performance gains while incurring a minimal hardware overhead of less than 0.042% of the A100 die area.

ABSTRACT. The evolution of 5G New Radio (NR) drives wireless baseband processing (WBP) toward programmable, energy-efficient platforms that enable virtualized RAN. The RISC-V Vector extension (RVV 1.0) fits WBP well, since PHY kernels such as channel estimation and MIMO detection are dominated by regular, variable-length data parallelism (across subcarriers, antennas, and OFDM symbols) that matches RVV's vector-length-agnostic model and is exploited portably across hardware vector widths. As a general-purpose ISA, however, RVV lacks native complex-valued arithmetic, which is common in these kernels, thereby constraining their throughput. We present CExt, a lightweight complex-arithmetic extension to RVV 1.0, operating directly on interleaved in-phase/quadrature (I/Q) vectors and implementing complex multiply and multiply-accumulate as single instructions. The CExt instructions occupy reserved opcodes, preserving the standard RVV programming model and portability while incurring negligible decode overhead. We integrate CExt into the Saturn RVV processor and evaluate it using a 2D Wiener filter-based 5G NR channel estimation kernel, comparing it against the baseline RVV 1.0 implementation. Synthesized in a 16 nm technology node at 1 GHz, CExt incurs only a 1.51% area overhead. For 4×4 MIMO, CExt achieves a 1.46× speedup, thereby meeting the LTE high-end and 5G NR FR1 transmission time interval (TTI), with 46.0% higher throughput and 8.1% better energy efficiency.

ABSTRACT. The irregular, non-deterministic memory access patterns of random forest models make them ill-suited for von Neumann architectures, where constant data movement between memory and processors severely limits throughput and energy efficiency. To resolve such inefficiency, processing-in-memory (PIM) approaches using ternary content-addressable memory (TCAM) have been explored to address this challenge by mapping decision paths directly onto memory arrays. However, existing designs that fully enumerate all paths onto TCAM incur substantial area overhead and quickly exhaust limited on-chip resources, particularly problematic for embedded Internet of Things (IoT) platforms with limited memory size. Such an observation motivates this paper to propose a shared-prefix factoring (SPF) scheme, a software–hardware co-design framework for accelerating random forest inference on a hybrid 2.5T1R and 3-bit-per-cell TCAM accelerator, specifically designed for embedded environments with demanding area and time-sensitive constraints. Instead of mapping every decision path, the SPF scheme exploits prefix sharing across tree branches to store common prefixes only once, substantially reducing redundant entries. Furthermore, the SPF scheme prunes unnecessary comparisons when decisions become deterministic, minimizing both access latency and switching energy. By jointly optimizing data placement and hardware utilization, the proposed co-design enables efficient large-scale random forest inference on memory- and power-constrained embedded systems. Experimental results demonstrate that the SPF scheme achieves an average 95.78% reduction in area and 87.34% reduction in energy consumption compared with the prior path-mapping method on 2.5T1R TCAMs, while delivering 2.16x the throughput of GPU-based inference.

ABSTRACT. Emerging humanoid robotic systems, particularly robot control applications, rely heavily on elementary mathematical functions, whose software execution remains a major bottleneck on lightweight RISC-V processors. This paper proposes RobotCFU, a tightly coupled multi-operator Custom Functional Unit (CFU) integrated into the execution stage through custom ISA extensions to accelerate elementary mathematical functions. By exploiting cross-function datapath sharing, SIMD execution, and function fusion, the proposed architecture significantly improves computational throughput while maintaining low hardware overhead, enabling configurable hardware-performance trade-offs for lightweight RISC-V processors. Experimental results demonstrate that the proposed CFU achieves an average speedup of 22.52× over the software baseline for elementary mathematical functions and 17.5× speedup for representative application workloads, with 10.3% LUT overhead compared with the baseline processor.

ABSTRACT. The growing number of time-sensitive applications in safety-critical embedded systems, together with the need to keep system costs under control, is pushing their consolidation onto a few microcontroller platforms. Consolidation requires isolating each application and avoiding the recompilation of already verified code, as a new build may require its re-verification. To this end, virtualization enables the consolidation of multiple applications, allowing them to run in isolation on the same platform, without the need to rebuild any of them. A virtualization solution commonly achieves this by providing CPU, memory, and I/O virtualization. In this context, memory management units are the standard mechanism for memory virtualization. However, due to their unpredictable timing behavior, microcontroller platforms that require predictable execution of applications typically do not include memory management units. The current state of the art proposes approaches to consolidate several applications on a microcontroller platform. However, all these approaches, although ensuring isolation, require rebuilding of applications, which in turn causes re-verification and ultimately impacts design-time costs. This paper solves this problem by proposing the m-MMU, a hardware component composed of a set of relocation regions, which enables memory virtualization on microcontroller platforms without impacting the timing predictability of the platform. We design the component and describe its use in a virtualization solution, showing that the m-MMU use allows each application to be consolidated without recompilation, while still guaranteeing its isolation. We instantiate the solution on a RISC-V-based microcontroller platform (Ibex) hosting a virtualization solution. Each m-MMU relocation region requires 62 FFs and about 130 LUTs, and the maximum core frequency drops from 59.5 to 51.5 MHz when using the proposed m-MMU with a maximum of 12 regions. With two applications consolidated on the same core, the m-MMU adds only a 0.08% increase in end-to-end execution time, while ensuring their isolation without any need for recompilation.

ABSTRACT. Hyperdimensional computing (HDC) is a brain-inspired paradigm for ultra-low-energy edge inference. However, the projection stage, mapping low-dimensional features to hypervectors (HVs) via item memories (iMs), remains an efficiency bottleneck. This stems from two factors: state-of-the-art iMs trade off large-area single-cycle ROM (40–60% of design) against slower multi-cycle CA90 generation (up to three orders of magnitude slower latency); and existing iMs support only single-HV access, dominating 90% of the encoding time. This work presents CABLE, a cached, bidirectional, multi-lane item memory enabling high-bandwidth, on-the-fly multi-HV generation in a single cycle. The architecture uses a shared cache with most-recently-used (MRU) arbitration across multiple lanes, supporting orthogonal and continuous iMs with bidirectional generation to reduce miss latency. CABLE achieves 1.9× lower latency than a ROM, and 1,500× than bare CA90 generation at the cost of 20× CA90's area but 2× less than ROM, yielding 2–5× lower latency and up to an order of magnitude higher energy efficiency across HDC classification tasks. CABLE thus enables high-bandwidth, near-single-cycle multi-HV access for efficient HDC projection and encoding.

ABSTRACT. Conductance-based leaky integrate-and-fire (COBA-LIF) neuron provide richer synaptic dynamics, but their governing differential equations incur substantial arithmetic overhead on FPGAs. More over, the bidirectional synaptic-weight accesses required by STDP introduce additional memory-access cycles. To address these chal lenges, this paper presents SpikeFold, an FPGA-basedneuromorphic processor supporting COBA-LIF inference and on-chip learning. SpikeFold efficiently maps the complex neuronal dynamics onto DSP slices and decomposes postsynaptic updates into row-level jobs that are executed during otherwise idle cycles. Implemented on a Xilinx ZCU102 at 100 MHz, SpikeFold reduces the LUT, FF, and DSP usage of excitatory neurons by up to 18.7%, 36.7%, and 50%, respectively. Meanwhile, the proposed scheduling mechanism reduces learning cycles by up to 40.9% while preserving the causal ordering of STDP updates.

ABSTRACT. As the scale of Spike Neural Networks (SNNs) grows, the number of neurons, synapses, and state variables in SNNs increases rapidly, requiring to map them on multicore neuromorphic hardware accelerators for processing, and the quality of SNN mapping is related to the previous neuron partitioning. Under strict per-core SRAM capacity limits, neuron partitioning algorithms must avoid overloaded cores while reducing off-chip accesses for highly active neurons and limiting inter-partition spike communication. This paper presents Nexus, a fast, activity-aware and capacity-constrained neuron partitioning algorithm for SNN hardware deployment. Nexus uses neuron firing rates to estimate memory access pressure and prioritizes active neurons for SRAM, reducing DRAM access and total storage energy costs under hardware capacity constraints. Meanwhile, Nexus partitions neurons following the network topological order, preserving local connectivity and controlling cross-partition communication. Experiments on representative SNN models show that compared with other partitioning algorithms like METIS, Nexus improves storage performance, reduces communication costs and maintains suitable runtime under the same hardware constraints.

ABSTRACT. Database (DB) search and clustering are fundamental to data-analytics workloads such as mass spectrometry-driven proteomics. Current workflows rely on resource-intensive search and re-clustering, often offloaded to the cloud, raising privacy concerns for sensitive biological data. In this work, we enable efficient and privacy-preserving interaction on low-resource hardware platform through a cross-layer co-design approach. At the algorithm level, we propose a hardware-friendly data driven incremental update mechanism while preserving nearly the same proteomics outcome, eliminating costly repeated re-clustering during database updates. Performing cluster expansion directly during similarity search maps the algorithm naturally onto content-addressable memory (CAM), fusing distance computation and cluster expansion into one in-memory operation and eliminating dedicated distance units and data movement. This enables reduced footprint making a compact CAM-based accelerator feasible. We exploit bucket-wise search to scale and parallelize by mapping spectra buckets to CAM arrays to serve large dataset and maximize throughput, respectively. Bucket cache and main memory enables mapping datasets of different scales. Experimental results show a $\approx20\times$ algorithmic speedup over re-clustering with only $0.3\%$ additional error and $96\%$ DB search overlap with state-of-the-art(SOTA) methods. Bucket-wise parallelization enables $\approx100\times$ further acceleration over sequential search. The hardware implementation with $24.4MB$ SOT-MRAM CAM with $2.5MB$ bucket cache sustains $3.21\mu\text{J}$ per $1\text{K}$ queries and $263.8\mu\text{s}$ maximum latency on a $131GB$ human proteome dataset.

ABSTRACT. Traditional wafer defect analysis relies on offline, closed-world classifiers that fail to detect novel, unseen defect signatures emerging during continuous semiconductor manufacturing. To address this, we propose WaferHDC, an online open-world wafer defect discovery framework based on hyperdimensional computing (HDC). The memory-centric architecture of WaferHDC enables rapid anomaly detection and grouping of recurring failures into compact hypervector representation. This allows the memory space to dynamically scale with new defect modes without retraining a static classifier or archiving entire raw wafer history. WaferHDC initially models normal spatial distributions, then dynamically groups recurring failures into persistent defect memory without label or predefined class counts. This architecture provides a seamless, unified pipeline transitioning from real-time anomaly detection to online defect-mode discovery. Evaluated on the industry-standard WM-811K dataset, WaferHDC outperforms the strongest online baseline by 13.3% in adjusted Rand index and 10.5% in normalized mutual information. These results demonstrate the effectiveness of WaferHDC for continuous and open-world wafer defect analysis.

ABSTRACT. Neural volume rendering (NVR) has emerged as an important paradigm for photorealistic novel-view synthesis from implicit 3D scene representations. However, real-time NVR requires massive MLP-based neural field evaluations, with substantial computation and intermediate-data handling overhead jointly limiting rendering throughput. To address these bottlenecks, we propose Hit-SME, a high-throughput hybrid spiking neural network (SNN)-based MLP engine with a cascaded systolic pipeline architecture for NVR inference. To better exploit this pipeline, hardware-aware model refinement and quantization are applied at the algorithm level to adapt the hybrid MLP for cascaded execution and reduce hardware implementation complexity. At the hardware level, layer-specific systolic arrays and dataflow alignment units between adjacent arrays support direct cross-layer data streaming, and improve processing element (PE) utilization during multi-timestep execution. Experimental results show that Hit-SME maintains competitive rendering quality while delivering over 307$\times$ higher throughput and 11$\times$ lower power than an edge GPU. Compared with the state-of-the-art SNN-based neural rendering accelerator, Hit-SME achieves 2.8$\times$ higher throughput, demonstrating the effectiveness of the proposed cascaded systolic pipeline.

ABSTRACT. On-device Large Language Model (LLM) inference is increasingly limited by memory capacity and bandwidth, especially as model sizes and context windows grow. While high-density NAND memories can store static model weights, the dynamic Key-Value (KV) cache remains difficult to place efficiently: it grows linearly with context length, is scanned at every decode step, and is updated after each generated token. This paper proposes CCD-KV, a compute-near-memory accelerator that stores the KV cache in 3D Charge-Coupled Device (CCD) string memory and computes attention products next to the CCD banks. CCD provides high density and low access energy, but exposes a strict FIFO-like sequential access pattern. CCD-KV addresses this constraint through a GQA-aware bank organization, a CCD-compatible KV mapping, and a tiled output-stationary dataflow. Using a cross-stack evaluation from SPICE analog simulations and RTL synthesis to LLM system simulation, we show that CCD-KV achieves up to 4.2x decode attention speedup at 128K sequence length over an LPDDR5x mobile baseline for Qwen3-32B and 3.4x for Llama3-8B, while reducing KV-memory area by 79.8% and energy per bit by 71.5%.

ABSTRACT. Deploying large language models (LLMs) imposes stringent demands on today’s memory systems in both capacity and memory bandwidth. High-Bandwidth Memory (HBM) remains constrained by its fundamental architectural limitations due to die stacking. Recent advances in Monolithic 3D-Stackable DRAM (M3D DRAM) offer a promising alternative to HBM with better memory density, energy efficiency, and internal bandwidth compared to HBM. Yet, its monolithic 3D structure presents a unique challenge: data access latency is non-uniform across the vertical layers. This requires careful system-architecture co-optimization to take full advantage of M3D DRAM. In this work, we propose KV3D, a KV cache-centric processing near memory (PNM) accelerator that effectively utilizes the heterogeneous latency characteristics of M3D DRAM. We evaluate our proposed architecture and system under production LLM serving scenarios. Our evaluation shows that KV3D achieves up to 9.7× better time per output token (TPOT) and 18.6× better energy efficiency compared to state-of-the-art GPU-based systems while preserving model accuracy.

ABSTRACT. Long-context LLMs enable retrieval, reasoning, and agent workloads, but autoregressive decoding repeatedly reads a KV cache that grows with context length. Quantization cuts this storage and HBM-PIM provides internal bandwidth, yet existing PIM attention either reconstructs 2-bit codes into FP16 or supports only coarse scale layouts. Efficient KIVI-compatible execution faces three challenges: token-group value scales cannot move behind the PV sum; off-bank softmax creates context-length traffic; and reconstruction restores a wide datapath. To tackle these coupled constraints, DeferKV folds key scales into the broadcast query and token-group value scales into bank-local softmax weights, reducing $O(nd)$ wide scale multiplies to $O(nd/G)$ scalar folds. Second, blocked online softmax emits one group-exponent-aware state per bank and removes context-length cross-bank traffic. Finally, an integer/fixed-point PCU and hierarchical reducer preserve the low-bit path. Against iso-quantized Fused-DQ, DeferKV improves attention latency by $1.5\times$ and modeled dynamic energy by $1.06$--$1.19\times$. A routed PCU achieves $1.28\times$ throughput per area; a routed three-lane macro delivers $1.77\times$ aggregate throughput in $0.8\times$ the area of two-lane FP16. Relative to FP16-PIM, the combined quantization-and-dataflow design uses $4.9\times$ less modeled dynamic energy under the stated reducer model. It tracks KIVI-int-$z$ within $0.02$ PPL and meets a predeclared $\pm5$-F1 equivalence margin on five of six LongBench tasks.

ABSTRACT. Paged sparse attention reduces KV reads during long-context LLM decode, making it attractive for DRAM-PIM. Paged serving recycles physical frames, so token order no longer determines placement, creating three challenges. 1) Coarse placement concentrates sparse runs in a few banks, yielding a 4.23 busiest-to-mean load ratio. 2) General-purpose allocators scatter bank-balanced frames across DRAM rows. 3) Stored vector addresses add per-frame metadata and recycle updates. We propose CRISP, a placement and address-generation substrate for paged sparse attention. 1) Whole-vector cyclic interleaving balances bank work without splitting vectors. 2) Sequence-scoped row-band allocation places related frames while ownership and order remain visible. 3) Frame-derived generation computes bank, row, and column from frame and vector indices, eliminating fine-grained address maps. Across 19,200 trace-replay records, CRISP reaches a 1.00 normalized bank-load ratio and reduces mean per-bank row bands by 1.90× over buddy. With row-grouped open-row scheduling, its DDR4 PIM model improves bank-parallel K/V read and MAC latency by 1.15×/1.27× and modeled dynamic energy by 1.21×/1.22× over buddy/Native; closed-row and naive schedules show no modeled benefit. Allocator state uses 0.27 to 0.32 bytes per frame plus 2 bytes per live sequence. CRISP passes 355 lifecycle cases and bit-exact decode, and its mixed-level sky130 reference area is about 4,500 µm².

ABSTRACT. LLM inference applications, especially those that leverage test-time scaling, increasingly see poor compute utilization due to their low arithmetic intensity. We propose a waferscale memory architecture for such applications. The architecture consists of a compute die, or a set of dies, placed in the middle of a large waferscale memory pool consisting of hundreds of high-bandwidth memory devices. The proposed architecture suffers from low shoreline bandwidth and high overhead from memory controllers and the crossbar between the compute die and the memory devices. We present techniques to enable a feasible 258-HBM implementation: a distributed ASIC architecture to address shoreline bandwidth constraints, retimer-based waferscale interconnects to address reach constraints, and ultra-wide channels implemented using a multicast retimer design to address memory-controller and memory-crossbar overheads. The implementation improves cost efficiency by up to 3.8× and energy efficiency by up to 5.33× over a GPU cluster.

ABSTRACT. Large language model (LLM) inference on edge devices is fundamentally memory-bound, making processing-near-memory (PNM) a compelling paradigm that alleviates the data-movement bottleneck. To further reduce memory footprint and bandwidth pressure, weight and key-value (KV) cache quantization is widely adopted. Nevertheless, quantization introduces mixed-precision floating-point–integer (FP–INT) computation, incurring costly dequantization overhead. Lookup tables (LUTs) can eliminate this overhead by directly retrieving precomputed FP–INT products. However, the large number of LUT entries inflates lookup latency and energy and demands substantial on-chip storage, thereby hindering its integration with PNM architecture. In this paper, we present LUMEN, a compressed-LUT-based PNM architecture for efficient LLM inference at the edge. LUMEN exploits the structural regularity of FP–INT multiplication to compress the table and employs a two-level LUT hierarchy to reduce lookup overhead. To further increase system hardware utility, LUMEN introduces a hardware-friendly quantization method and a workload-balancing mapping scheme. System-level evaluation demonstrates that LUMEN achieves 53.5×, 37.2×, and 3.3× higher energy efficiency while improving throughput by 31.7×, 4.7×, and 2.4× over Jetson Thor, RTX 5090, and H2LLM, respectively.

ABSTRACT. Static IR-drop analysis determines whether a design satisfies sign-off constraints, but repeated exact power-grid solves are too costly for tight optimization loops. Existing machine-learning (ML) estimators reduce latency but return point estimates without per-instance guarantees, can miss sign-off hotspots without warning, and lack inference-time accuracy–cost control. We present CertIR, to our knowledge the first certified ML estimator for static IR drop. CertIR combines fixed-budget Krylov iterations with a multiplicative correction network. Under the M-matrix and exact-arithmetic conditions, a residual bound yields per-node certificates after a reusable supersolution check. On the ten ICCAD-2023 test designs, CertIR attains the lowest image MAE on every case, reduces mean image MAE by 5.4× relative to the best published baseline, and achieves the highest reported mean hotspot F1 (+15% over the best prior). Its end-to-end prediction path averages 0.18 s per design, including input parsing. Across the tested refinement budgets, the nodal screen records no benchmark-threshold misses and reaches a median safe-node false-alarm rate of 0.14%. Under the same conditions, zero-miss screening applies to any specified threshold. Adjusting the anchor budget reduces one model’s image MAE from 0.032 to 0.009 mV at nearly constant prediction runtime.

ABSTRACT. Dynamic IR drop analysis is essential for circuit performance and reliability but incurs substantial runtime overhead as design scale and PDN complexity increase. Graph-based learning methods have therefore been explored for fast dynamic IR drop prediction, with Graph Transformers offering strong capability for modeling power delivery interactions. However, existing methods mainly construct PDN graphs over coarse-grained tiles, while conventional attention mechanisms do not explicitly capture physical cell-to-cell coupling. In this work, we propose a subgraph-based Graph Transformer framework for fast and accurate cell-level dynamic IR drop pre diction. Specifically, we develop a criticality-guided subgraph con struction method for cell-centered graph learning and a PDN-aware self-attention mechanism to better represent PDN structures and capture power-delivery coupling among cells. Experiments were conducted on TSMC 12nm designs of different scales, and the pro posed method was evaluated at both cell and tile levels. Compared with the strongest reproduced cell-level baseline, our method re duced the average MAE by17.0%andincreasedtheaveragePearson correlation from 0.717 to 0.803. At the tile level, it reduced MAE by 10.6% and increased Pearson from 0.728 to 0.782 compared with PDNNet. It also achieved a 30× speedup over commercial analysis, demonstrating its prediction accuracy and computational efficiency.

ABSTRACT. In advanced packaging, multilayer redistribution-layer (RDL) power/ground (P/G) planes are synthesized from fragmented whitespace remaining after signal routing. Unlike conventional on-chip power delivery networks (PDNs), modern chiplet packages often contain many P/G domains but only a few RDL routing layers, making cross-layer overlap between same-net P/G planes critical for dense power-via insertion and low-impedance power delivery. Existing P/G-plane synthesis methods, however, optimize plane geometries largely on a per-layer basis and therefore cannot effectively maximize cross-layer overlap. This paper formulates multilayer RDL P/G-plane synthesis as a cross-layer overlap optimization problem and proposes a cross-layer aligned cell partition that enables joint optimization across routing layers. Built upon this representation, a reinforcement learning framework efficiently explores the enlarged optimization space while preserving connectivity constraints to maximize power-via opportunities. Experimental results on industrial benchmarks demonstrate 1.44$\times$ the power-via count and 2.08$\times$ the stacked power-via count of a state-of-the-art geometry-based P/G-plane synthesis method, leading to consistently improved IR-drop performance.

ABSTRACT. Backside-powered face-to-face (F2F) 3D ICs deliver current to the top die through the pitch-constrained hybrid-bonding interface used for signal routing. Power/ground (P/G) and signal hybrid-bond terminals (HBTs) therefore share the bonding-interface area, so P/G HBT placement must reserve capacity for signal HBTs. Top-die voltage drop is set by resistance from bottom-die back-side power metal to top-die cell rails, including bottom-die power via stack (BD-PVS) structures, P/G HBTs, and redistribution metals. Our flow co-optimizes redistribution stripes, legal BD-PVS locations, and legal P/G HBT locations before detailed routing. An implemented-geometry sparse modified nodal analysis (MNA) model uses the interconnect technology (ICT) file and the implemented PDN geometry to evaluate each possible resource location. The optimizer selects standard-width stripes and discrete locations for BD-PVSs and P/G HBTs under resource budgets and a pre-route routing-demand cost. The BD-PVS and P/G HBT count limits do not exceed the corresponding baseline counts. Experimental results show that our flow reduces the sign-off worst top-die voltage drop by 53--88% versus a uniform-pitch baseline under the same BD-PVS and P/G HBT count limits and at comparable PDN metal.

ABSTRACT. Backside metallization offers lower-resistivity routing and decouples power delivery from signal, yet backside power (BS-PDN), clock (BS-CDN), and signal (BSS) routing have been developed in isolation, leaving their combined PPA potential unrealized. We present \textit{Grad-BSS}, to our knowledge the first commercial-EDA-integrated flow to unify all three backside domains, anchored by the first gradient-based BSS net-assignment optimizer. Treating BS-PDN and BS-CDN as strong routing priors, Grad-BSS couples GPU-accelerated differentiable timing, layer-aware routing surrogates, and a learned congestion model, with black-box perturbation gradients bridging the discrete commercial router. The resulting differentiable optimization moves thousands of nets simultaneously per iteration---beyond the reach of CPU-bound flows and 2D wirelength proxies. Across four benchmarks spanning 90K--3.7M cells, Grad-BSS improves WNS 17--32\% and TNS 16--34\% and cuts routing overflow 25--38\% over no-backside-signal baselines while confining backside signals to at most 1{,}024 nets per design under an explicit signal-TSV budget.

ABSTRACT. We propose a clock distribution network (CDN) where the clock mesh is on backside metal (BM) layers while the rest of the CDN stays on the frontside. Since power distribution network is also on the backside (BSPDN), BM layers are shared between mesh and PDN. We identify an important problem of placing mesh receivers while the keep-out zones (KOZ) between clock- and power-nTSVs are taken into account. We show that the problem can be addressed through a potential-field method (PFM).

ML models are developed for placement of mesh receivers: a U-Net predicts initial positions, and an MLP predicts force weights for PFM-guided position refinement. Both models are trained through self-supervised learning by optimizing a differentiable objective over clock latency, IR-drop, and KOZ violations. Experimental results show that the proposed CDN reduces max local clock latency by 26%, global clock skew by 40%, and mesh switching power by 29% on average over a frontside CDN [1]. On the same backside CDN, ML-guided PFM satisfies KOZ while lowering IR-drop by 33% and requiring 85% fewer iterations than standard PFM.

ABSTRACT. Formal Verification of large industrial hardware designs remains challenging, as state-space explosion often prevents existing verification engines from proving or refuting safety properties within practical resource budgets. We observe that many difficult verification instances contain structurally decomposable sub-problems that remain unexploited in conventional monolithic verification flows. This work present Decompose-Transform-Refine-Verify (DTRV), a new decomposition-guided methodology that augments portfolio-based verification through disjunctive decomposition, functionality-preserving transformations and incremental constraint refinement. DTRV exposes simpler verification tasks and progressively reduces the reachable search space while preserving verification correctness. We formally prove the correctness of the decomposition strategy and soundness of the constraint refinement process. Experimental evaluation on a diverse set of representative Hardware Model Checking Competition (HWMCC) benchmarks demonstrates its scalability on industrial designs exceeding 1.5 million elements. Notably, on this 1.5 million elements instance, DTRV achieves a peak verification runtime speedup of 5.5× over the state-of-the-art verification approaches, demonstrating that it serves as a valuable addition to strengthen existing portfolio-based verification flows.

ABSTRACT. Subcircuit matching is important for circuit analysis, verification, and pattern recognition, but general subgraph matching methods are often inefficient on large-scale circuit netlists. This paper presents a schema-aware heterogeneous GPU framework for subcircuit matching. The method represents circuits as typed, port-labeled bipartite graphs, preserving component types, nets, and port semantics. It uses circuit-aware candidate pruning, relation construction, and prefix-based task decomposition to reduce the search space and expose parallelism for GPU execution. The framework combines CPU-side query planning with GPU-accelerated filtering and matching, and further exploits circuit features such as high-degree nets, repeated motifs, and structural symmetry. Preliminary experiments show that the proposed approach achieves substantial efficiency improvement on large-scale circuit graphs.

ABSTRACT. JEDEC specifies DRAM protocol behavior through simplified stat machines, timing tables, and prose, and each generation moves more of a command’s legality into command history and state shared across Banks—evidence that a table of pairwise timing constraints, which records each legality boundary but not the state enforcing it, cannot restore. In this paper, we propose a Resource-Grounded Executable Semantics (RGES) that keeps this state with its architectural owner. RGES factors the device snapshot into resource Domains, each separating discrete modes from the active processes created by earlier commands; commands and elapsing time evolve the snapshot under declared visibility, scoped updates, and a frame condition; and a single execution derives the legality verdict, the pairwise timing boundary, and the complete set of rejection causes. We realize RGES for LPDDR5, whose two-step activation, Bank Groups, rolling activation limits, and on-demand WCK synchronization lifecycle make the reassembly burden most acute, and the model reproduces all 17/17 independently derived JEDEC timing records exactly. Bounded exhaustive exploration further shows that the simplified-state-machine view leaves 67.71% of the explored command judgments verdict-ambiguous, that every reduced view leaves rejection causes ambiguous, and that both resolve only under full declared visibility.

ABSTRACT. Formal hardware information-flow verification (IFV) provides strong guarantees against secret-dependent timing and control behavior, but often scales poorly on realistic RTL. We identify two recurring proof barriers in self-composed IFV: implementation complexity, where proof-hard datapath logic dominates even though the property needs only a compact boundary relation, and relational inductive complexity, where the proof depends on cross-copy public-control facts that the backend prover does not infer efficiently. To address them, we introduce two semantic proof decomposition forms: functional simplification, which replaces a proof-hard RTL region with a validated over-approximate summary, and relational strengthening, which exposes and proves the cross-copy relations needed for induction. We further present SLED-IFV, a solver-validated LLM-guided flow that automates the selection of these forms and their concrete targets. Given a self-composed miter and an oracle-free decision sheet, the LLM proposes a decomposition, then materializes it into proof artifacts under controller checks. The controller compiles the checked artifacts into proof obligations, and the formal verification backend remains the sole authority for acceptance. Across nine nontrivial benchmarks constructed from real RTL, SLED-IFV achieves up to 603x solver-only speedup and converts two 12-hour timeouts into completed proofs. The closed-loop flow produces verifier-accepted decompositions for all cases.

ABSTRACT. The scalability of word-level hardware model checking is highly sensitive to the syntactic structure of BTOR2 models; semantically equivalent representations often yield vastly different performance from backend SAT/SMT solvers. Existing rewriting techniques are typically local and syntactic, failing to explore the broader space of equivalences that impact solver behavior. We introduce a novel framework based on equality saturation to systematically explore this space. Our approach utilizes a solver-aware cost model integrating metrics such as dependency depth, operator characteristics, and a CNF complexity proxy to extract the representation predicted to minimize downstream solving effort. Critically, to adapt to the diversity of hardware designs, we employ a learning-based strategy selector trained via knowledge distillation. This selector adaptively chooses the optimal cost model configuration using only static features, effectively transferring insights from expensive dynamic feedback into a fast, deployable policy. Experiments on HWMCC benchmarks demonstrate substantial improvements across multiple IC3 and BMC engines. Across the four IC3 engines, our approach yields an increase from 582 to 693 (+19.07%), while the mean PAR-2 across engines decreases from 4139.33 to 3516.62 (-15.04%). This work establishes adaptive, solver-aware equality saturation as an effective preprocessing layer for hardware verification.

ABSTRACT. Parameterized cells (PCells) generate layout geometries from user-specified parameters, and undetected DRC violations in PCells propagate to all downstream instantiations, causing costly late-stage rework. Traditional DRC tools operate on concrete layouts, requiring PCells to be instantiated at specific parameter values before checking; this approach cannot cover the full parameter space and may miss violations that only manifest at certain parameter combinations. We present FormalPCell, a formal DRC verification framework for PCells that guarantees correctness across the entire parameter space in a single pass. We design a layout primitive IR with symbolic interpretation to extract symbolic geometric primitives from complex PCell code, and apply DRC property generation with two-level spatial dominance pruning to map DRC rules onto the IR effectively, reducing naive O(n2) nonlinear formulas to O(n) linear properties for SMT verification. On a benchmark of 374 LLM-generated buggy PCells across four Sky130 devices, FormalPCell achieves 100% DRC violation coverage within seconds, while sampling-based baselines cannot cover all violations.

ABSTRACT. LLM-based applications are rapidly shifting from single-turn inference to multi-turn dialogues, such as chatbots, virtual-agent services, where the requests repeatedly interact with long histories represented as prefix cache contexts. Prior hardware architectures tailored for single-turn inference are insufficient as simple request binding and migration strategies would incur substantial KV-cache transfer overhead for long-context multi-turn dialogue serving. In this work, we present ATLAS, a heterogeneous processing-near-memory (PNM) based architecture utilizing a request offloading scheme based on prefix-based radix tree reordering. We further mitigate the inherent thermal challenges of 3D-stacked architectures via optimized compute-buffer co-placement and cache-aware dataflow mapping. Experimental results demonstrate that ATLAS achieves a 1.55$\times$ speedup in TTFT-P99 and a 44\% lower energy consumption compared to the NVIDIA H100 GPU baseline across synthesized workloads. Furthermore, it effectively alleviates thermal pressure by reducing the peak steady-state temperatures of both the DRAM and logic dies, alleviating the bandwidth loss in 3D DRAM caused by thermal-induced refresh overheads with up to a ~1.08$\times$ throughput improvement.

ABSTRACT. Hybrid Bonding (HB) DRAM vertically integrates a DRAM die with a logic die through dense Cu-Cu interconnects, providing high bank-level bandwidth for Large Language Model (LLM) inference. However, its bank-local organization complicates system-level error correction. Although banks share command and address interfaces, they lack a high-bandwidth lateral data path for cross-bank aggregation. Redundancy collection and failure recovery must therefore traverse the network-on-chip (NoC) on the logic die, where ECC traffic competes with LLM inference traffic. Our analysis shows that data gathering accounts for up to 80.1% of naive cross-bank ECC latency, while single-bank failure recovery incurs up to 17 times the baseline access latency. We propose TCE, a two-level grouped cross-bank ECC architecture for HB DRAM. TCE preserves bank-local on-die ECC for fine-grained errors and organizes banks into small topology-aware protection groups for larger failure domains. Within each group, XOR parity is distributed across all participating banks, eliminating a dedicated parity bank and localizing redundancy traffic. We further formulate bank grouping as a multi-objective optimization problem that jointly considers storage overhead, communication cost, and uncorrectable-failure probability. The analysis identifies group sizes of four and eight banks as effective configurations. Evaluations across representative LLM workloads show that TCE limits ECC-induced inference latency overhead to at most 30.3% and reduces the latency penalty by 36% to 62% over non-pipelined gather-based baselines. The distributed XOR engine incurs only 612 µm^2 of area and 6.7 mW of dynamic power per bank. Mission-time fault simulations further show that TCE substantially reduces uncorrectable failures without silent data corruption in the evaluated configurations. TCE therefore provides efficient cross-bank protection for HB DRAM without modifying the internal DRAM die.

ABSTRACT. Embodied AI and AR/VR devices increasingly require low-latency, low-power, and privacy-preserving access to local knowledge, making edge-local retrieval-augmented generation (Local RAG) increasingly important.Computing-in-memory (CiM) executes computation within memory arrays to reduce data movement, offering a promising approach to efficient edge retrieval. However, limited array capacity and numerical precision require high-dimensional embeddings to be compressed into low-dimensional, low-bit representations. Dimensionality reduction, quantization, and hardware noise can perturb candidate similarities and disrupt the local-neighborhood topology critical to top-k retrieval. Meanwhile, blockwise mapping and large-scale top-k ranking in conventional CiM deployments incur substantial peripheral-processing and data-movement overhead. We propose TACO (Topology-Aware COmpression), a hardware-software co-designed framework for robust and efficient CiM retrieval. On the software side, TACO combines Proximal Relation Distillation, two-stage feature alignment, and noise-aware fine-tuning to preserve retrieval-critical local topology and improve robustness to quantization and hardware noise. On the hardware side, it employs calibration-guided pre-ADC input-block fusion, exact MSB-first radix top-k ranking, and dataflow optimization to reduce peripheral and data-movement overhead. Across five KILT tasks and four device settings, TACO improves Average Recall@5 by 2.7%–5.2% over the strongest software baselines. Compared with a conventional blockwise-conversion CiM baseline, it reduces modeled core area, query latency, and dynamic energy by 12.39%, 29.25%, and 12.59%, respectively.

ABSTRACT. Large language model serving offloads idle key-value (KV) caches to SSDs to relieve memory pressure, but under agentic coding traffic, this can result in a huge amount of write amplification. We show that most of these writes eventually become unneeded: offloaded chunks are orphaned by context compaction, re-hashed under a new key on the next append, or left behind by a finished session. The serving system already knows these conditions with certainty, so they require no prediction. We use them to build a lossless KV- cache offloading mechanism that suppresses provably dead writes at their source, groups the surviving chunks by session onto Zoned Namespace (ZNS) zones so that data with correlated lifetimes shares a zone, and evicts the longest-idle session under capacity pressure. We implement the design in LMCache and evaluate it on one month of production Claude Code and Codex traffic, using a simulator validated against FEMU and a real vLLM and LMCache deployment. The design reduces system-level write amplification by up to 29% with no loss of read service, extends projected SSD lifetime by 1.3 to 1.4 times, and serves the same workload on half the SSD capacity that unmodified LMCache requires.

ABSTRACT. Speculative decoding (SD) is a draft-then-verify technique for large language model (LLM) inference that improves generation efficiency at low batch sizes. To overcome the memory wall inherent in the sequential drafting phase, processing-in-memory (PIM) is attractive because of its immense near-data bandwidth. However, accelerating dynamic SD trees on PIM is severely bottlenecked by pipeline load imbalances and heavy cross-bank key-value (KV) cache relocations for accepted tokens. This work proposes TreePIM, a tree-aware heterogeneous architecture leveraging 3D hybrid bonding (HB) to accelerate SD. At the hardware level, TreePIM proposes a topology-aware KV cache mapping strategy that maps tree depth to specific bank groups, thereby eliminating migration overheads. At the software level, a hardware-aware, scalable tree-construction algorithm dynamically adjusts the topology to balance arithmetic intensity and mask pipeline bubbles. Compared with SD on an existing PIM-enabled heterogeneous architecture, TreePIM boosts throughput by 4.6$\times$ and energy efficiency by 10.1$\times$.

ABSTRACT. Transformer models are widely used in large-scale vision and language applications. The cost of self-attention grows with the square of sequence length, increasing inference latency and energy consumption. Hybrid ReRAM-SRAM computing-in-memory (CIM) architectures offer an efficient solution for Transformer acceleration. However, sparse-attention CIM designs rely on auxiliary predictors whose sparsity-search and data-management overhead can reduce the benefits of sparse execution. Removing this path requires efficient sparsity generation within the main data path, while ReRAM nonidealities distort binary Q/K projections and sparse-selection boundaries. In this work, we propose PSD-CIM, a predictor-free sparse binary attention CIM accelerator. PSD-CIM integrates binary Q/K-based sparse selection into attention computation, eliminating a standalone predictor.EMEP extracts binary codes and mean factors from ReRAM currents, while the SRAM-CAM Match Count unit selects important Q-K pairs. Hardware-aware distribution shaping reduces projection errors and recovers accuracy lost to nonidealities and sparsification. Experiments on multiple models and datasets show that PSD-CIM maintains task accuracy comparable to the baseline while improving energy efficiency by 1.52x--34.19x over state-of-the-art CIM Transformer accelerators.

ABSTRACT. This paper presents CalNet, an ADC calibration framework that learns bandgap-reference (BGR) behavior and digitally corrects ADC output errors over temperature using LUT-based coefficients. Temperature-induced BGR drift shifts ADC reference levels and causes output-code errors in precision mixed-signal systems. Using three BGR node voltages at 25 ◦C and a given trimming code, CalNet predicts chip-specific BGR output at five temperature points, derives temperature-dependent ADC correction factors and suggests a per- chip best trimming code. The model is pre-trained on Monte Carlo data and fine-tuned with chip measurements to reduce simulation- to-silicon mismatch. A selective stage further limits overcorrection when the predicted BGR temperature behavior is unreliable. A prototype chip including BGR, ADC, and digital block is fabricated in a 130 nm process to validate CalNet. The proposed calibration reduces the total ADC measurement error to ±0.033mV over −15 to 80◦C, which is equivalent to a 76.2% reduction in BGR temperature coefficient.

ABSTRACT. Analog circuit design automation using reinforcement learning (RL) has emerged as a promising approach for reducing manual effort. However, many existing RL-based methods focus on single-objective optimization. Even methods designed for multi-objective (MO) problems often reduce multiple design specifications to a single scalar reward. This simplification limits the ability to capture the true Pareto trade-off among competing objectives and often leads to suboptimal designs. Moreover, requiring the model to be retrained from scratch whenever the desired MO specifications change remains a key limitation. To address these challenges, we present ORACLE, an open-source RL-based framework for MO analog circuit design optimization that replaces scalar reward optimization with vector-valued learning and preference-aware conditioning. ORACLE represents a true MO analog circuit design optimizer that uses a preference vector to specify the relative weights of multiple objectives, enabling a single trained model to generate designs across diverse trade-off settings without retraining. We further propose two preference-guidance strategies, namely normalized-weight guidance and cosine-aligned guidance, to improve convergence. In addition, we incorporate a large language model (LLM)-guided action selection mechanism to filter actions that are likely to lead to suboptimal designs or increased runtime. Our results show that, on multiple circuit topologies with 2,000 test cases, ORACLE reduces runtime by 35.4x - 104.4x compared to state-of-the-art approaches. It also meets 99.9% of the 2,000 target specifications, and achieves 4.3x - 318.6x better figure of merit in the resulting output specs.

ABSTRACT. Analog layout automation remains challenging in Analog/Mixed-Signal circuit design, because parasitics and mismatches introduced during layout strongly affect circuit performance. Placement is especially critical among the layout stages, as it constrains the routing solution space and the achievable post-layout performance. Existing analytical placement methods optimize device coordinates under center-based wirelength proxies and leave access point (AP) selection to routing. In analog circuits, however, a routing pin is an extended piece of terminal metal rather than a fixed point, and the best AP on it depends on where the other connected devices are placed, so a coordinate-only placement optimizes for connection points that the router will not use. We present APPlace, a routing-aware analog placement framework that co-optimizes device locations and AP selections during global placement, followed by a legalization stage that preserves the structure established by global placement. Experimental results on four real-world analog benchmarks show that APPlace achieves better overall post-layout performance than representative baselines at comparable layout area. Ablation studies further show that removing AP co-optimization causes up to a 13dB CMRR loss among the OTA benchmarks and a 23% increase in comparator delay.

ABSTRACT. We present an explainable routing agent for analog and mixed-signal (AMS) layouts that provides deterministic constraint-conflict diagnosis through an LLM-aware backend design. The agent translates natural-language requests into abstract API calls for an SMT/ILP-based track-assignment backend supporting advanced BEOL design rules, symmetry, and EM/IR constraints. When constraints conflict, a priority-staged relaxation loop extracts minimal UNSAT cores and produces a deterministic diagnosis report, preventing formulation-level hallucination by construction without fine-tuning or retrieval-augmented generation. Evaluated on seven AMS circuits (16--3205 transistors) in ASAP7 7nm FinFET, five zero-shot LLMs achieve over 94% interaction accuracy, with interactive-speed backend latency and routing quality matching expert manual layouts in wirelength, via count, and symmetry.

ABSTRACT. Circuit image-to-netlist extraction is widely adopted to generate high-quality datasets for analog circuit design automation. However, the application is bottlenecked by topological inaccuracies, especially for complex circuits. To address this, a promising method is to integrate an autoregressive rectification flow, which presents three inherent challenges: 1) general Vision Language Models (VLMs) suffer from a severe visual-topological semantic gap, lacking the domain expertise to reason about circuit connectivity from schematic images; 2) task-specific rectification models are hindered by extreme class imbalance, where abundant correct edges dominate training and suppress the detection of rare topology errors; 3) iterative rectification frameworks lack principled halting criteria, making it difficult to balance correction accuracy with computational efficiency. In this paper, we propose CktHVR, a convergence-aware Hypothesize-Verify-Refine framework that integrates Graph Neural Networks (GNNs) with VLM-based visual verification for analog circuit topology rectification, featuring three key contributions: 1) a heterogeneous GNN with a dual-channel message passing encoder, generating topology error hypotheses; 2) a two-stage confidence annealing strategy with a linearly decaying bias schedule, resolving the cold-start problem caused by extreme class imbalance; 3) a convergence-aware dynamic halting mechanism based on the topological consistency score, enabling bounded and interpretable termination. Experimental results on the constructed TR-100 benchmark demonstrate that CktHVR outperforms the best general VLM baseline by 2.4× on simple circuits and 6.0× on medium circuits. On large complex circuits, while general VLMs achieve near-zero rectification rates (<5%), CktHVR maintains effective rectification capability with a perfect rectification rate of 60%.

ABSTRACT. Analog integrated circuit sizing is a core task in analog design automation, requiring the simultaneous optimization of conflicting performance objectives under stringent specifications. Existing methods still struggle to balance feasibility discovery and performance improvement under limited simulation budgets. We therefore propose LMSACO, an LLM-guided multi-objective state-adaptive framework. LMSACO introduces Annealed Dynamic Feasibility Utility Mapping, which reformulates each raw performance metric into a feasibility-aware utility and applies iteration-dependent annealing to produce dynamically calibrated constraint-aware signals. It further develops an LLM-guided strategy-adaptive qParEGO acquisition mechanism that adjusts the scalarization function and weight-generation strategy according to the optimization state, enabling adaptive exploration–exploitation balancing. Experiments on 10 circuits from six categories show that, under identical simulation budgets, LMSACO achieves the highest final HV on all benchmarks and improves the average HV by 30.8%-191.5% over competing baselines.

ABSTRACT. Vision-language-action (VLA) models have been widely used in various robotic applications, yet the substantial computation and memory-bandwidth demands of these models make it difficult to meet the real-time requirements of edge deployment. Quantization can reduce both computation and data movement, but existing methods typically adopt static weight precision allocation schemes. In this work, we systematically analyze the temporal characteristics of VLA models and find that: 1) the language model’s requirement of weight precision varies across different action chunks, and 2) the action expert’s precision sensitivity varies across diffusion denoising steps. Motivated by these findings, we propose ACED, an algorithm–hardware co-designed VLA accelerator exploiting dynamic weight precision switching. At the algorithm level, ACED applies an actionsensitivity-aware strategy for the language model and a denoisingstep-aware strategy for the action expert, both realized through a 2-bit-weight-with-2-bit-residual (W2R2) quantization, enabling efficient switching between W2R2 and W2 execution. At the hardware level, ACED implements a dual-mode multiplier-free compute core with a lightweight precision switching component to efficiently support these runtime precision transitions. Experiments on 𝜋0.5 and GR00T N1.5 demonstrate that ACED preserves task success rate while achieving 5.86× and 3.44× end-to-end speedup, as well as 3.55× and 4.88× higher energy efficiency, compared with NVIDIA Jetson Thor, respectively. Moreover, compared with the state-of-theart accelerator DiTPA, ACED improves action chunk generation frequency by 1.28× on average.

ABSTRACT. Vision-Language-Action (VLA) models are emerging as a unified paradigm for embodied applications. Their diffusion-transformer-based action experts must run at the edge to meet low-latency control requirements. However, these experts comprise operators of low operational intensity, making inference dominated by weight movement. Analog compute-in-memory (ACIM) alleviates this bottleneck by keeping weights stationary, but its computation noise severely degrades the task success rate. Executing the few large-magnitude (salient) channels on a digital NPU is the mainstream remedy, yet it faces two challenges. First, digital execution restores accuracy at the cost of ACIM's efficiency. Since the salient set varies across diffusion steps, a static analog/digital partition incurs excessive digital execution. Second, dynamically adapting the partition shifts the distribution of the remaining analog workload, deviating from the statically calibrated quantization scales and ADC ranges and reducing the effective resolution. We present ActRAM, a hybrid analog/digital action-expert accelerator architecture for efficient VLA inference. ActRAM employs a three-stage, diffusion-step-aware mapping search to minimize digital execution. To alleviate the weight-loading overhead of the remaining digital channels, ActRAM caches their frequently reused weights in on-chip SRAM, reducing off-chip memory accesses by 54.2%-62.6%. ActRAM further integrates a rescale unit that adapts activation quantization parameters and ADC ranges for the dynamically mapped ACIM workload. Experiments on pi0.5 show that ActRAM achieves 3.9×/5.3× speedups and 8.3×/20.0× energy-efficiency improvements over NVIDIA Jetson Thor and Jetson Orin, respectively, and a 2.0× speedup over the state-of-the-art DiT accelerator DiTPA, with less than 1% task-success-rate degradation.

ABSTRACT. Efficient deployment of feed-forward 3D reconstruction models is becoming increasingly important for emerging applications, which require both real-time response and high energy efficiency. Among recent approaches, the Visual Geometry Grounding Transformer (VGGT) delivers high-quality multi-view 3D reconstruction, but its global attention scales quadratically with the number of input frames, making efficient long-sequence inference challenging. We observe that VGGT attention heads expose two stable but complementary forms of redundancy: sparsity and row-wise similarity. Exploiting both forms substantially reduces computation, but leaves a highly irregular workload that maps poorly to GPUs and uniformly partitioned near-memory systems. This work proposes HB-VGGT, a hybrid-bonded near-memory accelerator for efficient VGGT inference through algorithm-hardware codesign. At the algorithm level, the HB-VGGT introduces a head-wise complementary attention optimization that jointly exploits two forms of redundancy in VGGT global attention by anchor-based merging and dynamic block-sparse attention. At the architecture level, we design an HB-based near-memory accelerator tailored to this optimized attention with hybrid parallel execution, HB-aware ring-attention mapping, and complementarity-aware head scheduling. The experimental results show that compared with an RTX 6000 Ada GPU, HB-VGGT achieves up to 4.1× speedup and 20.73× higher energy efficiency while occupying only 57.6% of the area.

ABSTRACT. The increasing size and complexity of neural networks have motivated research into effective compression techniques that preserve model accuracy. Sparsity and weight clustering are well-established methods for reducing neural network size, demonstrating proven success in maintaining accuracy while improving computational efficiency. Recent advancements have expanded the application of these techniques beyond mere compression, leveraging them for inference acceleration as well. However, there is a notable lack of exploration into the combined application of these two methods to fully realize their potential benefits. To address this challenge, this paper presents a comprehensive co-design space exploration framework and methodology that investigates the application of sparsity and weight clustering techniques across the layers of a neural network to minimize the hardware cost requirements of hardware accelerators and the network inference latency while maximizing network accuracy. As target architectures, our co-design framework considers RISC-V-based SoC designs including hardware accelerators realized by instruction set extensions to best support the above sparsity and weight clustering techniques. To accelerate the exploration, analytical models (proxies) for the estimation of performance and cost of accelerator settings are defined and used. In our evaluations, we compare the exploration progress of when using proxy-based evaluations with a measurement-based approach in which each design point is evaluated on an FPGA board which takes 2 orders of magnitude more time per design point. As for the quality of the DSE results, we show being able to find solutions with inference speedups of up to 4.3× over a CPU-only RISC-V baseline, within a given optimization time budget of 4 hours.

ABSTRACT. Tiny machine learning (TinyML) targets neural network inference on highly resource-constrained devices, where conventional design choices effective for edge AI often become suboptimal when scaled down to TinyML workloads. Under such constraints, post-processing operations are no longer negligible and can account for a substantial fraction of execution. However, existing accelerator designs provide limited support for efficient post-processing under these conditions. In this work, we present a TinyML-oriented accelerator design derived from the Versatile Tensor Accelerator (VTA). The design introduces a fused arithmetic logic unit (ALU) micro-operations (μops) execution pattern that improves data reuse without sacrificing flexibility for diverse post-processing sequences. It also tightly couples the general matrix multiplication (GEMM) unit and the ALU via a register-based interface to enable execution overlap and reduce buffer overhead. Implemented in UMC 28nm technology, the proposed design achieves 3.56 TOPS/W (INT8) at 250 MHz, corresponding to a 2.83× improvement in energy efficiency over VTA.

ABSTRACT. Sparse training is an effective approach to mitigating the prohibitive computational cost of deep neural network training. Existing accelerators, however, face two fundamental challenges. First, the irregular distribution of nonzero operands does not fit naturally into regular architectures such as systolic arrays, necessitating sophisticated processing elements and complex zero skipping logic. Second, prior works that support sparsity across forward propagation (FP), backpropagation (BP), and weight update (WU) typically rely on heterogeneous sparsity sources (weights, activations, and gradients), whose sparsity patterns are distinct and phase-dependent. Managing such heterogeneity complicates dataflow scheduling and may inflate hardware cost. In this work, we propose a hardware-software codesign that enables efficient irregular-sparsity exploitation across FP, BP, and WU on a single systolic array. Specifically, we exploit only weight sparsity to reduce computation, which reliably achieves ultra-high ratios (>75%) across all three phases. We also introduce a fast compression method that transforms the irregular layout of the sparse weight matrix (or its transpose) into compact, structurally regular blocks, enabling efficient processing on the array. By reconfiguring the systolic array between weight-stationary (FP/BP) and output-stationary (WU) dataflows, we maximize hardware utilization without modifying the underlying PE microarchitecture. Experiments show up to 5.21x and 3.73x improvements in training throughput and energy efficiency, respectively.

ABSTRACT. Face-to-face 3D IC floorplanning jointly optimizes block layer assignments and planar positions while modeling cross-layer connections through hybrid bonding terminals (HBTs). Pseudo-3D methods pre-partition blocks and restrict vertical mobility. Existing native 3D methods either constrain the search through heuristic representations or require legalization after analytical optimization. NaCo3D instead uses grid-based reinforcement learning to search the joint layer-position space without predefined partitioning or a heuristic representation. Its hybrid action learns layer and position jointly while determining orientation from geometric feasibility. Because HBT positions remain unknown during sequential floorplanning, an HBT-aware wire mask estimates cross-layer HPWL from layer-wise bounding boxes before congestion-aware HBT legalization. Orientation-specific masks and local spatial features promote compact layouts. On GSRC, NaCo3D reduces average HPWL by 9.8% and improves area utilization by 3.2% over the strongest baselines. Experiments with up to 911 blocks and zero-shot transfer assess scalability and transferability.

ABSTRACT. Vertical stacking in 3D ICs increases power density and complicates heat dissipation, making thermal management a major challenge in early physical design. In 3D fixed-outline soft-module floorplanning, the high cost of accurate thermal feedback and the vast design space make it particularly challenging to jointly optimize die assignment, module positions, and shapes while accounting for thermal effects. To address these issues, we propose a two-stage thermal-aware optimization framework. In the first stage, a thermal-aware discrete structural search is performed to determine a favorable die assignment and initial floorplan. In the second stage, a thermal-guided continuous optimization determines module positions and shapes under the fixed die assignment. To provide efficient thermal feedback during optimization, we develop a CNN-based thermal model with explicit physical scale conditioning to generalize across different chip sizes. Compared with the prior method, our framework reduces peak temperature by \(9.68~\mathrm{K}\) on average and by up to \(18.9~\mathrm{K}\) on the GSRC benchmarks, while maintaining favorable wirelength and competitive cross-die interconnect overhead. Moreover, the proposed thermal model achieves about 5,200$\times$ speedup over HotSpot with high prediction accuracy.

ABSTRACT. In face-to-face (F2F) memory-on-logic 3D ICs, rising power density makes static IR-drop a first-order design constraint. However, P/G TSV planning and macro placement compete for shared bottom-die whitespace, making their joint optimization challenging. We propose MoL-PAM, a Benders-type decomposition heuristic that separates the joint problem into a master problem for region-level whitespace reservation and a subproblem for reservation-aware macro repartitioning, placement refinement, and optimistic IR-drop evaluation through full P/G TSV insertion. Instead of exact Benders cuts, the two levels communicate through structured feedback consisting of displacement-based wirelength cost estimates and adjoint-sensitivity-based IR-benefit estimates. This feedback enables the master to efficiently evaluate and refine candidate reservations without rerunning the complete placement-and-IR flow for every candidate. After the iterative coordination converges, detailed P/G TSV planning determines the final TSV plan. Experiments on four benchmarks under a 120 mV static IR-drop target, corresponding to 12% of VDD, show that MoL-PAM reduces worst-case static IR-drop by 18.3%–31.5% compared with the best baseline while maintaining placement quality comparable to the original unconstrained placement flow.

ABSTRACT. Face-to-face bonding enables clock signals to be distributed across tiers in 3D integrated circuits, creating new opportunities for clock tree synthesis (CTS). However, cross-tier CTS must coordinate clock-tree construction with the tier assignment and sizing of clock buffers. Existing 3D CTS flows typically fix topology or tier decisions early, limiting exploration of the cross-tier design space. To solve this, we propose XCTS, a cross-tier-aware differentiable CTS framework that represents parent connectivity, buffer tier, and buffer size as learnable probability distributions. XCTS uses differentiable 3D physical and timing models together with a two-stage optimization strategy. It first optimizes and materializes topology and tier assignment, then refines buffer sizing on the fixed tree and projects the result to legal library cells. We evaluate XCTS on seven OpenCores benchmarks using the ASAP7 technology and Pin-3D flow. Compared with the default Pin-3D CTS flow, XCTS reduces average latency, clock-buffer power, routed wirelength, and clock-buffer area by 12%, 43%, 4%, and 65%, respectively, while maintaining comparable skew. Compared with the M3D baseline, it reduces latency, skew, power, wirelength, and area by 31%, 22%, 44%, 29%, and 64%, respectively.

ABSTRACT. Clock skew scheduling (CSS) is a proven technique that improves timing by redistributing clock arrival times across flip-flops without modifying the underlying logic, and it is particularly attractive for 3D ICs, where the vertical freedom of the clock network offers greater room to realize a desired schedule. Yet, existing 3D CTS flows do not support skew-aware clock synthesis. In this paper, we propose an end-to-end framework that derives a useful skew schedule for 3D ICs and physically realizes it through 3D clock tree synthesis. Within this framework, to maximize the benefit of CSS, we first address its fundamental limitation: the improvement achievable through CSS is bounded by the minimum mean weight cycle (MMWC) of the timing graph. We therefore prioritize critical paths within such cycles during pre-CTS optimization, improving the MMWC slack and thereby expanding the schedule improvement CSS can deliver. Using the improved graph, we determine the target clock arrival time at each sink through CSS and synthesize a 3D clock tree that reflects these targets. Finally, we correct the residual between the scheduled and the actual clock latencies from place-and-route (P&R) by inserting a minimal set of delay elements, which is formulated as an optimization problem. Experimental results show that the proposed pre-CTS optimization improves the mean MMWC slack by 26%, while the resulting CSS-based schedule and its physical realization with 3D CTS improve the post-layout WNS by 33% on average.

ABSTRACT. Bit-line crosstalk has become a critical challenge as DRAM scales. It is especially pronounced in wafer-bonded DRAM, where the pe- riphery is stacked with the cell array so that bit-lines can be laid out as folded pairs and twisted—yet existing circuit- and process-level compensations lack a routing methodology matched to the timing of DRAM operation. We propose one that cancels this crosstalk by twisting in a folded bit-line while accounting for how each bit-line changes state—shielding or floating—over the course of an oper- ation. From this we derive an exposure-based cost that, under a pessimistic model of DRAM operation, measures how imperfectly the crosstalk onto each victim is canceled, and we minimize it with a two-stage router: twist planning, cast as a minimum-cost path over a bit-line permutation graph and solved by beam-search dy- namic programming, followed by layer assignment. Because twist- ing and layer assignment compete for the same crossing layer, both stages minimize this single cost. On a folded-bit-line channel, the framework raises the worst-case sensing margin from 41.81 mV to 70.11 mV on average—a 67.7% gain over an untwisted channel and 19.3% over twist-count minimization—and the cost tracks the simu- lated margin closely (𝑟 2 = 0.87) enough to stand in for a simulator at the routing level.

ABSTRACT. Neural Compact Models (NCMs) have emerged as an effective approach for bridging device characteristics and circuit-level evaluation for efficient Design-Technology Co-Optimization (DTCO). DTCO flows repeatedly invoke TCAD simulation, NCM training, and circuit evaluation until the target figures of merit are achieved. However, typical NCMs require a substantial number of TCAD data points across a wide range of voltage biases to achieve sufficient modeling accuracy. Consequently, computationally expensive TCAD simulation becomes a major bottleneck in the DTCO loop. This paper proposes the Process-Aware Adaptation (PAA) framework that substantially reduces the number of required TCAD simulation points while preserving high NCM accuracy. PAA exploits the incremental evolution of device characteristics along DTCO trajectories and integrates three key techniques: process-aware sparse sampling, low-rank parameter adaptation, and iterative weight inheritance. Together, these techniques enable efficient incremental adaptation of an existing NCM to successive device configurations. Experiments on realistic DTCO trajectories demonstrate that PAA achieves high accuracy at both the device level, with R^2 > 0.99, and the circuit level, with MAPE <2%. Compared with existing adaptation methods, PAA consistently provides higher modeling accuracy with reduced adaptation time. By incorporating PAA into the DTCO flow, the number of TCAD simulation points required for NCM can be reduced by 99%, resulting in an overall DTCO acceleration of 27 times.

ABSTRACT. Multi-FPGA prototyping systems enable emulation of large designs, but cut signals must traverse capacity-limited interconnects whose time-division multiplexing (TDM) ratios directly affect timing. Existing methods often assume homogeneous resources or fixed two-level topologies and therefore cannot consistently optimize static timing analysis (STA) minimum slack after legal physical assignment. In this paper, we present a timing-aware routing and heterogeneous TDM assignment framework for cable-aware multi-FPGA platforms. A TDM-ratio lookahead estimates both candidate-edge delay and the aggregate delay externality of TDM-ratio transitions on existing routed edges, while STA-guided refinement prioritizes critical edges. Continuous timing--capacity guidance is then converted into legal resource, ratio, cable, and channel assignments, followed by worst-path-driven post-optimization. A cable-aware typed graph represents hierarchy-dependent connectivity, resource libraries, and packing constraints for both stages. On the single-level platform, heterogeneous resources improve minimum slack by $7.0\,\mathrm{ns}$ on average over the homogeneous configuration. On the two-level platform, the proposed method improves minimum slack by $145.0\,\mathrm{ns}$ on average over the closest STA-aware baseline. On 36- and 90-FPGA platforms, the complete timing-aware flow improves minimum slack by $364.8\,\mathrm{ns}$ on average over its fully non-timing-aware variant.

ABSTRACT. Verification planning remains a major bottleneck in hardware design, requiring engineers to translate complex specifications into plans that determine coverage quality and bug-detection effectiveness. Despite demanding significant effort and domain expertise, this stage remains largely unaddressed by existing LLM-based verification approaches. We present Spec2Plan, a multi-stage LLM-powered framework that generates comprehensive, methodology-aware verification plans by decomposing the task into functional point extraction, testpoint synthesis, and global stress test construction. Spec2Plan integrates expert verification knowledge via retrieval-augmented generation and enforces coverage-oriented reasoning through carefully designed prompts. We evaluate plan quality using three metrics, namely specification coverage, corner-case identification, and methodology alignment, each grounded in external references and validated via cross-LLM evaluation. Across ten diverse OpenTitan designs, Spec2Plan consistently outperforms one-pass, budget-matched, and agentic baselines by a substantial margin. A mutation-based case study on the OpenTitan I2C bus monitor further demonstrates a 1.71× improvement in mutation kill rate with strictly additive coverage gains, surpassing expert-authored tests. These results establish Spec2Plan as a practical and scalable solution for high-quality verification planning.

ABSTRACT. Functional verification in IC/ASIC projects typically accounts for up to 60% of the entire development effort, consuming substantial resources. Existing methodologies remain poorly connected to the modern software ecosystem, limiting the use of efficient testing tools and the involvement of software developers. This gap mainly stems from low coding efficiency and limited support for software testing tools and developers. We present Toffee, a Python-based verification framework that addresses these challenges through three mechanisms: Asynchronous Function Modeling (AFM), which models hardware designs as software APIs; a hook-enabled reference model, which employs hooks for efficient communication; and a test-driven execution strategy, allowing test cases to be managed by software testing frameworks. Experiments show that Toffee can reduce lines of code in the verification environment by up to 86.31% and cut execution time by up to 89.69%. Moreover, most users can apply Toffee to real projects within 5.0–15.0 hours and integrate well with software testing tools.

ABSTRACT. A Boolean function admits structurally distinct implementations under semantics-preserving synthesis. Yet circuit graph neural networks (GNNs) are judged by native-task accuracy or positive-pair embedding similarity, neither of which establishes whole-circuit functional identity. We introduce synthesis-invariant functional identifiability, an end-to-end property requiring both invariance to resynthesis and discrimination against unrelated circuits. We audit ten representative circuit-GNN pipelines through source-equivalence retrieval across eight synthesis outcomes. The results reveal systematic task–identity decoupling: GNN4IP retains 93.2% of its original F1 score while achieving only 0.2732 mean reciprocal rank (MRR), whereas DeepGate3 maintains a transformed to original cosine similarity of 0.9247 but achieves only 0.0056 MRR. These findings show that robustness depends on the complete parser, graph abstraction, encoder, readout, and objective rather than neural architecture alone.

ABSTRACT. Machine learning (ML) accelerators have become essential hardware platforms for modern AI applications, with their functionality realized through Register Transfer Level (RTL) designs. Recent advances in large language models (LLMs) have demonstrated promising capabilities for generating RTL directly from natural-language design specifications, driving rapid progress in LLM-based RTL generation frameworks. As these frameworks continue to evolve, standardized evaluation becomes increasingly important for reliably assessing RTL generation capability. Existing RTL benchmarks, however, remain focused on general-purpose digital circuits and therefore do not adequately evaluate RTL generation for the specialized RTL modules found in modern ML accelerators. To address this gap, we present ML-AccelBench, a benchmark suite comprising 26 RTL generation tasks organized into five composition levels spanning the primary hardware functionality found in modern ML accelerators. Experimental evaluation using four state-of-the-art LLMs demonstrates that ML-AccelBench effectively differentiates contemporary RTL generation systems while revealing the unique challenges of ML accelerator RTL generation. ML-AccelBench provides a standardized and reproducible benchmark for evaluating LLM-based ML accelerator RTL generation frameworks.